-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
1/15
Review
RF MOSFET: recent advances, current status
and future trends
Juin J. Liou a,*, Frank Schwierz b
a School of EE and CS, University of Central Florida, Orlando, FL 32816 2450, USAb Fachgebiet Festk €oorperelektronik, Technische Universit€aat Ilmenau, Germany
Received 15 April 2003; accepted 6 May 2003
Abstract
Recent advances in complementary metal oxide semiconductor (CMOS) processing, continuous scaling of gate
length, and progress in silicon on insulator have stirred serious discussions on the suitability of metal-oxide semi-
conductor field-effect transistors (MOSFETs) for RF/microwave applications. This paper covers the recent advances
and current status of mainstream CMOS as the dominating technology in very large scale integration, future trends of
RF MOSFETs, and applications of MOSFETs in RF electronics. Aspects of RF MOSFET modeling are also ad-
dressed. Despite some lingering debates, the prospects for RF MOS with operating frequencies in the lower GHz range
are very promising.
2003 Elsevier Ltd. All rights reserved.
Contents
1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882
2. Evolution, current status, and future tends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883
2.1. Historical background of the MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883
2.2. Current status of MOSFET development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
2.2.1. Mainstream CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
2.2.2. RF MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1885
2.3. Future trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1886
2.3.1. Mainstream CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1886
2.3.2. RF MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887
3. Applications of MOS in RF electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888
4. Issues of RF MOSFET modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
4.1. Modeling of three-terminal RF MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890
4.1.1. BSIM model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
4.1.2. Philips MOS model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
4.1.3. EKV model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
4.1.4. Model comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1892
4.2. Modeling of four-terminal RF MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1892
* Corresponding author. Tel.: +1-407-823-2786; fax: +1-407-823-5835.
E-mail address: [email protected] (J.J. Liou).
0038-1101/$ - see front matter 2003 Elsevier Ltd. All rights reserved.
doi:10.1016/S0038-1101(03)00225-9
Solid-State Electronics 47 (2003) 1881–1895
www.elsevier.com/locate/sse
http://mail%20to:%[email protected]/http://mail%20to:%[email protected]/
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
2/15
5. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
1. Introduction
It is beyond anyones imagination as to how
the metal-oxide semiconductor field-effect transistor
(MOSFET) could have evolved in the past 40 years.
Moreover, it is very likely that a decade from now you
wont recognize a MOSFET as it is today. Although
some pundits have predicted that the evolution of
semiconductor technology to smaller dimensions will
slow down as the feature size hit the 0.1-lm mark, the
developments in fact have been speeding up recently.
The ITRS (International Technology Roadmap for
Semiconductors) [1] recently revised its projection for
the 2003 technology node from 120 nm (ITRS 1999
issue) to 100 nm (ITRS 2001, 2002 update), and the
targeted gate length for MOSFETs in high-performance
logic circuits for 2003 from 85 nm (ITRS 1999) to 45 nm
(ITRS 2001). Fig. 1 shows the evolution of the DRAM
capacity and the minimum MOSFET feature size (i.e.,
the gate length), together with the ITRS targets up to the
year 2016. Continuous MOSFET scaling and simulta-
neous increase of chip size led to more and more com-
plex integrated logic circuits with enhanced speed and
performance. For example, microprocessors manufac-
tured by Intel Corp. have seen the number of transistors
per chip increases from 2300 in 1971 (Intel 4004) to morethan 108 in 2003, as illustrated in Fig. 2. The clock fre-
quency of the processors, on the other hand, has been
increased from 1 MHz in 1971 (Intel 4004) to about 3
GHz in 2003 (Pentium 4).
This leads us to look at the issue of transistor speed.
If a processor shows a high clock frequency, it must
contain fast transistors. Indeed, continuous scaling not
only made the MOSFETs smaller, but also much faster.
Roughly speaking, transistor speed is inversely propor-
tional to the gate length. In the past, MOSFETs have
been considered as ‘‘slow’’ devices. Several reasons
contributed to this conviction. First, the electron mo-
bility, a measure of how fast the free electrons can move
in a semiconductor, in Si is by nature lower than inGaAs and other compound semiconductors. Second, the
inversion channel of a MOSFET is located very close to
the Si/SiO2 interface, thereby subjected to the effects of
interface roughness, crystal imperfections, and interface
traps. As a result, the mobility of free electrons traveling
in the inversion channel is further degraded. Fig. 3
1970 1980 1990 2000 2010 2020
1T
1G
1M
1k M i n i m u m F
e a t u r e S i z e , µ m
M e m o r y B i t s p e r
C h i p
Year
0.01
0.1
1
10
100
0.001
DRAM
Processors 9nm
22nm
ITRS 2001 projection
Fig. 1. Trends and projections of memory bits per chip and
minimum feature size of MOSFETs for DRAM and micro-
processors (after [1] and [23]).
1970 1980 1990 2000 201010
3
104
105
106
107
108
109 ItaniumISSCC 2003
ItaniumISSCC 2002
Pentium 4Pentium III
Pentium IIPentium
486
286
386
8086
8080
80084004
T r a n s i s t o r s p e r c h i p
Year of introduction
Fig. 2. Evolution of transistors per chip of Intel microproces-
sors.
0.01 0.1 110
2
103
2
Universal mobility curve
N A 3.9x10
15 cm
-3 N
A 2.0x10
16 cm
-3
N A 7.2x10
16 cm
-3 N
A 3.0x10
17 cm
-3
N A 7.7x10
17 cm
-3 N
A 2.2x10
18 cm
-3 E f f e c t i v e m o b i l i t y , c m
2 / V s
Effective field, MV/cm
Fig. 3. Effective electron mobility in the channel of MOS
devices.
1882 J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
3/15
shows the effective electron mobility in the MOS channel
versus the vertical electric field (i.e., the field caused by
the gate voltage). It can be seen that the mobility de-
creases with increasing field, due to the fact that a larger
field, i.e. a larger positive gate voltage, will attract the
electrons in the inversion layer more strongly to the Si/
SiO2 interface and thus induce more interface scatteringon the electrons. Table 1 compares the low-field electron
mobilities in a Si MOS inversion channel, bulk Si, and
bulk GaAs (the doping concentration is 1017 cm3 in all
cases).
Besides the low-field mobility in MOSFET channels,
a second reason for the inferior MOSFET RF perfor-
mance in the past was the relatively large gate length.
In the early 1980s, the gate length of production-
stage MOSFETs was in the range of 1.5–2.5 lm, while
RF GaAs metal-semiconductor field-effect transistors
(MESFETs) with gate lengths between 0.25 and 0.5 lm
were quite common and commercially available.
Thanks to the aggressive feature size reduction in the
past few years, however, MOSFETs are now qualified as
RF devices. Today, the MOSFET gate length is com-
parable or even smaller than that of III–V RF FETs.
Currently, deep-submicrometer complementary metal
oxide semiconductor (CMOS) processes typically reach
several tens of GHz cutoff frequency f T and show rela-
tively low noise figures, making them a serious alterna-
tive to the traditional III–V compound devices [2–4]. In
addition, MOSFETs offer very large scale integration
(i.e., the possibility to realize systems-on-chip) and high
reliability. It should be noted that the progress toward
MOSFETs capability for RF operation is a spin-off from the developments of very large scale integration
(VLSI) and is based on the tremendous research and
development efforts of the Si VLSI chipmakers. Much of
the advance achieved in increasing the switching speed
of MOSFETs for fast logic circuits has been adopted for
RF MOSFETs. Fig. 4 shows the evolution of the market
share of the different semiconductor technologies. Note
that in the early 2000s about 90% of the market belongs
to CMOS and MOSFETs! Since the R&D budgets for
enhancing the performance of a certain semiconductor
technology are normally related to its market share, one
can get an idea on the tremendous amounts of money
spent on the development of modern and future MOS-FETs.
In this paper, we will start with a brief history of the
MOSFET. Because RF MOSFET development bene-
fited from the advances in Si VLSI mentioned above, we
will address both mainstream CMOS and RF MOS-
FETs. Issues discussed include the prospects and future
trends of RF MOSFETs, combination of MOSFETs
with SiGe heterojunction bipolar transistors (HBTs,
SiGe BiCMOS), and applications of MOSFETs in RF
electronics. Finally, important issues pertinent to RF
MOSFET modeling will be addressed.
2. Evolution, current status, and future tends
2.1. Historical background of the MOSFET
The first transistor, nowadays known as a MESFET,
was proposed in a patent filed by Lilienfeld in 1926 [5]
who, two years later, presented the idea of the depletion-
mode MOSFET [6]. These concepts were made possible
by Lilienfelds understanding of conductivity modula-
tion by a transverse electric field, which he repeatedly
used to describe signal amplification of the transistors in
the patents. However, it is still not known if Lilienfeldever made a working, amplifying transistor.
The notion of the inversion-mode MOSFET was
proposed by Heil in 1935 [7]. Nevertheless, the first
MOSFET was not fabricated until 1960 by Kahng and
Atalla [8,9]. The immense delay between the idea and the
fabrication was due to the technical difficulties to obtain
a good oxide and the lack of fundamental and basic
semiconductor notions. After World War II, researchers
at Bell Labs were trying unsuccessfully to make field
effect devices and apparently they were not aware of the
previous work by Lilienfeld and Heil. Ironically, this
unsuccessful research on field-effect devices led to the
Table 1
Comparison of the low-field mobility in a Si inversion channel,
bulk Si, and bulk GaAs
Material
Si inversion
channel
Bulk Si Bulk GaAs
Low-field
mobility, cm2/V s
6550 700 4700
The doping concentration is 1017 cm3 in all cases.
Fig. 4. Market share of different semiconductor technologies.
J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895 1883
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
4/15
birth of the bipolar transistor [10–14]. Using the ideas of
the ‘‘point contact transistor’’, Shockley completed the
description of the bipolar junction transistor on 23
January 1948 and filed it for a patent on 26 June 1948
[15]. Shockley and his two Bell Labs colleagues, Brattain
and Bardeen, received the Nobel Prize in Physics in 1956
for the ‘‘invention of the transistor.’’ Soon the bipolartransistor became the dominating device in semicon-
ductor electronics and maintained this position for more
than two decades.
Interests in the MOSFET were resuscitated in 1960
by Kahng and Atalla [8,9], who presented the first suc-
cessful realization of a silicon inversion-channel MOS-
FET using thermally grown oxide for the gate insulator.
The MOSFET dramatically increased its importance
three years later when Wanlass and Sah invented the
CMOS circuit [16–18]. Due to their compactness and
low power dissipation, MOSFETs have been the most
widely used semiconductor device since the 1980s (seeFig. 4).
It is understandable that the evolution of integrated
circuits has always followed but somewhat behind that
of semiconductor devices. In 1959, Kilby fabricated a
flip-flop from a single chip of germanium using gold
wires for interconnections. This is called today a hybrid
integrated circuit and is the predecessor of the mono-
lithic integrated circuit. Kilby, who received the Nobel
Prize in Physics 2000 for the ‘‘invention of the integrated
circuit’’, gave in 1976 [19] his personal account about his
previous invention of the integrated circuit at Texas
Instruments. The development of the planar technol-
ogy at Fairchild in the late 1950s allowed Noyce to
invent in 1959 [20] the monolithic silicon integrated
circuit. Moore, a cofounder of both Fairchild and Intel,
predicted in 1965 [21] that the number of devices per
integrated circuit would increase exponentially with in-
creasing time. This astonishing prediction, which has
been named the Moores Law [22] and is still valid
today, was based on only five data points available from
Fairchild.
While most integrated circuits fabricated during the
1960s and 1970s were based on bipolar transistors,
MOSFET-based circuits gained importance and took
over the leading role in the early 1980s.
2.2. Current status of MOSFET development
2.2.1. Mainstream CMOS
The basic structure of MOSFETs, shown in Fig. 5
consisting of a single gate, a semiconducting substrate
(frequently called body or bulk), and heavily doped
source and drain regions, has not changed much in the
past 20 years [23]. Only the dimensions and other fea-
tures have been scaled down continuously to meet the
demands of higher speed and increased compactness. A
somewhat significant modification to the MOSFET
during the last 10 years was the introduction of the sil-
icon on insulator (SOI) technology, where the transistor
body is separated from the semiconducting wafer by an
insulating layer. The gate length, which is directly re-lated to the effective channel length, is a main feature
controlling the MOSFET performance. Reducing the
gate length, however, requires the scaling of other fea-
tures such as the oxide thickness, drain/source junc-
tion depth, and substrate doping density [24–26]. For
example, when the gate length is reduced, the oxide
thickness needs to be reduced so that the gate can have a
better control of the channel inversion and can give rise
to a larger oxide capacitance. Typically, the gate is made
of a heavily doped polysilicon, and silicides are fre-
quently deposited underneath the drain/source contacts
to reduce the contact resistance.
Unfortunately, undesirable effects called short-
channel effects occur in modern deep submicrometer
MOSFETs. To alleviate such effects, several additional
features have been added to the basic MOSFET struc-
ture. For example, to minimize hot-carrier effects due to
the high electric field near the drain junction, lightly
doped drain/source (LDD) regions are implemented in
MOSFETs [27]. Another important phenomenon asso-
ciated with the short-channel effects is the threshold
voltage roll-off (i.e., threshold voltage starts to decrease
when the channel length is reduced below a critical
value). This can be effectively eliminated by the use of
halo or pocket-implant MOSFET [28].Many foundries, including IBM, Intel, TSMC,
Philips, Motorola, and LSI Logic, are gearing up to
start volume production of 100- to 90-nm technology
node processes as early as 2003. In these processes, gate
lengths can be selectively etched down to about half this
technology node. In fact, Intels prototype 90-nm pro-
cess has already produced functional circuits with
MOSFET gate length of 50 nm.
The primary aim of the entire research and devel-
opment efforts in VLSI electronics has been to decrease
the cost per logic function and per stored bit, and si-
multaneously to increase the switching speed of logic
p-type substrate
n+ n+
Poly Si Oxide
Source Gate Drain
Inversion channel (2DEG)
Fig. 5. Schematic of a typical bulk MOSFET structure.
1884 J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
5/15
gates. So far this aim has in fact been achieved and re-
sulted in new generations of microchips containing more
transistors and having a higher clock frequency than
their predecessor.
2.2.2. RF MOSFET
An important measure of RF transistor is the cutoff
frequency f T. This is the frequency at which the small-
signal current gain h21 of the transistor rolls off to unity
(i.e., 0 dB). Fig. 6 shows the cutoff frequency versus the
gate length of n-channel MOSFETs, with the upper limit
as of May 2002 indicated [23]. For todays 50- to 100-nm
gate-length MOSFETs, the cutoff frequency can reach
an astonishing 200 GHz [29,30]. Applying a frequently
used rule of thumb that the cutoff frequency should be
around 10 times the transistors operating frequency,
one could use these devices to design integrated circuits
operating up to 20 GHz, an operating frequency higher
than that for the great majority of modern RF elec-tronics. This, however, is only half of the picture because
a high cutoff frequency is not the only requirement for a
good RF transistor. Other figures of merit have to be
considered as well. For example, a high maximum fre-
quency of oscillation f max which is the frequency at
which the transistors unilateral power gain U rolls off to
unity (i.e., 0 dB), is often desirable. Small noise figure
NF min and high output power P out are also critical for RF
noise and power applications, respectively.
Properly designed III–V RF field-effect transistors
(MESFET and HEMT) show comparable f max and f T,
but typically with f max > f T. The situation is different forSi MOSFETs. For these devices, one could either realize
short-channel transistors for high f T but substantially
lower f max or long-channel transistors for rather low f Tbut higher f max. Table 2 illustrates such a trade-off using
two Si MOSFETs reported in 1998 and 2000. The trade-
off resulted from the fact that a very high f max can only
be achieved with transistors having a high f T and a low
gate resistance RG. For III–V FETs, metal gates with
multi-finger mushroom structures are frequently used to
minimize RG. The gates of Si MOSFETs are made of
polysilicon, which has a much higher resistivity than a
metal. Furthermore, for MOSFETs in digital applica-
tions, multi-finger and mushroom gates are not com-
mon. Reducing RG is imperative for RF MOSFETs
because RG not only limits the power gain attainable at a
certain frequency (and thus f max), but also sets a lower
limit to the minimum noise figure.
There are several means to minimize the gate resis-
tance of Si MOSFETs:
• deposition of silicides on top of the polysilicon gate,
• metal overgates on top of the polysilicon gates,
• multi-finger gates with small finger width.
Recently, considerable progress on increasing the
maximum frequency of oscillation of Si MOSFETs has
been made. Fig. 7 shows the maximum frequency of
oscillation as a function of gate length for Si MOSFETs
reported up to 2001 [33]. Highlights are the 50-nm SOI-
MOSFET [34] with an f max of 193 GHz ( f T 178 GHz)
and the 80-nm SOI-MOSFET [35] with f max of 185 GHzand f T of 120 GHz. In Fig. 8, the reported maximum
frequency of oscillation of Si MOSFETs is plotted ver-
sus the cutoff frequency. Considerable improvement of
f max since January 2001 can be clearly seen.
Because of the presence of Si/SiO2 interface, MOS-
FETs are noisier than other RF transistors. Reported
0.1 110
100
500
0.05
Empirical Upper Limit Experimental Data
C u t o f f F r e q u e n c y , G
H z
Gate Length, µm
Fig. 6. Reported cutoff frequency versus gate length of MOS-
FETs [23].
Table 2
State of the art of RF MOSFETs in terms of f T and f max re-
ported in late 2000s
LG, nm f max, GHz f T, GHz Reference
80 60 140 [31]
500 66 25 [32]
0.1 110
100
300
0.04
Reported up to Dec. 2000 Reported in 2001
M a x . F r e q u e n c y o f O s c i l l a t i o n , G H z
Gate Length, µm
Fig. 7. Reported maximum frequency of oscillation versus gate
length of MOSFETs [33].
J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895 1885
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
6/15
minimum noise figures NF min of experimental Si MOS-
FETs are given in Fig. 9 [23]. Only noise figures up to
about 15 GHz had been reported, and MOSFETs be-
come too noisy at even higher frequency for practical
microwave applications.Due to the low breakdown voltage, the standard
MOSFET structure, shown in Fig. 5, can only be used in
relatively low power applications. High-power micro-
wave amplifiers used in the base stations for mobile
communication systems, however, are designed for max-
imum operating (and thus breakdown) voltage to deliver
maximum output power. For such applications, a dif-
ferent MOSFET structure called the LDMOSFET (lat-
erally-diffused MOSFET) is frequently used [23]. The
cross-section of a typical high-power LDMOSFET is
shown in Fig. 10. It consists of a pþ-Si substrate on top
of a lightly doped p
-layer grown epitaxially. While the
nþ-source region extends to the gate, the nþ-drain region
is spatially separated from the gate. The conductive
connection between the nþ-drain and the channel region
underneath the gate is realized by an n-LDD (lightly
doped drain) region which is frequently called the
drift region. This is the main region contributing to a
high breakdown voltage. Typically, the gate length of
LDMOSFETs is in the range of 0.3–1.0 lm and the gate
oxide is several ten nm thick. As such, the technology,
especially the lithography and the gate oxide deposition,
of the LDMOSFET is much more relaxed than that of
the small signal microwave MOSFET. Depending on the
specific designs, typical f T of LDMOSFETs is around 5–
15 GHz, and the drain-to-source breakdown voltage
BVDS is around 20–40 V.
2.3. Future trends
2.3.1. Mainstream CMOS
The road to advances beyond a decade into the
future has always been obscure and has stimulated
much speculation as to where miniaturization must
end. Thus far, new ideas have regularly met the chal-lenges posed by new problems. One thing for sure is
that the downscaling will continue at least for a couple
of years. The ITRS targets for the year 2016 for high-
performance logic circuits (microprocessors in desktop
computers) are a physical MOSFET gate length (i.e.,
the transistors gate length after all fabrication steps are
finished) of 9 nm and microprocessors with a chips size
of 140–280 mm2 containing more than 3 billion tran-
sistors. To reach this target and ensure that the tran-
sistor still operates satisfactory, however, requires many
changes and innovations. The most likely changes are
[39]:
0 50 100 150 200 2500
50
100
150
200
250 Reported Jan. 2001 - March 2003 Reported by Dec. 2000
f m a x , G
H z
f T, GHz
Fig. 8. Reported maximum frequency of oscillation of MOS-
FETs versus the cutoff frequency [33].
1 100.0
0.5
1.0
1.5
2.0
(b)
(c)
Exp. Data MOSFET Empirical Lower Limit
(a)(a)
200.6
M i n i m u m N o i s e F i g u r e , d B
Frequency, GHz
Fig. 9. Measured data of minimum noise figure versus fre-
quency, with four lowest figures indicated with (a), (b), and (c)
reported in [36–38].
Gate
Source
p substrate
p body
p epi
DrainSource
n
n LDD
p sinker
-
+
-+
+
n+
Fig. 10. Schematic cross-section of a typical LDMOSFET
structure [23].
1886 J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
7/15
(a) To increase the mobility and improve performance,
silicon will be mixed with a semiconductor like ger-
manium to produce a strained monocrystalline sili-
con layer at the wafer surface that lets electrons
move faster.
(b) To reduce the gate leakage current, gate oxide will
be made of materials with higher dielectric constantthan todays silicon dioxide.
(c) To reduce the gate resistance and improve channel
control, gates will be made of metals, instead of
polysilicon.
(d) For better control of MOSFETs on and off states
and reduce power consumption, more than one gate
will be used.
The technology of putting a Si strained layer on a
silicon wafer seems to be closest to commercialization.
The process is as follows. Germanium atoms replace
some of the silicon atoms near the wafers surface, then a
thin layer of silicon is grown on top of this SiGe layer.
Because Ge atoms are larger than Si atoms, the distance
between the atoms in the SiGe layer is larger than that in
pure Si. When the top Si layer is grown, its atoms line up
with the SiGe atoms below, and it becomes strained in
the two directions parallel to the plane of the wafer.
Finally, MOSFETs are fabricated in this top strained
silicon layer. The tensile strain forces in the strained
silicon layer change the energy band structures. As a re-
sult, the effective mass of electrons and holes is reduced
and the phonon scattering is decreased. Because of these,
much higher free-carrier mobilities in Si strained layer
are possible. Several research groups reported a 60%
increase in the mobilities [40].
As mentioned earlier, the oxide thickness decreases
with decreasing gate length. For a 100-nm process, the
oxide thickness should be around or even less than 1.5
nm. Such a thin oxide allows for a considerable amount
of current to flow from the gate to channel, thereby
increasing the power consumption and degrade the
functionality of MOSFETs. The solution to this prob-
lem seems to be straightforward––replace the silicon
dioxide with a material having a higher dielectric con-
stant k . A gate over a thick high-k material can control
the channel just as effective as one over a thinner low-k material. Consequently, using a high-k dielectric allows
one to increase the oxide thickness and reduce the gate
leakage. Promising candidates for high-k dielectrics are
oxynitrides and hafnium dioxide.
Todays MOSFETs have heavily doped polysilicon
gates. When the gates are biased, a depletion region
forms near the interface of polysilicon gate and oxide
layer. Since the oxide is very thin, this depletion region
in effect increases considerably the thickness of the di-
electric and therefore reduces the effectiveness of the
controlling mechanism of the gate. The second draw-
back of polysilicon gates is, as mentioned above, their
relatively high series resistance. Metal gates can mini-
mum these two problems. But before choosing a suit-
able metal, factors such as thermal stability and work
function need to be considered. Recently, ruthenium–
tantalum alloy has been suggested as a possible gate
metal, which has the advantage of adjustable work
function to meet the required threshold voltage of MOSFETs [41].
In the past few years, more and more researches have
been devoted to investigating innovative MOSFETs
having more than one gate to enhance the control
of ultra-small MOSFETs. Several vertical and planar
structures have been suggested and tested, and the
frontrunner is an approach called the double-gate
MOSFET under development by many semiconductor
companies [42–44]. In Fig. 11, two double-gate MOS-
FET versions are shown. On the left is a planar double-
gate transistor investigated by IBM researches, and the
other is a vertical double gate FET commonly calledFinFET favorited by AMD, TSMC, and others. The
FinFET is built by etching the silicon layer of an SOI
wafer to form narrow vertical fins on the wafer surface.
The narrow fin forms the channel, the source and drain
are formed at end of the fin, and the gate drapes over
both sides of the fin (i.e., two gates). Since the fin is made
extremely thin, no region of the fin escapes the influence
of the gate, and no leakage path for the carriers to flow
between the source and drain when the device is off.
Currently, Intel is pushing for a modified FinFET ver-
sion called the Trigate FET. Here, an almost quadratic
cross-section of the fins is striven for and the gate sur-
rounds the fin from the vertical surfaces and from the
top. Thus, there are three gates controlling the current
path in the fin. Such a device is schematically shown in
Fig. 12.
2.3.2. RF MOSFET
The advanced MOSFET concepts described above
are focused on developing transistors for high-level in-
tegrated circuits, such as microprocessors, ASICs, etc.
How they will be used for RF MOSFETs is still unclear.
Fig. 11. Schematic of a planar double-gate MOSFET (left) and
a vertical double-gate MOSFET (FinFET, right).
J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895 1887
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
8/15
Currently, the preferred RF MOSFET structures are
conventional single-gate bulk or single-gate SOI MOS-FETs. There is no doubt, however, that RF MOSFETs
will benefit from the progress made in Si VLSI. Besides
the MOSFET, another important issue for RF elec-
tronics is good passive on-chip components, i.e. capac-
itors, inductors, and resistors [45], which can be made
using the CMOS process.
Recent progress on the SiGe HBT, although in
principle being a competing device, will help to expand
the market share of MOSFETs in RF electronics. SiGe
HBTs offer excellent RF properties (high speed, i.e. both
high f T and f max and low noise figure), as evidenced by
the maximum frequency of oscillation versus cutoff fre-
quency shown in Fig. 13 [33] and the noise performancegiven in Table 3.
During the last few years, considerable efforts have
been devoted to realize SiGe HBTs from standard
CMOS processes [48–51]. This makes pure Si-based RF
ICs possible, where SiGe HBTs are used in the critical
parts which demand RF performance (such as frequency
and noise performance) while Si MOSFETs are em-
ployed in other components. Fig. 14 shows the f T and
f max values obtained from the CMOS-compatible SiGe
HBTs as a function of emitter width [33]. An interestingfeature of SiGe HBTs is the fact that both f T and f maxbetween 50 and 100 GHz can be realized with an emitter
width larger than 0.4 lm. This is different from the RF
Si MOSFET, which requires a much smaller gate length
to reach such high frequency limits.
3. Applications of MOS in RF electronics
In the following, civil RF applications that currently
have large market volumes or are expected to create
mass markets in the near future are described. Fur-thermore, RF MOSFET applications in wireless com-
munications are discussed.
The operating frequencies of civil RF applications
can range from a few hundreds MHz to 100 GHz, but
most systems having mass markets operated at fre-
quencies below 6 GHz. The number of units sold in
these markets is in the order of millions per year. Table 4
summarizes various applications and their frequency
spectrums.
Examples for civil communications systems in the
higher frequency range are the Hiperlink system (17
GHz), direct-to-satellite communication (20 GHz down
Fig. 12. Schematic of a Trigate MOSFET.
0 100 200 300 4000
100
200
300
400
IHP 2002
IBM 2002
Jan. 2000 - Dec. 2002
Before 2000
f m a x ,
G H z
f T , GHz
Fig. 13. Reported maximum frequency of oscillation of SiGe
HBTs versus the cutoff frequency [33].
Table 3
State of the art noise performance of SiGe HBTs
Frequency, GHz NF min, dB Reference
2 0.14 [46]
4 0.18 [46]
10 0.2 [47]
26 1.5 [47]
0.0 0.2 0.4 0.6 0.8 1.00
50
100
150
200
250
f T
f max
IHP 2002
IHP 2002b
aa
a
IBM 1999IHP 1999
IHP 2001
IBM 1999Lucent 1999
IBM 2001
a Conexant 2001b Hitachi 2002
F r e q u e n c y ,
G H z
Emitter width, µm
Fig. 14. Reported f T and f max of SiGe HBTs versus the emitter
width [33].
1888 J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
9/15
link, 30 GHz up link), local multi-point communication
services (27.5–29.5 GHz), millimeter-wave digital radio
systems (23 and 38 GHz, and possibly 12, 15, 18, 26
GHz). Another field of civil microwave applicationsis automobiles. The envisaged applications include the
global positioning system (1.8 GHz), collision avoidance
radar (operating at 77 GHz), vehicle identification,
traffic management, and others. Certain radar and sen-
sor applications will operate around 94 GHz.
Cellular phones are no doubt the most popular
wireless communication system currently in use. Such a
system can be divided into the user part (handset) and
the infrastructure part (base stations). The user part
consists of a receiver and a transmitter, and their design
considerations are discussed below.
In the receiver part of a handset, low-noise RF tran-
sistors are used to amplify the incoming signals. As in
any low-noise amplifier, the use of low minimum noise
figure transistors is desired. The noise requirements for
the RF devices for this application are, however, not as
stringent as those for satellite communications. In wire-
less communications, the receiver ‘‘feels’’ the noise of the
whole environment, which is interference dominated,
whereas in satellite communications the signal comes
from the sky with less background noise [52]. Conse-
quently, for wireless communications, the noise pro-
duced intrinsically in the RF devices is somewhat
negligible comparing to that from the noisy environment.
GaAs MESFETs and Si bipolar transistors as the tra-ditional low-noise transistors used in wireless commu-
nications, but the use of MOSFETs, possibly merged
with SiGe HBTs using a low-cost BiCMOS process, has
become a realistic option.
Another requirement for the handset is the reduction
of power consumption. At present, a supply voltage of
3 V has been established as a standard. To deliver a high
output power combined with a high efficiency at a lim-
ited supply voltage of 3 V, RF power transistors pos-
sessing a large on-current and a low on-resistance are
required in the transmit section of the handset. MOS-
FETs are not the best devices for this application due to
the relatively low output power density. GaAs transis-
tors (especially GaAs HBT) dominate this application.
To date, the dominant power RF transistor used in
base stations of wireless communications systems with
operating frequencies up to 2.5 GHz is the Si LDMOS-
FET, which in the last several years has replaced all
other competing Si and GaAs transistors [53]. Si LD-MOSFETs combine the advantages of moderate cost,
high reliability and extremely high output power.
Aside from cellular phones, several other civil RF
systems with operating frequencies below 20 GHz are
potential fields for the application of RF MOSFETs as
well. For example, Bluetooth, in which the requirements
on transistors RF performance are quite moderate, is
predestinated for RF MOSFETs. In fact, all-MOS
Bluetooth products are already commercially available
[54]. For other applications below 20 GHz but with
more stringent requirements concerning RF perfor-
mance, the combination of SiGe HBTs and CMOS(SiGe BiCMOS) is currently a heavily discussed possi-
bility in industry [55,56].
Although RF MOSFETs seem to fulfill most of the
performance requirements for civil RF systems with
operating frequencies up to 6 GHz, debates still existed
as to whether such devices will find widespread appli-
cations in the market [57]. Nevertheless, there is a
growing belief that the importance of MOSFETs in RF
applications will increase in the near future and for
many years to come.
4. Issues of RF MOSFET modeling
MOSFET has four terminals: drain, source, gate, and
body. The number of free carriers in the channel is
mostly controlled by the field induced from the gate
voltage, but a change in the body potential can also
affect the number of channel carriers. At low frequen-
cies, the impedance of the junction capacitance is so
large that the substrate impedance may not be seen from
the drain terminal, and a MOSFET can be modeled as a
three-terminal device. In RF MOSFETs, however, the
distributed R – C network composed of the depletion
capacitances and the substrate resistances, and the accurrent passing through this R – C network, make the
concept of three-terminal device invalid [58].
It is much more difficult to explain and predict the
behavior of a four-terminal device than that of a three-
terminal one. A three-terminal device can be treated as a
two-port network, where four complex numbers are
sufficient to characterize the device. On the other hand,
nine complex numbers are required to characterize a
three-port network, such as a four-terminal device.
Unfortunately, there is no established measurement
technique to perform on-wafer three-port S -parameter
measurements. Even if three-port measurements are
Table 4
Civil RF systems operating below 6 GHz
Application Operating frequency
Pagers 0:2; . . . ; 0:9 GHz
Cellular phones 1st generation (1G) 0:8; . . . ; 0:9 GHz
Cellular phones generation 2 and 2.5
(2G, 2.5G)
0:9; 1:4; 1:8; . . . ; 1:9
GHz
Cellular phones generation 3 (3G) 0.9, 1.8, 2.6 GHz
Global positioning system (GPS) 1.8 GHz
Wireless area networks (WLAN) 2.4 GHz
Bluetooth 2.4 GHz
HiperLAN2 5 GHz
802.11a Local Area Network (Wi–Fi) 5:15; . . . ; 5:825 GHz
J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895 1889
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
10/15
possible, many bias combinations for the ac character-
istics will need to be considered, and the measurements
and parameter extractions become impractical and too
time consuming.
In spite of these problems, intensive efforts have been
devoted to RF MOS modeling and parameter extrac-
tion. In the following, we will first briefly introduce thestrategies for RF modeling and parameter extraction of
two-port networks. Then the modeling of four-terminal
MOSFETs based on the macro-modeling approach will
be discussed. Only the approaches and concepts will be
given in this section, as the detailed information of
device physics and RF modeling can be found in the
literature.
4.1. Modeling of three-terminal RF MOSFET
We will first discuss RF III–V FET models, as these
models have been developed in the past to address high-frequency issues and can be readily extended for RF
MOSFETs.
Only when both a proper model and a good set of
model parameters are used together can one obtain ac-
curate and meaningful circuit simulation results. Thus it
is imperative to develop a well-constructed model and its
parameter extraction method in order to effectively de-
scribe and predict the device characteristics. A model is
normally represented by an equivalent circuit consisting
of elements such as resistances, capacitances, induc-
tances, and current sources. These elements are de-
scribed by mathematical equations. All of the constants
and coefficients associated with the equations, called the
model parameters, ideally should have physical origins.
However, some of them may result from empirical ex-
periences to enhance the model accuracy. The model
parameters need to be determined from extraction
techniques based on experimental data from MOSFETs
measured at different biased condition and frequencies.
At low frequencies, these measurements are usually done
utilizing Z , Y , or H matrices. This is because it is easier
to measure the voltage or current with open or short
circuits. However, there are many problems with this at
high frequencies. By terminating the port with a cable of
characteristic impedance, the S -parameter techniquemeasures power waves propagating into and being re-
flected from the device and thus is the easiest and the
most reliable way to characterize high-frequency net-
works.
A conventional small-signal equivalent circuit of III–
V FETs is shown in Fig. 15 [59]. This equivalent circuit,
which consists of capacitances C , inductances L, resis-
tances R, and a current source involving transconduc-
tance g m and delay time s, can be divided into two parts:
(1) Intrinsic elements: g m, g ds, C gs, C gd, C ds, Ri, and s,
which are functions of biases.
(2) Extrinsic elements: Lg, Rg, C pg, Ls, Rs, Rd, C pd, and Ld, which are independent of biases.
The extrinsic elements are first determined from data
measured at cold-FET conditions. Then, de-embedding
the extrinsic elements yields the values of intrinsic ele-
ments.
Small-signal simulation based on the model in Fig.
15, unfortunately, cannot be used to reliably extrapolate
the true large signal performance of RF MOSFETs.
This is due to the fact that the small signal model, while
simple and straightforward, does not guarantee charge
conservation in a semiconductor device [60]. Charge
conservation is absolutely required for accuracy and
convergence of circuit simulation. This means that after
controlling voltages are allowed to vary and then re-
turned to their original values, the values of the current
and charge should remain unchanged regardless of the
variation history. As a result, accurate RF MOSFET
modeling should be based on the large signal model. As
the equivalent circuit in Fig. 15 does not contain a
complete set of intrinsic capacitances, we cannot build a
large-signal model assuring charge conservation from
this small-signal model. The equivalent circuit of a
typical large signal model for III–V FETs is illustrated in
Fig. 16. It composes of nonlinear intrinsic componentssuch as the current and charge sources, rather than lin-
earized intrinsic components such as resistances and
capacitances. Based on this, a more accurate charge-
conserving small-signal model can then be developed for
RF simulation [61].
The Shichman–Hodges model, normally refer to as
level 1 MOSFET model, has simple equations, yet it is
only valid for long-channel devices and does not have
charge conservation. In the past 20 years, such a model
has evolved into the following three mainstream, public-
domain models: BSIM from UC Berkeley [62], MOS
model from Philips Laboratories [63], and EKV model
Lg R g C gd R d Ld
C pg C gs
R i
R s
Ls
g ds C dsg me
-jwt C pd
V
Intrinsic device
Fig. 15. Equivalent circuit of conventional small-signal model
for three-terminal FETs.
1890 J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
11/15
[64]. These models are basically large signal ones, so the
issue of charge conservation does not present a problem.
The BSIM, MOS, and EKV models have been imple-
mented in several commercially available SPICE simu-
lators, as illustrated in Table 5.
An overview and brief comparison of the three
models are presented below.
4.1.1. BSIM model
As illustrated in Table 6, the BSIM model has gone
through several improvements and versions in the past,
starting from the Berkley Level-I model for 5.0-lm
MOSFETs to the latest BSIM4 for 0.1-lm MOSFETs.
Many physical effects have been added during the BSIM
evolution. For example, the BSIM3 was developed
from a coherent quasi-two-dimensional analysis of the
MOSFET, and it takes into account the effects of many
device and process variables for good model scalability
and predictability.
4.1.2. Philips MOS model
MOS11 model is the latest version in Philips MOSmodel family, but MOS9 model is still being used in the
industry. Such models were developed intended for the
simulation of circuit behavior with emphasis on analog
applications. The models give a complete description of
all transistor-action related quantities, such as nodal
currents and charges, noise-power spectral densities, and
weak avalanche currents. The equations describing these
quantities were based on the gradual channel approxi-
mation with a number of first-order corrections for
small-geometry effects. The consistency is maintained by
using the same carrier-density and electric-field expres-
sions in the calculations of all model quantities.
4.1.3. EKV model
EKV model is a relatively new model, which is just
beginning to be implemented in some commercial circuit
simulators. Two EKV versions existed: the old EKV
v2.6 and more recent EKV v3.0. The model is somewhat
unique in that it uses the substrate contact, rather than
the source contact, as the voltage reference. This greatly
simplifies the description of the MOS device behavior
and has given the EKV model a greater hope of fun-
damentally eliminating the asymmetry problems in the
source referencing models. As a result, the complexity of
the model structure is greatly reduced, with a small
number of physically relevant parameters. Despite the
simplicity, the EKV model is quite accurate and gener-
ates continuous second derivatives. Furthermore, the
Qgs Qgd I gd I gs
I ds
Qds
Ls R s R s Ls
Lg
R g
G
S D D
Fig. 16. Equivalent circuit of large-signal model for three-
terminal FETs.
Table 5
Availability of BSIM, MOS, and EKV models in commercially available software tools
BSIM3 BSIM4 MOS9 MOS11 EKV
HSpice Available Available Available Available Available
Spectre Available Available Available Available
SmartSpice Available Available Available Available Available
Pspice Available Available
Table 6
Comparison of the various BSIM versions
Model Geometry (lm) Ids Subthreshold Rout Scalability
Berkeley Level-1 5.0 Poor NA Fair Poor
Berkeley Level-2 2.0 Poor Poor Fair Fair
Berkeley Level-3 1.0 Fair Poor Poor Poor
BSIM-1 0.8 Good Fair Poor Fair
BSIM-2 0.25 Good Good Fair Fair
BSIM-3 0.15 Good Good Good Good
BSIM-4 0.1 Good Good Good Good
J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895 1891
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
12/15
EKV model is built around a hierarchal structure which
allows for a clean link between hand calculations (using
a subset of the model equations) and the full fledged
circuit simulation. This model is also the first to intro-
duce parameters to specifically address the issue of MOS
mismatch.
4.1.4. Model comparisonTable 7 summarizes the major differences in modeling
approach of the BSIM, Philips MOS, and EKV models
[65]. For example, only the MOS11 model includes dif-
fusion tendency in describing the dc current, and the
EKV model is the only one using the bulk terminal as
the reference. These differences give rise to the different
levels of complexity, robustness, and accuracy among
these models.
It is fairly safe to say that the number of model pa-
rameters increases with increasing model complexity. As
illustrated in Fig. 17, the number of intrinsic model
parameters is indeed increased exponentially over thepast 40 years [66]. It is also indicated that the EKV and
Philips MOS models possess less model parameters than
the BSIM model.
4.2. Modeling of four-terminal RF MOSFET
Theoretically, it is possible to develop a four-terminal
MOSFET model for RF applications. However, the
measurements of four-terminal devices require much
effort, and the parameter extraction procedures are too
difficult due to the complicated theoretical Y -parameter
expressions of the four-terminal equivalent circuit. The
macro-modeling approach can alleviate this problem.
This approach makes use of a commercially available
MOSFET model core, such as the BSIM4, MOS11, or
EKV model, and adds lumped-element equivalent cir-
cuit extensions. In other words, the model core andlumped components compose an equivalent circuit rep-
resenting an RF four-terminal MOSFET. One of these
lumped components is the gate resistance, which con-
sists of the distributed gate electrode resistance as well
as the non-quasi-static element. The effect of substrate
using lumped components should also be incorporated
into the macro model. Fig. 18 shows a macro RF MOS
model consisting of the gate resistance and a sub-circuit
accounting for the effect of substrate including two ca-
pacitances and five resistances.
Usually, parameters of the model core are extracted
with dc and low-frequency C – V measurements using thesame procedures available in the commercial model. The
extraction of the lumped elements is then carried out
using measured S -parameters at a given dc bias condi-
tion. The gate resistance has a great influence on the
real part of Y 11, and the substrate network affects the
real part of Y 22 most significantly. Thus, the gate resis-
tance and substrate-related elements are extracted from
Table 7
Summary of the approached used in the BSIM, MOS, and EKV models
BSIM3 BSIM4 MOS9 MOS11 EKV
Method Analytic Analytic Analytic Analytic Analytic
Channel inversion Vt-based Vt-based Vt-based Surface-potential based Hybrid
DC current Drift Drift Drift Drift-diffusion Drift
Reference Source Dynamic Source Source Bulk
Symmetry No Yes No Yes Yes
Gate noise Ignore Yes Yes Yes Ignore
Tunneling Ignore Yes Ignore Yes Ignore
1960 1970 1980 1990 2000 2010
LEVEL1
LEVEL2
1
10
100
1000
LEVEL3
BSIM
HSP28
BSIM
HSP28
BSIM2
BSIM3V1
BSIM3V2
PCIM
MM9
SP2000
EKV V3.0
EKV V2.6
BSIM 3V3
BSIM 4
BSIM2
BSIM3V2BSIM 3V3
Including L,W,P Scaling
Without Scaling
Years
N o . o
f M o d e l P a r a m e t e r s
Fig. 17. Comparison of the number of parameters associated
with the various MOS models (after [66]).
R GGext
C DB
Gint
Dint
Sint
Bint
BextR DSB2
R DSB1
R SB
R DB
C SB
R DSB3
Sext
Dext
Model
Core
Fig. 18. Four-terminal RF MOSFET model based on the
macro-modeling approach.
1892 J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
13/15
ReðY 11Þ and ReðY 22Þ directly or using a fitting technique.
Results of frequency-dependent Y-parameters modeledand measured from a 0.18-lm n-MOSFET are given in
Fig. 19 [67].
The approach of macro-modeling discussed above
provides a useful compromise between accuracy and
efficient. These models, accompanied by appropriate
parameter extraction processes, show fairly good agree-
ments with measured RF data. However, such an
approach cannot overcome some of the limitations in-
herited in the MOSFET model core. For example, g mand g ds predicted by commercial models is not yet very
accurate, this is especially troublesome for RF circuit
simulation where the higher order derivatives of the
current should be smooth and correct. There are also
errors in predicting the intrinsic C – V characteristics of
short-channel MOSFETs. Moreover, scalable models
for the added lumped elements are needed for the whole
model to be scalable and predictive.
5. Conclusions
The evolution, state of the art, as well as future
trends of RF MOSFETs have been presented and dis-
cussed. Aspects of RF MOSFET modeling and three
widely used MOS models were also reviewed. There is
no doubt that MOSFETs are progressing quickly andbecoming a strong contender in the RF applications
traditionally dominated by III–V devices. Todays RF
MOSFETs already fulfill most of the performance re-
quirements for civil RF systems operating in the fre-
quency range up to 6 GHz. For example, a low-end
wireless system such as Bluetooth is well suited for MOS
technology. In high-end systems, the combination of
MOSFETs and CMOS-compatible SiGe HBTs (i.e.,
SiGe BiCMOS) is a promising option.
References
[1] The International Technology Roadmap for Semicon-
ductor, Semiconductor Industry Association, 1999, 2001,
2002.
[2] Larson LE. Integrated circuit technology options for
RFICs––present status and future directions. IEEE J
Solid-State Circuits 1998;33:387–99.
[3] Woerlee PH, Knitel MJ, van Lengevelde R, Klaassen
DBM, Tiemeijer LF, Scholten AJ, et al. RF-CMOS per-
formance trends. IEEE Trans Electron Dev 2001;8: 1776–
82.
[4] Chang C-Y, Su J-G, Wong S-C, Huang T-Y, Sun Y-C. RF
CMOS technology for MMIC. Microelctron Reliab 2002;
42:721–33.
0 5 10 15 20
0
1
2
34
5
6
7
8
9
Y 1 1
[ m S ]
Frequency [ GHz ]
Real
Imaginary
Measurement Model
0 5 10 15 20-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
Y 1 2
[ m S ]
Frequency [ GHz ]
Real
Imaginary
Measurement Model
0 5 10 15 20-10
-5
0
5
10
15
20
25
30
Y 2 1
[ m
S ]
Frequency [ GHz ]
Real
Imaginary
Measurement Model
0 5 10 15 20
0
1
2
3
4
5
6
7
Y 2 2
[ m
S ]
Frequency [ GHz ]
Real
Imaginary
Measurement Model
(a) (b)
(c) (d)
Fig. 19. Characteristics of Y -parameters modeled and measured from a 0.18-lm n-MOSFET (after [67]).
J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895 1893
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
14/15
[5] Lilienfeld JE. Methods and apparatus for controlling
electric current. US Patent 1745175. Application filed 8
October 1926, granted 18 January 1930.
[6] Lilienfeld JE. Device for controlling electrical current. US
Patent 1 900 018. Application filed 28 March 1928, granted
7 March 1933.
[7] Heil O. Improvements in or relating to electrical amplifiersand other control arrangements and devices. British Pa-
tent 439 457. Application filed 4 March 1935, granted 6
December 1935.
[8] Kahng D, Atalla MM. Silicon–silicon dioxide field induced
surface devices. IRE-AIEEE Solid-State Device Research
Conference, Carnegie Institute of Technology, Pittsburgh,
PA, 1960.
[9] Khang D. Silicon–silicon dioxide surface device. Techn.
Memorandum of Bell Laboratiories. In: Sze SM, editor.
Semiconductor Devices: Pioneering Papers. Singapore:
World Sientific; 1991.
[10] Brattain WH. Discovery of the transistor effect. Adv Exp
Phys 1976;5:1–31.
[11] Shockley WB. The path to the conception of the junctiontransistor. IEEE Trans Electron Dev 1976;23:597–620,
Reprinted: 1984;31:1523–46.
[12] Bardeen J, Brattain WH. Three-electrode circuit ele-
ment utilizing semiconductive materials. US Patent 2 524
035. Application filed 17 June 1948, granted 3 October
1950.
[13] Bardeen J, Brattain WH. The transistor, a semi-conductor
triode. Phys Rev 1948;74:230–1.
[14] Shockley WB. Electron and holes in semiconductors. New
York: Van Nostrand; 1950.
[15] Shockley WB. Circuit element utilizing semiconductive
material. US Patent 2 569 347. Application filed 26 June
1948, granted 25 September 1951.
[16] Sah CT. Evolution of the MOS transistors––from concep-
tion to VLSI. Proc IEEE 1988;76:1280–326.
[17] Wanlass FM, Sah CT. Nanowatt logic using field-effect
metal-oxide semiconductor triodes. In: IEEE Int Solid
State Cir Conf, 1963. p. 32–3.
[18] Wanlass FM. Low stand-by power complementary field-
effect circuitry. US Patent 3 356858. Application filed 18
June 1963, granted 5 December 1957.
[19] Kilby JS. Invention of the integrated circuit. IEEE Trans
Electron Dev 1976;ED23:648–54.
[20] Noyce RN. Semiconductor device-and-lead structure. US
Patent 2 981 877. Application filed 30 July 1959, granted 25
April 1961.
[21] Moore GE. Cramming more components onto integratedcircuits. Electronics 1965:114–9.
[22] Schaller RR. Moores law: past, present and future. IEEE
Spectrum 1997;34:52–9.
[23] Schwierz F, Liou JJ. Modern microwave transistors:
design, modeling, and performance. Hoboken: Wiley;
2003.
[24] Dennard RH, Gaensslen FH, Yu H-N, Rideout VL,
Bassous E, Leblanc AR. Design of ion-implanted MOS-
FETs with very small physical dimensions. IEEE J Solid-
State Circuits 1974;9:256–68.
[25] Brews JR, Fichtner W, Nicollian EH, Sze SM. Generalized
guide for MOSFET miniaturization. IEEE Electron Dev
Lett 1980;1:2–4.
[26] Baccarani G, Wordeman MR, Dennard RH. Generalized
scaling theory and its application to a 1/4 micrometer
MOSFET design. IEEE Trans Electron Dev 1984;31:452–
62.
[27] Ogura S, Codella CF, Rovedo N, Shepard JF, Riseman J.
A half-micron MOSFET using double implanted LDD.
Tech Dig IEDM 1982:718–21.[28] Hori A, Segawa M, Shimomura H, Kameyama S. A self-
aligned pocket implantation technology for 0.2-lm dual-
gate CMOS. IEEE Electron Dev Lett 1992;13:174–6.
[29] Momose HS, Morifuji E, Yoshimoto Y, Ohguro T, Saito
M, Iwai H. Cutoff frequency and propagation delay time of
1.5-nm gate oxide CMOS. IEEE Trans Electron Dev 2001;
48:1165–74.
[30] Momose HS, Morifuji E, Yoshimoto Y, Ohguro T, Saito
M, Morimoto T, et al. High-frequency AC characteristics
of 1.5 nm gate oxide MOSFETs. Tech Dig IEDM 1996:
105–8.
[31] Momiyama M, Hirose T, Kurata H, Goto K, Watanabe Y,
Sugii T. A 140 GHz f t and 60 GHz f max DTMOS integrated
with high-performance SOI logic technology. Tech DigIEDM 2000:451–4.
[32] Johnson RA, dela Houssaye PR, Chang CE, Chen P-F,
Wood ME, Garcia GA, et al. Advanced thin-film silicon-
on-sapphire technology: microwave circuit applications.
IEEE Trans Electron Dev 1998;45:1047–54.
[33] Schwierz F. Microwave transistors: state of the art in the
1980s, 1990, and 2000s. A compilation of 1000 top refer-
ences, TU Ilmenau 2003, Unpublished.
[34] Narashima S, Ajmera A, Park H, Schepis D, Zamdmer N,
Jenkins KA, et al. High performance sub-40 nm CMOS
devices on SOI for the 70 nm technology node. Tech Dig
IEDM 2001:625–8.
[35] Hirose T, Momiyama Y, Kosugi M, Kano H, Watanabe
Y, Sugii T. A 185 GHz f max SOI DTMOS with a new
metallic overlay-gate for low-power RF applications. Tech
Dig IEDM 2001:943–5.
[36] Tiemeijer LF, Boots HMJ, Havens RJ, Scholten AJ, de
Vreede PHW, Woerlee PH, et al. A record 150 GHz f maxrealized at 0.18 lm gate length in an industrial RF-CMOS
technology. Tech Dig IEDM 2001:223–6.
[37] Burghartz JN, Hargrove M, Webster CS, Groves RA,
Keene M, Jenkins KA, et al. RF potential of a 0.18-lm
CMOS logic device technology. IEEE Trans Electron Dev
2000;47:864–70.
[38] Hirose T, Momiyama Y, Kosugi M, Kano H, Watanabe
Y, Sugii T. A 185 GHz f max SOI DTMOS with a new
metallic overlay-gate for low-power RF applications. TechDig IEDM 2001:943–5.
[39] Geppert L. The amazing vanishing transistor act. IEEE
Spectrum 2002:28–33.
[40] Hoyt JL, Nayfeh HM, Eguchi S, Aberg I, Xia G, Drake T,
et al. Strained silicon MOSFET technology. Tech Dig
IEDM 2002:23–6.
[41] Zhong H, Hong S-N, Suh Y-S, Lazar H, Heuss G, Misra
V. Properties of Ru–Ta alloys as gate electrodes for NMOS
and PMOS silicon devices. Tech Dig IEDM 2001:467–
70.
[42] Choi Y, King T, Hu C. Nanoscale CMOS spacer FinFET
for terabit era. IEEE Electron Dev Lett 2002;23:
25–7.
1894 J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895
-
8/20/2019 3.RF MOSFET- Recent Advances, Current Status and Future Trends
15/15
[43] Yu B, Chang L, Ahmed S, Wang H, Bell S, Yang C-Y, et al.
FinFET scaling to 10 nm gate length. Tech Dig IEDM
2002:251–4.
[44] Guarini KW, Solomon PM, Zhang Y, Chan KK, Jones
EC, Cohen GM, et al. Triple-self-aligned, planar double-
gate MOSFETs: devices and circuits. Tech Dig IEDM
2001:425–8.[45] Lee TH, Wong SS. CMOS RF integrated circuits at 5 GHz
and beyond. Proc IEEE 2000;88:1560–71.
[46] Schumacher H, Erben U, D€uurr W. SiGe heterojunction
bipolar transistors––the noise perspective. Solid-State Elec-
tron 1997;41:1485–92.
[47] Greenberg DR, Jagannathan B, Sweeney S, Freeman G,
Ahlgreen D. Noise performance of a low base resis-
tance 200 GHz SiGe technology. Tech Dig IEDM 2002:
787–90.
[48] Heinemann B, R€uucker H, Barth R, Bauer J, Bolze D,
Bugiel E, et al. Novel collector design for high-speed
SiGe:C HBTs. Tech Dig IEDM 2002:775–8.
[49] Hashimoto T, Nonaka Y, Saito T, Sasahara K, Tominari
T, Sakai K, et al. Integration of a 0.13-lm CMOS and ahigh performance self-aligned SiGe HBT featuring low
base resistance. Tech Dig IEDM 2002:779–82.
[50] Knoll D, Ehwald KE, Heinemann B, Fox A, Blum K,
R€uucker H, et al. A flexible, low-cost, high-performance
SiGe:C BiCMOS process with a one-mask HBT module.
Tech Dig IEDM 2002;783–786:2002.
[51] Freeman G, Ahlgreen D, Greenberg DR, Groves R,
Huang F, Hugo G, et al. A 0.18 lm 90 GHz f T SiGe
HBT BiCMOS, ASIC-compatible, copper interconnect
technology for RF and microwave applications. Tech Dig
IEDM 1999:569–72.
[52] Wang N-LL. Transistor technologies for RFICs in wireless
applications. Microwave J 1998:98–110.
[53] Browne J. More power per transistor translates into
smaller amplifiers. Microwaves RF 2001:132–6.
[54] Browne J. Chip contains full bluetooth solution. Micro-
waves RF 2001:139.
[55] Bindra A. Silicon–germanium HBTs merge with main-
stream CMOS process. Electron Des 2000:97–110.
[56] Rich DA, Carroll MS, Frei MR, Ivanov TG, Mastrapa-
squa M, Moinian S, et al. BiCMOS technology for mixed
digital, analo, and RF applications. IEEE Microwave Mag
2002:44–55.
[57] Rich DA, Carroll MS, Frei MR, Ivanov TG, Mastrapa-
squa M, Moinian S, et al. 10 Years of RF-CMOS––but
how many products today? Dig ISSCC 2001:104–5.[58] Je MY, Kwon I, Shin H, Lee K. MOSFET modeling and
parameter extraction for RF ICs. Int J High Speed
Electron Syst 2001;11:953–1006.
[59] Dambrine G, Cappy A, Heliodore F, Playez E. A new
method for determining the FET small-signal equivalent
circuit. IEEE Trans Microwave Theory Tech 1988;36:
1151–9.
[60] Kundert K, Sangiovanni-Vincentelli A. Simulation of
nonlinear circuits in the frequency domain. IEEE Trans
Computer-Aided Des 1986;CAD-5.
[61] Vandeloo PJV, Sansen WMC. Modeling of the MOS
transistor for high frequency analog design. IEEE Trans
Computer-Aided Des 1989;8:713–23.
[62] MOSFET Model Users Model. Dept Electrical Engineer-ing and Computer Sciences, University of California,
Berkeley. Available from: .
[63] Philips MOS Model Manual. Available from: .
[64] Enz CC, Krummenbacher F, Vittoz EA. An analytical
MOS transistor model valid in all regions of operation and
dedicated to low-voltage and low-current applications.
Analog Integ Circuits Signal Process J 1995;8:83–114.
[65] Liu W. MOSFET models for SPICE simulation including
BSIM3v3 and BSIM4. John Wiley; 2001.
[66] Grabinski W, Bucher M, Sallese J-M, Krummenacher F.
Compact modeling of ultra deep submicron CMOS devices.
Available from: .
[67] Je M, Han J, Shin H, Lee K. A simple four-terminal small-
signal model of RF MOSFETs and its parameter extrac-
tion. Microelectron Reliab 2003;43:601–10.
J.J. Liou, F. Schwierz / Solid-State Electronics 47 (2003) 1881–1895 1895
http://www-device.eecs.berkeley.edu/http://www-device.eecs.berkeley.edu/http://www.semiconductors.philips.com/Philips_Models/documentation/mosmodel/http://www.semiconductors.philips.com/Philips_Models/documentation/mosmodel/http://www.semiconductors.philips.com/Philips_Models/documentation/mosmodel/http://legwww.epfl.ch/ekv/ICSES2000s1.pdfhttp://legwww.epfl.ch/ekv/ICSES2000s1.pdfhttp://legwww.epfl.ch/ekv/ICSES2000s1.pdfhttp://legwww.epfl.ch/ekv/ICSES2000s1.pdfhttp://www.semiconductors.philips.com/Philips_Models/documentation/mosmodel/http://www.semiconductors.philips.com/Philips_Models/documentation/mosmodel/http://www.semiconductors.philips.com/Philips_Models/documentation/mosmodel/http://www-device.eecs.berkeley.edu/http://www-device.eecs.berkeley.edu/