I²C
Sample clock
generator logic
(FPGA)
1P8V_ISO 3P3V_ISO
EMACIntegrated
IEEE 1588
AM3359ARM
CortexA8Core
USB 2.0 / OTG PHY
Memory interface
Gigabit transceiver
USB connector
Flash
DDR2
SPI
System bus
I2C
Beagle Bone
Router or hub
Ethernet
Ethernet connector
EEPROM
SPI
FPGA
OSC
3P3V 1P8V 2P5
Isolation barrier
TI-PHIEVM controller
(PHI2) USB
Vcm
OPA625
± +
±
+
18-Bit 2-MSPS
SAR ADC
1P8V_ISO
DVDDAVDD
REF5045Reference
4.5 V
Vcom
ADS9110
SDO-1SDO-2SDO-3
SDO-0
SCLKSCSSDI
Input protection
LMK61E2OSC
I 2 C
TPS70933TPS7A4700
LDO
3P3V_ISO
5V_ISO 5P5V_ISOTPS70933
TPS7A4700LDO
3P3V1P8V1P8V_ISO
1P2V_ISO
LMZ14203TZDC-DCBuck
12-V DCSN6505
Push pull
driver
+
ISO_GND GND
5-V DC
5-V DC
CONVST
5V_ISO
5V_ISO
5-V DC
Optional
ISO78xx
ISO78xx
xx
xx
SN65LVDS4RSETLVDS receiver
Copyright © 2016, Texas Instruments Incorporated
TI-PHIEVM controller
(PHI1)
RVS
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
TI Designs18-Bit, 2-MSPS Isolated Data Acquisition ReferenceDesign for Maximum SNR and Sampling Rate
All trademarks are the property of their respective owners.
TI DesignsThis TI Design illustrates how to overcomeperformance-limiting challenges typical of isolated dataacquisition system designs by:• maximizing sampling rate by minimizing
propagation delay introduced by digital isolator• maximizing high-frequency AC signal chain
performance (SNR) by effectively mitigating ADCsampling clock jitter introduced by the digitalisolator
Design Resources
TIDA-00732 Design FolderADS9110 Product FolderISO7840, ISO7842, ISO1541 Product FoldersREF5045, TLV3012 Product FoldersOPA376, OPA378, OPA625 Product FoldersTPS7A4700 Product FolderTPS70918, TPS70912 Product FolderLMZ14203, SN6505A Product FoldersSN74LVC1G17, SN74LVC1G08 Product FoldersLMK61E2 Product FolderADS9110EVM-PDK Associated Design
ASK Our E2E Experts
Design Features• Isolated 18-Bit, 2-MSPS, Single-Channel,
Differential Input Data Acquisition (DAQ) System• Leverages multiSPI™ Digital Interface of ADS9110
to Achieve 2-MSPS Sampling Rate WhileMaintaining Low SPI CLK Speed
• ADC Clock Master Mode and Source-SynchronousSPI Data Transfer Minimizes Digital IsolatorPropagation Delay and Increases Throughput
• Optimized Jitter Reduction Techniques EmployedResults in 12-dB SNR Improvement (100-kHz fIN,2-MSPS)
• Includes Theory, Calculations, ComponentSelection, PCB Design, and Measurement Results
Featured Applications• Modular DAQ Systems• Data Logging• Design Validation and Verification• Remote Process Monitoring and Control
Key System Specifications www.ti.com
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and otherimportant disclaimers and information.
1 Key System Specifications
Table 1. Key System Specifications
PARAMETER SPECIFICATIONSNumber of channels SingleInput type DifferentialInput range ±5-V fully differentialInput Impedance 1 KΩResolution 18 bitsSNR 95.5 dB at 100-kHz signal inputENOB 15.5 bits
Power supply isolation 250-V DC (continuous) basic insulation5000-V AC for 1 minute (withstand)
Digital channel isolation 5.7-kVRMS isolation for 1 minute per UL 1577Operating temperature 0°C to 60°CStorage temperature –40°C to 85°C
ConnectorsTwo, 60-pin Samtec high density connector for PHI moduleinterface2x46-pin 2.54-mm header for Beaglebone Black™ interface
Power 12- V DC, 250 mAForm factor (L × W) 228 mm × 106 mm
Sensor
I/P protection
Amp FilterDigitizer
(A/D)
MCUor
FPGA
Control circuitD/A Digital IO
Volt or Current IO
Direct sensor interface
Optional
DAQ
Data processing
Plottingand
data logging
Host
Physical phenomena
Measurement Types Form Factors Host Interfaces
1. Voltage, current and resistance2. Temperature ± Thermocouple, RTD, thermistor3. Displacement ± LVDT4. Force, Weight ± Strain gauge5. Flow sensor, pressure sensor
1. Standalone ± USB, LAN, Wi-)L�2. Open modular ± PXI, PXIe, VXI, AXI, and LXI3. Embedded modular ± PCI, PCIe4. Proprietary modular ± USB, LAN
1. Desktop PC or laptop2. Embedded controller
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
2 System DescriptionA DAQ system measures an electrical or physical phenomenon such as voltage, current, temperature,pressure, or sound with an integrated or external host computer.
A DAQ system consists of sensors, DAQ measurement hardware-signal conditioning ADC, and anembedded or host computer with programmable software. Figure 1 shows a generic DAQ system blockdiagram.
Figure 1. Generic DAQ System Block Diagram
The DAQ system can be found in following applications:• Voltage, current, and resistance measurement• Temperature measurement• Force measurement• Position, distance, or rotation• Sound and vibration monitor
The DAQ system can be classified according to functions• Analog input (isolated or non-isolated)• Multifunction• Universal input• Direct sensor input
Input protection
AmpADC driver
LPF
ADC MCU or FPGA
USB or LAN
PXI or PCI
VXI or LXI
HMI
VCOM REF
DC-DC
DC-DC
LDO
LDO
DC-DC
OSC
RAM
Isolation Barrer
LDO
LDO
LDO
LDO
12-V DC
3.3 V
2.5 V
1.8 V
1.2 V
(15 or 5 V)
(5 or 3.3 V)
(3.3 or 1.8 V)
(±15 or ±5 V)
+VCC
AVDD
DVDD
±VEE
Isolated power rail
Non-isolated power rail
Isolation Transformer
Digital Isolator
Serial or parallel
interface
Sample clock control
lines
Integrated AFE
±VEE ±VEE
+VCC +VCC
SPI or I2C
Host interface
AVDD DVDD
AVDD DVDDIN+
IN±
Gain selection
Optional
System Description www.ti.com
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
The TIDA-00732 is developed based on an isolated analog input type. Figure 2 shows the generic block diagram of an isolated analog inputmodule.
Figure 2. Generic Illustration of Isolated Analog Input DAQ Module
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
SensorAs discussed earlier, the DAQ system accepts direct electrical signal or physical parameters liketemperature, pressure, and force. If it is a physical parameter, an appropriate sensor can convert thephysical parameter to electrical signals; these electrical signals (volt or current) can be used as input toDAQ system.
Analog Front-EndThis device contains an input protection circuit at the front end, which protect inputs from surge voltageand feeds to a programmable gain amplifier that scales signals to the required level of the ADC dynamicrange. Followed by PGA, signals are fed to an anti-aliasing low-pass filer through the ADC driver. Here,anti-aliasing filters remove unwanted signals and limits input bandwidth of the analog front-end.
The ADC converts the time varying analog input to either a serial or parallel binary bit stream. These bitstreams are processed by a local embedded controller (MCU) or FPGA.
The ADC has onboard voltage reference, which provides high precision and low noise. Some versions ofADCs have integrated voltage reference as well.
In isolated DAQ systems, the isolation can be accomplished either with an analog or digital end dependingon system requirements. Typically, digital ends can isolate due to low costs and easy implementationcompared to analog isolation. In Figure 1, ADC data lines pass through the digital isolator and areconnected to embedded controller.
Host Computer InterfaceThe host or embedded controller is interfaced with ADC through a serial or parallel interface. The acquireddata are processed and displayed in a physical format.
The embedded controller has a human machine interface (HMI) with an embedded GUI for localmonitoring and data logging. The DAQ module also supports LXI, VXI, PCI, and PXI open architectureplatforms and USB interface, which can be used for further monitoring and analysis.
2.1 DAQ Signal Chain Design ChallengesDAQ systems use isolation in the signal chain because it breaks ground loops, thereby improvingmeasurement accuracy and safety. The isolation can be either at the analog input side or can be at thedigital interface. Analog isolation typically decides (and limits) the signal chain performance (analogisolation typically has an A/D-digital isolation-D/A chain). The digital isolator works fine for mediumresolution and medium sampling rates. However, for higher resolution (>16 bits), higher speed (>1 MSPS),and higher input BW (>100 kHz), the digital isolators present few design challenges to be considered tomatch the ADC performance with the complete signal chain performance.
2.1.1 Isolated Analog Input Module Signal Chain Design ChallengesDAQ systems typically use digital isolators at the serial peripheral interface (SPI) of the ADC for functionalisolation. The digital isolator presents two main design challenges: propagation delay and additive jitter.The propagation delay of the isolator limits the maximum clock of the SPI and hence limits the samplingrate of the ADC. The digital isolator adds jitter to the sampling clock that is generated at the host side. TheSNR degradation of the signal chain due to jitter in sampling clock is proportional to the input signalfrequency.
2.1.1.1 Propagation Delay in Digital IsolatorThe SPI bus is a synchronous, full duplex, serial data link commonly used for onboard short distance dataexchange between a master device, such as a microcontroller unit (MCU) or FPGA, and one or multipleslave devices, such as data converters, digital I/O devices, temperature sensors, and power managementcontrollers.
In SPI communication, data transfer transmission and reception happens on the same clock period. Inisolated systems, the digital isolator is placed in between master and slave devices. The round trippropagation delay of the digital isolator results in the delayed receive of ADC data at MCU. The round-trippropagation delay must be less than the half serial clock period to ensure an error-free data transfer.
11.7 MSPS
50.2
13
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+ç ÷ê úè øë û
0.3
20
æ öç ÷è ø
20
13
æ öç ÷è ø
1570 kHz
200.2
13
æ öç ÷ç ÷ @ç ÷æ ö
+ç ÷ç ÷è øè ø
( )1
13 MHz2 2 16 6.5
@´ ´ +
MCUDigital
IsolatorADC
SPI_CLK
MOSI
MISO
D0 D1 D2MOSI
SPI_CLK
D0 D1 D2MISO
D0 D1 D2MOSI
SPI_CLK
D0 D1 D2MISO
SPI
SPI_CLK_ISO
MOSI_ISO
MISO_ISO
Both Data and Clock are delayed, so no problem here
Clock to output delay of ADCReceive data timing error
( )SCLK _ min ISO _pd ADC_CKDOt 2 2 t t= ´ ´ +
System Description www.ti.com
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
(1)
Figure 3 shows the isolator propagation delay affecting the SPI receive timing.
Figure 3. Propagation Delay Affecting SPI Receive Timing
ISO7842 and ADS9110 ExampleConsider a signal chain with the ADS9110 and ISO7842 for an 18-bit, 2-MSPS sampling rate DAQsystem.• ISO7842: tISO_pd = 16 ns max• ADS9110: tADC_CKDO = 6.5 ns max and 20 SCLKs per sample
• fSCLK_max limited by isolator will be
For one MISO SPI, 13 MHz of SCLK results in of ADC sampling rate, where
is the data transfer time and 0.2 μs is the acquisition time for the ADC.
Any delay added in the SPI data path will further reduce the sampling rate. Therefore, at system level, themaximum sampling rate is limited by the delays and not by the ADC.
To achieve the sampling rate of 2 MHz, the SCLK should be at least or ~67 MHz, which requires anisolator propagation delay of ~4 ns max.
One way to relax the isolator’s propagation delay requirement is to use multiple SDO lines on the ADC. Byusing all four SDO lines of the ADS9110, the max throughput can be increased to
—still lesser than the 2 MSPS rated throughput of the ADS9110. However, threeadditional channels of isolation are required, and the host needs to support four SDI lines.
( ) ( )IN JITTERSNR 20log 2 f t 10log OSR= - p ´ +
Input Frequency (kHz)
SN
R (
dB)
SNR vs Input Signal Frequency (Jitter = 500 psRMS)
1 10 100 100050
60
70
80
90
100
110
120
Sampling error
Voltage measurement error
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
Another approach is to use the multi-SPI digital interface Clock Master Mode to perform a source-synchronous data transfer. In this mode, the ADC generates the SCLK signal on the RVS pin so that it isin sync with the data on the SDO pins, eliminating the effect of the isolator induced timing delays (see theADS9110 datasheet (SBAS629) or watch the multiSPI overview video for more details). To use this mode,the host side must support a SPI slave operation.
In summary, the propagation delay of the isolator affects the SPI receive data timing and limits the SCLKof the SPI. Limiting the SCLK, results in lower ADC sampling rate. The propagation delay could behandled by using lower SCLK for SPI. Slower SCLK is possible by using more SDO lines for SPI. Thepropagation delay can also be addressed by using source-synchronous mode of data transfer from ADC.
2.1.1.2 ADC Sampling Clock JitterThe SNR performance of the ADC at a higher input signal frequency is affected by the jitter in thesampling clock of the ADC. The sampling clock, which is the conversion start signal (CONVST), istypically generated by the host. Since the CONVST signal is passed through the isolator, jitter gets addedto the CONVST signal. The data convertor uses the convert start signal (CONVST) to sample the inputsignal, and any deviation in sample point creates a measurement error and increases the noise floor,which results in SNR degradation (see Figure 4 and Figure 5).
An acceptable clock jitter depends on the targeted system SNR, frequency of the input signal, and oversampling ratio (OSR) for sigma-delta ADC.
Figure 4. Error due to Jitter on Sampling Clock—Data Figure 5. Error due to Jitter on Sampling Clock—Graph
The SNR of the ADC with sampling clock jitter can be expressed as,
(2)
where• fIN: Input signal frequency• tJITTER: Total jitter of ADC (internal clock + external clock)• OSR: Over sampling ratio (only for sigma-delta ADC)
D
Hostcontroller
ADC
Isolator
Round trip delay period
D0 D1 D2MOSI
SCLK
D0 D1 D2MISO_1
SCLK_3
D0 D1 D2MOSI_1
D0 D1 D2MISO_1
SCLK_1
SCLK_2
SCLK
MOSI
MISO_1
SCLK_3
SCLK_1
MOSI_1
MISO(SDO0)
SCLK_2
Source synchronous mode at ADC
System Description www.ti.com
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
The datasheet SNR performance of the ADS9110 at 100-kHz input signal is 95.5 dB. The maximumallowed sampling clock jitter to achieve desired SNR can be calculated as shown in Table 2.
Table 2. Allowed Jitter-Desired SNR
PARAMETER VALUE UNITInput frequency 100 kHz
Target SNR 95.5 dBcAperture jitter 100 fs rms
Total jitter 26.72 ps rmsSample clock jitter 26.72 ps rms
Equation 2 clearly shows that the SNR of the signal chain will be limited if the jitter introduced by anisolator on the sample clock is greater than 27 ps rms.
2.2 Possible Solutions
2.2.1 Compensating the Propagation DelayThe ADS9110 has a multiSPI digital interface that allows the host controller to operate at slower SPISCLK and still achieve the required sampling rate. The multiSPI module offers the following options toreduce SCLK speed:1. Option to increase the width of the output data bus: 1, 2, and 4 SDO lines2. Source-synchronous mode
The multiSPI option allows the SPI SCLK to be reduced and thus reducing the impact of propagationdelay on the sampling rate. If the reduced SCLK rate is still above the loopback delay, then source-synchronous mode will be useful.
In source-synchronous mode, the SCLK from the host is looped back by the ADC along with the data. Theclock and data are synchronous in source-synchronous mode; therefore, the propagation delay of theisolator has no impact on the data rate.
As Figure 6 shows, in ADC-master or source-synchronous mode, the device provides asynchronousoutput clock (on the RVS pin) along with the output data (on the SDO-x pins). The ADC-master or source-synchronous mode completely eliminates the effect of isolator delays and the clock-to-data delays, whichare typically the largest contributors in the overall delay.
Figure 6. ADS9110 SPI Source-Synchronous Mode With Host and Slave End Timing Waveform
Prog- OSC
CONVST
#CS
SCLK
SDI
SDO 0 - 3
(READY or CLK) RVS
Isolator
ADC
60-Pin (30x2) 6DPWHF��
connector
I2C
I2C
OSC
#CS
SCLKSDO
SDI(0-3)
FPGA2
FRQ generator
DelayRCLK
PHI2 FPGA1
#CS_1
SCLK_1
SDO_1
SDI(0 ± 3)_1
#CS_2
SCLK_2
SDI_2
SDI(0 ± 3)_2
RCLK_2
#CS_3
SCLK_3
SDO_3
RCLK_3
SDI(0 ± 3)_3
CONVST_3 CONVSTCONVST_2
Option
RVS_1
CONVST_1
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
2.2.2 Mitigating SNR Degradation due to JitterAs per the analysis, the jitter on the conversion clock "CONVST" signal degrades the performance of ADC SNR at higher input signal frequencyand will impact the system performance.
As shown in Figure 7, the ADC sample clock CONVST is generated locally using CPLD or FPGA, and this signal is sent back to host forsynchronization. Further, this CONVST signal is synchronized with low jitter oscillator, which eliminates the jitter on the CONVST signal generatedby CPLD or FPGA.
Figure 7. Jitter Mitigation by Sampling CONVST With Ultra-low Jitter Clock
2.3 TIDA-00732 SolutionThe solution discussed in Section 2.2 is implemented in the TI Design TIDA-00732 and showcases the following features:• Compares SNR performance of the ADC side generated CONVST with the host generated CONVST• Demonstrates that the ADC side generated CONVST signal with low jitter clock has better SNR performance for high frequency input signal• Confirms that the host generated CONVST SNR performance is limited by digital isolator jitter
I²C
Sample clock
generator logic
(FPGA)
1P8V_ISO 3P3V_ISO
EMACIntegrated
IEEE 1588
AM3359ARM
CortexA8Core
USB 2.0 / OTG PHY
Memory interface
Gigabit transceiver
USB connector
Flash
DDR2
SPI
System bus
I2C
Beagle Bone
Router or hub
Ethernet
Ethernet connector
EEPROM
SPI
FPGA
OSC
3P3V 1P8V 2P5
Isolation barrier
TI-PHIEVM controller
(PHI2) USB
Vcm
OPA625
± +
±
+
18-Bit 2-MSPS
SAR ADC
1P8V_ISO
DVDDAVDD
REF5045Reference
4.5 V
Vcom
ADS9110
SDO-1SDO-2SDO-3
SDO-0
SCLKSCSSDI
Input protection
LMK61E2OSC
I 2 C
TPS70933TPS7A4700
LDO
3P3V_ISO
5V_ISO 5P5V_ISOTPS70933
TPS7A4700LDO
3P3V1P8V1P8V_ISO
1P2V_ISO
LMZ14203TZDC-DCBuck
12-V DCSN6505
Push pull
driver
+
ISO_GND GND
5-V DC
5-V DC
CONVST
5V_ISO
5V_ISO
5-V DC
Optional
ISO78xx
ISO78xx
xx
xx
SN65LVDS4RSETLVDS receiver
Copyright © 2016, Texas Instruments Incorporated
TI-PHIEVM controller
(PHI1)
RVS
Block Diagram www.ti.com
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
3 Block Diagram
Figure 8. TIDA-00732 System Block Diagram
www.ti.com Block Diagram
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
3.1 Highlighted ProductsThe system contains the following highlighted parts, which determine the overall system performance.
These parts can be grouped as flowing sections:• Signal chain• Clock• Power
3.1.1 Signal Chain• OPA625
The OPAx625 is designed to drive precision (16-bit and 18-bit) SAR ADCs at sample rates up to 1MSPS. The combination of low output impedance (1 Ω at 1 MHz), low THD, low noise, and fast settlingtime (4-V step, 16-bit levels with 280 ns) make the OPAx625 the ideal choice for driving both the SARADC inputs and the reference input to the ADC.
• ADS9110The module has a single-channel differential analog input and uses the ADS9110, 18-bit, 2-MSPS SARADC.
• REF5045The onboard reference REF5045 (ultra-low noise, low drift, and high precision) followed by low noise,low temperature drift, and low output impedance buffer provide a 4.5-V reference to ADC core.
• ISO784x and ISO1541The digital isolation for the host SPI and control signal is achieved using the ISO7840 and ISO7842digital isolators. The host controller communicates with the LMK61E2-SIAR (ultralow programmableclock oscillator) through the ISO1541, which isolates the I2C bus.
3.1.2 ClockThe LMK61E2 programmable oscillator has the following features:• Ultralow noise, high performance (90-fs RMS jitter at > 100 MHz)• Frequency tolerance ±50 ppm• Frequency output 10 MHz to 1GHz• I2C interface
3.1.3 Power• SN6505
The isolated power supply power is generated using the SN6505, low-noise, low-EMI push-pulltransformer driver.
• DC-DC and LDOThe power supply rail for both the isolated and non-isolated sections is generated by the DC-DCconvertor and LDO, which are shown in Table 3.
Table 3. Supply Rails
SINO TYPE PART NO SUPPLY RAIL1 DC-DC LMZ14203 5.5 V2 LDO TPS7A4700RGWR 5 V, 3.3 V3 LDO TPS709XXDBVT 1.8 V, 1.2 V
+
Gain Network
SAR
ADC
BufferVoltage
ReferenceRC Filter RC Filter
Anti-Aliasing
Filter
Input Driver
Reference Driver
VREF Output: Value and Accuracy
Low Temp & Long-Term Drift
Low Noise
Band-limiting
Reference Noise
Low Output Impedance
Low Offset Error
Low Temp & Long-Term Drift
VREF Load
Regulation
18-bit
1MSPS
+
Gain Network
REFP
VINP
VINM
Full Scale
10-kHz Sinewave
Band-limit the noise from front-end circuit
Attenuate ADC kick-back noise
“Isolation” resistor for amplifier stability
Rail-to-rail IO Swing
Low Power
Low Noise & Distortion
Differential
Voltage
Source
1
2
3
Circuit Design www.ti.com
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
4 Circuit DesignThe DAQ analog front-end consists of the high-speed signal chain and the power supply section. Thissection describes various circuit blocks, performance requirement, and the component selectionmethodology.
4.1 Signal Chain Circuit DesignOne of the major and essential building blocks for DAQ is the analog front-end, which consists of the inputdriver followed by an anti-aliasing filter, an ADC, and reference circuit. The TI Precision Design 18-Bit,1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest Power is taken as a reference, and all thedesign equations can be referred to the same (SLAU513).
The TIDA-00732 highlights the signal chain design challenges in an 18-bit, 2-MSPS DAQ system. Thisdesign uses TI’s 18-bit, 2-MSPS SAR ADC, ADS9110. The ADS9110 is a fully differential SAR ADC withexcellent dynamic performance and low power. The device consumes only 15 mW of power whenoperating at the full 2 MSPS throughput. The ADS9110 features the new multiSPI digital interface, whichreduces the SPI clock rate for the full sample rate.
To optimize the performance of the 18-bit, 2-MSPS DAQ system, the input buffer, anti-aliasing filter, andreference driver must be designed in such a way that the performance is equal to or greater than the ADCperformance.
To meet the performance goals of the AFE design, follow these steps:1. Select an appropriate amplifier with sufficient small-signal bandwidth and low power, which minimally
degrades the noise and distortion performance of the ADC.2. Design a low-pass anti-aliasing RC filter to band-limit the noise contribution from the front-end circuitry
while paying attention to the stability of the driving amplifiers.3. Design a high precision reference driver circuit, which should provide the required value of VREF with
low offset, drift, and noise contributions.
Figure 9. Analog Front-End Circuit of DAQ
3dB
FLT FLT
1f
2 R C-
=
p ´ ´
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
4.1.1 Input Driver Circuit
4.1.1.1 Input Buffer AmplifierThe input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is used for signal conditioning of the input signal, and its low outputimpedance provides a buffer between the signal source and the switched capacitor inputs of the ADC. TheRC filter helps attenuate the sampling charge injection from the switched capacitor input stage of the ADCand functions as an antialiasing filter to band-limit the wideband noise contributed by the front-end circuit.Carefully design the front-end circuit to meet the linearity and noise performance of the ADS9110.
The input op amp must support following key specifications:1. Rail-to-rail input and output (RRIO)2. Low power, low noise3. High small-signal bandwidth with low distortion at high frequencies
The OPAx625 is designed to drive precision (16-bit and 18-bit) SAR ADCs at sample rates up to 2 MSPS.The combination of low output impedance (1 Ω at 1 MHz), low THD, low noise (2.5 nV/√Hz), and fastsettling time (4-V step, 16-bit levels with 280 ns) make the OPAx625 the ideal choice for driving both theSAR ADC inputs as well as the reference input to the ADC.
Settling TimeFor DC signals with fast transients that are common in a multiplexed application, the input signal mustsettle within an 18-bit accuracy at the device inputs during the acquisition time window. This condition iscritical to maintain the overall linearity performance of the ADC. Typically, the amplifier datasheets specifythe output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 18-bit accuracy. Therefore, always verify the settling behavior of the input driver by TINA™-SPICEsimulations before selecting the amplifier.
Antialiasing FilterConverting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher-frequency content in the input signal beyond half the sampling frequency is digitized and folded back intothe low-frequency spectrum. This process is called aliasing. Therefore, an analog antialiasing filter mustbe used to remove the harmonic content from the input signal before being sampled by the ADC. Anantialiasing filter is designed as a low-pass, RC filter, where the 3-dB bandwidth is optimized based onspecific application requirements.
For DC signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designedto allow accurate settling of the signal at the inputs of the ADC during the small acquisition time window.
For AC signals, keep the filter bandwidth low to band-limit the noise fed into the input of the ADC, therebyincreasing the SNR of the system. Besides filtering the noise from the front-end drive circuitry, the RC filteralso helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. Afilter capacitor, CFLT, is connected from each input pin of the ADC to the ground (as shown in Equation 3and Figure 10).
This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly chargethe internal sample-and-hold capacitors during the acquisition process. Generally, the value of thiscapacitor must be at least 15 times the specified value of the ADC sampling capacitance. For theADS9110, the input sampling capacitance is equal to 60 pF, thus it is recommended to keep CFLT greaterthan 900 pF. The capacitor must be a COG- or NPO-type because these capacitor types have a high-Q,low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, andtime.
(3)
O
FLT
R 1R 0.111
9 9
W³ = =
FLT SHC 20 C 20 60 pF 1.2 nF³ ´ = ´ =
AINP
AINM
Device
GNDC FLT ��900 pF
C FLT ��900 pF
R FLT ��10
R FLT ��10
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Figure 10. Anti-aliasing Filter Configuration—Diagram
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making theamplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used atthe output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, butadds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortionincreases with source impedance, input signal frequency, and input signal amplitude. Therefore, theselection of RFLT requires balancing the stability and distortion of the design. For the ADS9110, limiting thevalue of RFLT to a maximum of 10 Ω is recommended to avoid any significant degradation in linearityperformance. The tolerance of the selected resistors must be kept less than 1% to keep the inputsbalanced. The driver amplifier must be selected such that its closed-loop output impedance is at least fivetimes lesser than the RFLT.
4.1.1.2 RC Filter Passive Components SelectionThe critical passive components are resistor (RFLT) and capacitor (CFLT) for RC filter. The resistor tolerancemust be 1% because use of differential capacitor at input balances the effect due to any resistormismatch. The type of capacitor should be COG (NPO) because it has high Q and low temperaturecoefficient and stable electrical characteristics over voltage and frequency and time variations.
To Select CFLT
The input capacitance for the ADS9110 is 60 pF. The filter capacitor CFLT should be 20 times greater thatsampling capacitor of ADC.
(4)
For common mode, the capacitor value selected was 10 nF for optimum design performance.
To select RFLT
The output resistance of OPA625 is RO = 1 Ω and substituted in following formula:
(5)
So, the value of RFLT can be chosen greater than 0.1 Ω.
VCM
-
+
-
+
18-Bit 2-MSPS
SAR ADC
1P8V_ISO
DVDDAVDD
ADS9110
5 VISO
5 VISO
RF =1 N��
CF =1 nF
RFLT = 2.2 ��
C FLT = 10 nF
1 N��
1 N��
OPA625
OPA625
10 nF
Anti- aliasing filter, band limit noise from
front-end circuit
Input buffer with 160-kHz band limiting filter
Differential input filter to remove external noise
C FLT = 10 nF
R FLT = 2.2 ��
RF = 1 N��
CF = 1 nF
VIN+
VIN-
GND
6 9
12.27
2 2 10 1 0 10 -
= = W
´ p ´ ´ ´ ´
FLTRC _ CUTOFF FLT
1R
2 F C=
´ p ´ ´
3dB _RC _ CUTOFFFLT FLT
1F
2 R C-
=
´ p ´ ´
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The RFLT and CFLT are calculated for 7-MHz, –3-dB cutoff frequency with above R and C valueconsideration. For the RC filter cut-off frequency:
(6)
where• CFLT = 10 nF• F–3dB_RC_CUTOFF = 7 MHz
(7)
4.1.1.2.1 Input Low-Pass Band Limiting FilterThe overall input signal bandwidth is limited by the input buffer amplifier configured as 160-kHz anti-aliasing filter formed 1-kΩ resistor and 1-nF capacitor at amplifier feedback.
Figure 11. TIDA-00732 Analog Front-End
(4.5 V)(2.25 V)
CLOSED
OPENBUFFER
REFOUTOPA625_CM
OPA625_CM R110
499
R106
20.0 k
R109
280 k
R111
20.0 k
R11420.0 k
R11210.0 k
4
3
12
J11
87898-0204
AGND_ISO
5 V_ISO
C74
1 µF
C77
0.1 µF
C801 µF
87898-0204
J10
AGND_ISO
12
2U23
OPA376AIDBVR1
5
AGND_ISO
AGND_ISO
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4.1.2 Common-Mode Voltage (VCM)The onboard reference REF5045 (ultra-low noise, low drift and high precision) generates both ADCcommon-mode voltage and ADC reference voltage.
To exercise the complete dynamic range of the ADS9110, the common-mode voltage at the ADS9110inputs is established at a value of 2.25 V (4.5 V / 2) by using the non-inverting pins of the OPA625amplifier’s on-board reference REF5045 (ultra-low noise, low drift, and high precision) used to generate4.5 V.
Figure 12. Common-Mode Voltage
REFERENCE
REFERENCE BUFFER
5 V_ISO
AGND_ISO
C 791 µF
3
2U22A
VIN
TEMP
VOUTTRIM/NR
GND
REF5045AIDGKTAGND_ISO
65
4
5
AGND_ISO
AGND_ISO
R1130.22
R85
1.00 k C53
1 µF
C8110 µF
REFOUT
5 V_ISO
AGND_ISOAGND_ISO
AGND_ISO
AGND_ISO
AGND_ISO
AGND_ISO
REFOUT
3
4
52
1
U14OPA378AIDBVT
5
3
4
26
R91
1.00 k
R884.99k
R880.1 µF
R86
2.49 k
C55 0.1 µF
C60 0.1 µFAGND_ISO
AGND_ISO
R94
30.0 k
C61
10 pF
R92
499
R89
4.75
C52 0.22 µF
R2760.1
R2680.1
C57
22 µF
C58
22 µF
C49
10 µF
1
5 V_ISO
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
4.1.3 Reference Buffer CircuitThe reference driver circuit, illustrated in Figure 13, generates a voltage of 4.5-V DC using a single 5-V supply. This circuit is suitable to drive thereference of the ADS9110 at higher sampling rates up to2 MSPS. The reference voltage of 4.5 V in this design is generated by the high-precision, low-noise REF5045 circuit. The output broadband noiseof the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz.
The reference buffer is designed with the OPA625 and OPA378 in a composite architecture to achieve superior DC and AC performance at areduced power consumption, compared to using a single high-performance amplifier. The OPA625 is a high-bandwidth amplifier with a very lowopen-loop output impedance of 1 Ω up to a frequency of 1 MHz. The low open-loop output impedance makes the OPA625 a good choice fordriving a high capacitive load to regulate the voltage at the reference input of the ADC. The relatively higher offset and drift specifications of theOPA625 are corrected by using a DC-correcting amplifier (OPA378) inside the feedback loop. The composite scheme inherits the extremely lowoffset and temperature drift specifications of the OPA378.
Figure 13. Reference Buffer Circuit
nRSTCONVST
nCSSCLK
SDISDO-0SDO-1SDO-2SDO-3
RVS
nRSTCONVSTnCSSCLKSDOSDI-0SDI-1SDI-2SDI-3RCLK
ADS9110 HOSTISOLATOR
SPI
PXOWL63,��
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4.1.4 ADC SPI (multiSPI)The ADS9110 has a integrated multiSPI that is backward compatible with the traditional SPI andconfigurable SDO lines (1, 2, and 4) . The configurable feature simplifies board layout, timing and firmwareand achieves high throughput at lower clock speeds, thus allowing easy interface with embeddedmicrocontrollers, digital signal processors (DSPs), and field programmable gate arrays (FPGAs). Figure 14shows multiSPI and detailed information can be found in ADS9110 datasheets.
Figure 14. multiSPI
4.2 Clock Circuit SectionThe clock source is an essential component in signal chain specifically when driving the sample clockinput of ADC. The clock optimization is a big challenge in system design.
The clock jitter directly impacts ADC SNR performance greatly at higher input signal frequency. Therefore,select the right clock source to optimize signal chain performance.
This design has two master clock sources that can be used for ADC sample clock generation, jittercleaner logic, and host interface synchronization:1. Crystal oscillator (3.3 V, 125 MHz, 50 ppm, low jitter, 1.9-ps jitter)2. LMK61E2: Programmable crystal oscillator (3.3 V, 150 MHz, 90-fs jitter)
Table 4 shows resistor jumpers selecting one of these clock sources:
Table 4. Master Clock Selection
SLNO MASTER CLOCK RESISTOR MOUNTING REMARKS
1 Crystal oscillator R167 — PopulateR269 — Do not populate 3.3 V, 125 MHz, 50 ppm, low jitter, 1.9-ps jitter
2 Programmable crystal oscillator R167 — Do not populateR269 — Populate
3.3 V, 150 MHz, 90-fs jitter(Frequency of oscillator must be programmedto 125 MHz through I2C interface)
4.3 Isolator SectionThe TIDA-00732 uses TI's ISO784x and ISO1541 series isolators to establish digital isolation in thesystem. The ISO784x series supports signaling rate up to 100 Mbps with typically low propagation delay(11 ns) and wide supply voltage (2.25 to 5.5 V). These isolators are reinforced with very high immunityand a 5.7-kVRMS isolation voltage with very low jitter.
The system requires six isolation channels for standard SPI communication and ten isolation channels formultiSPI.
The ISO784x isolators used for SPI, ADC control lines and ISO1541 bi-directional isolator is used for I2Cisolation.
BT
BB
RF 51 5.25
RF 0.8
æ ö= - =ç ÷
è ø
EN2
EN1LDO
LDO
LDO
LDO
LDO 5V_ISO1
3P3V_ISO
1P8V_ISO1
A1P8V_ISO
1P2V_ISO
DC-DCLMZ14203TZ-ADJ/NOPB
5.5 V
LDO
LDO
LDO
TPS7A4700RGWR
TPS70918DBVT
TPS70912DBVT
3P3V
1P8V1
+12-V DC
1P2V_ISO
5.5 V5.4-V DC
EVM1_DVDD
1P8V_ISO
EVM1_REG_5V5
5V_ISO OPAMPREFERENCE
EVM2_DVDD
1P8V
D1
D2SN6505A
+
ISOLATORLOGIC,FPGA IO
VDD(ADC)LOGIC,FPGA IO
FPGA CORE
AVDD(ADC)
FPGA IO
FPGA IO
FPGA CORE
TPS7A4700RGWR
TPS70918DBVT
TPS70912DBVT
TPS7A4700RGWR
TPS70918DBVT
Non-isolated power supply rail Isolated power supply rail
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4.4 Power SectionThe design requires isolated and non-isolated power rails to various components. The block diagram in Figure 15 describes the power supply treefor both isolated and non-isolated sections.
Figure 15. Power Supply Block Diagram of TIDA-00732
4.4.1 DC-DC
4.4.1.1 LMZ14203TZ-ADJThe LMZ14203TZ-ADJ simple switcher is capable of accepting 6- to 46-V DC input and deliver a0.8- to 6-V output with 90% efficiency. The undervoltage lockout is selected at 7.97 V, which helps to enable the LMZ4203TZ-ADJ.
To Set 5-V Output VoltageThe resistor RFBT (R220) and RFBB (R223 + R225) decide the output voltage of the LMZ14203TZ-ADJ.
For a 5-V output, the ratio for
(8)
FB
118kR219
20.5kR224
249kR221
0.022µFC42
0.01µF
C41
10µF
C39
10µFC40 22µF
C91
600 ohm
L2VIN
1
EN3
SS5
GND4
FB6
RON2
VOUT7
EP8
U3
LMZ14203TZ-ADJ/NOPB
+12VDC 5VDC
5.62kR220
1.07kR223
0.01R225
Red
21
D7
1.2kR222
GNDGND GNDGND
GND
GNDGND
5016
TP16
5016
TP32
Copyright © 2016, Texas Instruments Incorporated
UVLO set resisitors Output set resisitors
BT
5.62KRF 1.07K
5.25= =
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
Select
So R220 = 5.62K , R223 = 1.07K, and R225 = 0 Ω
Figure 16. DC-DC Power Supply
4.4.2 LDO
4.4.2.1 TPS7A4700RGWRThe TPS7A4700 is a positive voltage (36 V), ultralow-noise (4 μVRMS) LDO capable of sourcing a 1-A load.The TPS7A470x is designed with bipolar technology primarily for high-accuracy, high-precisioninstrumentation applications where clean voltage rails are critical to maximize system performance. Thisfeature makes the device ideal for powering op amps, ADCs, DACs, and other high-performance analogcircuitry.
The TPS7A4700RGWR has ANY-OUT™ programmable pins to program desired output voltage. The sumof the internal reference voltage (VREF = 1.4 V) plus the accumulated sum of the respective voltages isassigned to each active pins.
The ANY-OUT™ pins (Pin8, Pin1, and Pin12) are programmed to active low to get 3.3 V at output.
4.4.2.2 TPS7091XDBVTThe TPS709 series of linear regulators are ultralow, quiescent current devices designed for powersensitive applications. A precision band-gap and error amplifier provides 2% accuracy over temperature.The TPS709 series accepts 2.7- to 30-V input voltage and deliver fixed output voltage 1.2 to 6.5 V withmaximum 200-mA output current. The TPS70918DBVT and TPS70912 generate 1.8 V and 1.2 V,respectively, from 5-V DC of the LMZ14203TZ-ADJ DC-DC.
These supply rails power up both FPGA cores and IOs of the isolated and non-isolated section.
4.4.3 Transformer (750315240) and Push-Pull Transformer Driver (SN6505A)The SN6505 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC convertersusing push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate drive,comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary outputsignals that alternately turn the two output transistors on and off.
The SN6505 transformer driver is designed for low-power push-pull converters with input and outputvoltages in the range of 3 to 5.5 V. While converter designs with higher output voltages are possible, takecare that higher turns ratios do not lead to primary currents that exceed the SN6505 specified currentlimits.
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The TIDA-00732 uses the recommended transformer inform the SN6505A datasheet. For transformerselection and isolation power supply design, see the SN6505A datasheet. Table 5 shows key parametersof the transformer.
Table 5. Transformer Specification(Part No: 750315240, Mfr: WE)
PARAMETER VALUEVoltage-time 23 µsTurns ratio 1.1:1 ±2%
Switching frequency 150 kHz minDi-electric 6250 RMS, 1 sec
4.5 Host InterfaceThis design supports the following host interfaces to evaluate system performance:• Precision host interface (PHI)
PHI is TI’s SAR ADC evaluation platform, which supports the entire TI SAR ADC family. By using PHI,the TIDA-00732 easily communicates with the host PC using a USB interface. PHI supports theADS9110 multiSPI and onboard configuration I2C EEPROM interface.PHI GUI software can be used to evaluate both AC and DC parameter of the ADS9110. For moreinformation on PHI, refer to ADS9110 EVM-PDK.
• Beaglebone Black interfaceThe TIDA-00732 has Beaglebone Black interface, which can be used to interface the Sitara™ ARM®embedded processor and make the DAQ system with an embedded platform.
Isolated power supply ADC-side isolated power supply
12-V DC input
Digital isolatorHost interface connector (PHI)
ADC-side glue logic
Isolated analog inputs
BeagleBone Black interface connectors
ADC and front-end
Host-side power supply
(non-isoloated)
2
13
4
5
6789
10
11
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5 Getting Started Hardware
Figure 17. TIDA-00732 Hardware
5.1 Hardware Functional BlockFigure 17 shows various hardware functional blocks of the TIDA-00732 and function of each block:1. 12-V DC power supply input connector accepts 9- to 12-V DC input to power the TIDA-00732.2. The host side DC-DC buck convertor generates 5 V from the 12-V input.3. An isolation transformer for power supply isolation and isolated power is generated with the SN6506
push pull transformer driver.4. Isolated power supply rails block that generates 5-V, 3.3-V, 1.8-V and 1.2-V power rails.5. Differential analog inputs connector.6. Analog front-end circuits (ADC ADS9110, OPA625, REF4505).7. FPGA that holds CONVST signal generation logic and glue logic for the interface.8. Digital isolator for data isolation (SPI and I2C).9. PHI interface connector, which uses the TIDA-00732 to communicate with the host through USB
interface.10. Beaglebone Black interface, which allows the TIDA-00732 to communicate with the embedded
platform.11. FPGA to implement glue logic for PHI and Beaglebone Black interface selection.
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5.2 Headers and Jumper SettingThe TIDA-00732 has a number of jumpers that must be selected properly before powering up the module.1. Input common-mode jumper (see Table 6)
Table 6. Input Common-Mode Selection
J10 J11 DESCRIPTIONCLOSE OPEN 2.25-V select (default)CLOSE CLOSE See the ADS9110 EVM (Section 2.2.2) for
other common-mode settings.EVM Jumper reference J10 and J11corresponding to TIDA-00732 reference ofJ1 and J2, respectively.
OPEN CLOSE
OPEN OPEN
2. Power supply jumper (see Table 7)
Table 7. Power Supply Selection
REFERENCE DEFAULT DESCRIPTION
J17 2,31P8V source selectionPin 1,2—From PHI boardPin 2,3—Onboard
J12 2,35-V source selectionPin 1,2—From PHIPin 2,3—Onboard
J13 2,31P8V_ISO—Source selectionPin 1,2—From PHIPin 2,3—Onboard
J24 2,3FPGA (U24C)—IO Bank0 voltage selectionPin 1,2—3.3 VPin 2,3—1.8 V
J4 OPENEEPROM (U21)—Write protect enableOPEN—Write protect enableCLOSE—Write protect disable
J21 OPENEEPROM (U28)—Write protect enableOPEN—Write protect enableCLOSE—Write protect disable
3. Mode selection jumperThis mode selection jumper configures the TIDA-00732 in any one of the modes shown in Table 8.
Table 8. Mode Selection Switch
J16 J22 DESCRIPTION1,2 1,2 PHI without jitter logic (default)1,2 2,3 Reserved2,3 1,2 PHI with jitter2,3 2,3 Reserved
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4. Programming headerThe programming of Xilinx FPGA can be done using the 6-pin header listed in Table 9.
Table 9. FPGA Programming Header
REFERENCE DESCRIPTIONJ14 FPGA(U24) JTAG HeaderJ19 FPGA(U25) JTAG Header
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6 Getting Started Firmware
6.1 PHI GUI PanelThe PHI GUI software, which is based on the LabView™ platform, validates the TIDA-00732. Figure 18shows the available test options in PHI GUI.
Figure 18. PHI GUI Demonstrate AC Parameter—SpectralAnalysis
Figure 19. PHI GUI Demonstrate AC Parameter—TimeDomain Display
The PHI GUI can be used to validate the following system key specifications:1. Linearity analysis
• DNL• INL• Accuracy
2. Histogram analysis• Effective resolution
3. Spectral analysis• SNR• THD• SFDR• SINAD• ENOB
PHI GUI software can be found at http://www.ti.com/product/ADS9110/toolssoftware.
PC or Laptop
USB Interface
DC Power Supply
Ultra Low Distortion Function
Generator
100-kHz Band Pass
Filter
TIDA-00732
12-V DC
PHI Debug ModuleDifferential Input Signal
5 VPP, 100 kHz
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7 Test SetupFigure 20 shows the TIDA-00732 test setup to validate complete signal chain performance of isolatedhigh-speed, high SNR (18-bit, 2-MSPS) analog input DAQ module.
The test needs to evaluate the performance of a high-speed (2-MSPS) and high-resolution (18-bit) systemthat is compliant with testing requirements. The setup has a DS360, Standard Research Systemsprecision ultralow distortion waveform generator, which is capable of generating a sine pattern with asignal frequency range of 10 mHz to 200 kHz. The device needs high precision with very low ripple powersupply to power entire system. This design requires 9- to 12-V DC at 250 mA with high precision and lowripple power. The 12-V DC voltage is generated using Keithley triple output power supply (2230G). It iscapable of generating up to 30 V with 0.03% voltage accuracy and 0.1% current accuracy withsimultaneous voltage and current indication.
The data capturing is established using USB 2.0 interface. The testing computer must have one USB portand support USB 2.0 specification.
Sometimes the signal source may also have noise on top of the signal while generating a sine wave with100 kHz. To remove this unwanted noise, a 100-kHz differential band pass filler is connected in betweenthe signal source and TIDA-00732 input connector. This will attenuate input noise at a 100-kHz band.
Figure 20. TIDA-00732 Test Setup
The PHI GUI software must be installed in the host computer before testing.1. Plug the PHI interface board to the Samtec connector (J18).2. Connect 12-V DC of power to the J5 connector. Ensure the positive terminal is connected to the
positive input (Pin 2 of J5) and the negative terminal is connected to the negative input (Pin 1 of J5).3. Connect the differential output of function generator to the differential input terminal (J7 and J8 SMA
connector) of the TIDA-00732 board (for a 100-kHz input signal frequency, connect the 100-kHz bandpass filter in between signal source and the TIDA-00732 board). Also, make sure both differentialsignals are balanced and configure as shown in Table 10.
4. Connect the PHI module to the PC or laptop using microUSB cable.5. Switch on the power supply.6. Switch on the signal source and set the signal source parameter. Then, enable the output.7. Run the PHI GUI software, go to spectrum analysis tab and capture result with various input signal
frequency.
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Table 10. Test Conditions
FUNCTION GENERATORPattern Sine
Voltage 7.23 VPP(Adjust to cover full input dynamic range)
Frequency 2 kHz and 100 kHzSource impedance 150 Ω
POWER SUPPLY12-V DC at 250 mA
To evaluate jitter mitigation and SNR performance improvement in the TIDA-00732, the following testcases were created:1. Configure the TIDA-00732 as no jitter cleaning mode by using mode switch (J16, J22).2. Generate a sine wave with 7.32 VPP (adjust to cover full input dynamic range), 2 kHz.3. Run PHI software in debug mode.4. Go to the FFT tab and capture SNR, THD, ENOB.
The test results are taken for both 2-kHz and 100-kHz input frequency with and without jitter cleanermode.
NOTE:1. While testing with a 100-kHz input signal frequency, bandpass filter is used in
between the signal source and the TIDA-00732 module.2. Load the corresponding FPGA MCS file for with or without jitter mode.
Input Signal Frequency (kHz)
SN
R (
dB)
1 10 10070
75
80
85
90
95
100
105
110With Jitter CleaningWithout Jitter Cleaning
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8 Test DataTable 11 shows test results for with and without jitter cleaning mode with input signal frequencies of 2 kHzand 100 kHz. The datasheet SNR performance of the ADS9110 at a 100-KHz input signal is 95.5 dB.Table 10 shows that the SNR performance of the host generated CONVST (without jitter cleaning mode)is 82 dB while the locally generated CONVST (with jitter cleaning mode) is 94.34 dB, which is close to thedatasheet’s specification. This result shows that signal chain performance degraded due to isolator jitter,and the solution provided in the TIDA-00732 gives almost a 12-dB improved SNR performance.
Also, the serial data rate of SPI can be reduced to 49 MHz by using multiSPI while operating theADS9110 with a maximum sample rate of 2 MSPS.
Table 11. Test Result Comparison
PARAMETERTIDA-00732 TEST RESULT
HOST GENERATED CONVST(WITHOUT JITTER CLEANING)
LOCALLY GENERATED CONVST(WITH JITTER CLEANING)
fIN (kHz) 2 100 2 100 100SCLK (MHz) 49 49 49 49 49MODE QSDO QSDO QSDO QSDO QSDOSample rate (MSPS) 1.64 1.64 1.64 1.64 2SNR (dB) 98.89 82.00 99.32 94.34 94.28THD (dB) 121.01 112.64 120.78 113.86 113.72ENOB 15.61 13.32 16.20 15.37 15.36
Figure 21. SNR Performance Comparison
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
31
33
35
37
39
16
18
20
22
24
26
28
30
32
34
36
38
40
41 42
43 44
45 46
J1
TSW-123-07-G-D
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
31
33
35
37
39
16
18
20
22
24
26
28
30
32
34
36
38
40
41 42
43 44
45 46
J2
TSW-123-07-G-D
GND10.0R110.0R310.0R510.0R710.0R910.0R1110.0R1310.0R1510.0R1710.0R1910.0R2110.0R2310.0R2510.0R2710.0R2910.0R3110.0R3310.0R3510.0R3710.0R3910.0R4110.0R43
10.0R210.0R410.0R610.0R810.0R1010.0R1210.0R1410.0R1610.0R1810.0R2010.0R2210.0R2410.0R2610.0R2810.0R3010.0R3210.0R3410.0R3610.0R3810.0R4010.0R4210.0R44
GPIO_38GPIO_34GPIO_66GPIO_69PRUO_15_OUTGPIO_23GPIO_47GPIO_27GPIO_22PRU1_12GPIO_36GPIO_32PRU1_8PRU1_9GPIO_10GPIO_9GPIO_8GPIO_78PRU1_6PRU1_4PRU1_2PRU1_0
GPIO_39GPIO_35GPIO_67GPIO_68PRUO_14_OUTGPIO_26GPIO_46GPIO_65PRU1_13GPIO_37GPIO_33GPIO_61PRU1_10PRU1_11GPIO_11GPIO_81GPIO_80GPIO_79PRU1_7PRU1_5PRU1_3PRU1_1
BBB (P8)
BBB (P9) GND
GNDGND
VDD_3V3 VDD_3V3VDD_5VSYS_5VPWR_BUT VDD_5V SYS_5V
VDD_ADC GNDA_ADC
10.0R12410.0R12610.0R12810.0R13010.0R13210.0R13410.0R13610.0R13810.0R14010.0R142
10.0R14610.0R14810.0R15010.0R152
10.0R12310.0R12510.0R12710.0R12910.0R13110.0R13310.0R13510.0R13710.0R13910.0R14110.0R14310.0R14410.0R14510.0R14710.0R14910.0R151
GPIO_30GPIO_31GPIO_48GPIO_5BBB_I2C2_SCLGPIO_3GPIO_49PRUO_7PRUO_5PRUO_1PRUO_0AIN4AIN6AIN2AIN0PRUO_6
BBB_SYS_RESETNGPIO_60GPIO_50GPIO_51GPIO_4BBB_I2C_SDAGPIO_2GPIO_15PRU1_16_INPRUO_3PRUO_2
AIN5AIN3AIN1PRUO_4
BBB_ADC_SDIBBB_ADC_CSnBBB_ADC_SCLK
BBB_ADC_RESETnBBB_ADC_RVS
BBB_ADC_SDO0BBB_ADC_SDO1BBB_ADC_SDO2BBB_ADC_SDO3
BBB_GPIO0BBB_GPIO1BBB_GPIO2BBB_GPIO3BBB_GPO0BBB_GPIO4BBB_GPIO5BBB_GPIO6BBB_GPIO7BBB_GPIO8BBB_GPIO9
BBB_GPIO10BBB_GPIO11BBB_GPIO12BBB_GPIO13BBB_GPIO14BBB_GPIO15BBB_GPIO16
BBB_GPIO32BBB_GPIO17BBB_GPIO18BBB_GPIO19
BBB_GPIO20BBB_GPIO21BBB_GPIO22BBB_GPIO23BBB_GPIO24BBB_GPIO25BBB_GPIO26BBB_GPIO27BBB_GPIO28BBB_GPIO29BBB_GPIO30BBB_GPIO31
BBB_GPO1
BBB_GPIO44
BBB_GPIO47BBB_GPIO48BBB_GPIO49BBB_GPIO50BBB_GPIO54BBB_GPI0
BBB_GPIO52
BBB_GPIO53
BBB_GPIO35BBB_GPIO36BBB_GPIO37BBB_GPIO38BBB_GPIO39BBB_GPIO40
BBB_GPIO42BBB_GPIO43
BBB_SYS_RESETN
11
TP21
11
TP18
11
TP19
11
TP20
11
TP22
11
TP23
11
TP24
5VDC VDD_5V
11TP15
VDD_3V3
VDD_5V
SYS_5V
PWR_BUT
11TP25
11TP30
11TP31
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
4545
4747
4949
5151
5353
5555
5757
5959
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
4242
4444
4646
4848
5050
5252
5454
5656
5858
6060
GNDMP1
GNDMP2
GNDMP3
GNDMP4
J18
QTH-030-03-L-D-A
EVM2_PRESENTn
EVM2_ADC_RVS
EVM2_DVDD
10µFC89
GND GND
GND
GND
EVM2_REG_5V5
10µFC87
EVM2_ID_SCL
EVM2_ID_SDA
EVM2_ADC_SDIEVM2_ADC_CONVST
EVM2_ADC_CSnEVM2_ADC_SCLK
EVM2_ADC_RESETn 0R186
0R189
0R190
0R193
0R195
0R200
EVM2_ADC_SDO0EVM2_ADC_SDO1EVM2_ADC_SDO2EVM2_ADC_SDO3
0R210
0R212
0R213
0R215
0R199
GND
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
4545
4747
4949
5151
5353
5555
5757
5959
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
4242
4444
4646
4848
5050
5252
5454
5656
5858
6060
GNDMP1
GNDMP2
GNDMP3
GNDMP4
J3
QTH-030-03-L-D-A
EVM1_PRESENTn
EVM1_ADC_SDIEVM1_ADC_CONVST
EVM1_ADC_RVS
EVM1_ADC_SCLKEVM1_ADC_CSn
EVM1_ADC_SDO0EVM1_ADC_SDO1EVM1_ADC_SDO2EVM1_ADC_SDO3
EVM1_ADC_RESETn
EVM1_DVDD
10µFC83
AGND_ISO AGND_ISO
AGND_ISO
AGND_ISO
EVM1_REG_5V5
EVM1_ID_PWR
10µFC84
AGND_ISO
10µFC82
AGND_ISO
EVM1_ID_SCL
EVM1_ID_SDA
0R160
0R1620R163
0R1640R166
0R169
0R170
0R171
0R1720R1730R175
5V INPUT SUPPLY FOR BBB
TI-PHI PLATFORM INTERFACEWITHOUT ISOLATION
TI-PHI PLATFORM INTERFACEWITH ISOLATION
BEAGLE BONE BLA CK INTERFACE WITH ISOLATION
1P8V
EVM2_ID_PWR
10µFC90
GND
A01
A12
A23
VSS4
SDA5
SCL6
WP7
VCC8
U21
BR24G32FVT-3AGE2
WP
0.1µF
C75
0.1µFC78
AGND_ISO
AGND_ISO
AGND_ISO
EVM1_ID_SCL
EVM1_ID_SDA
10.0k
R246
WP
A01
A12
A23
VSS4
SDA5
SCL6
WP7
VCC8
U28
BR24G32FVT-3AGE2
EVM2_ID_PWR
EVM2_ID_PWR
10.0k
R251
WP1
0.1µF
C220
0.1µFC222
EVM2_ID_PWR
EVM2_ID_SCL
EVM2_ID_SDA
GND
GND
GNDWP1
1
2
J4
61300211121
1
2
J21
61300211121
600 ohm
L1
BBB_GPIO33 BBB_GPIO45BBB_GPIO46BBB_GPIO34
11
TP51
11
TP50
EVM1_ID_PWREVM1_ID_PWR
EVM1_ID_PWR
Copyright © 2016, Texas Instruments Incorporated
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29TIDUB85A–April 2016–Revised May 2016Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
9 Design Files
9.1 SchematicsTo download the schematics, see the design files at TIDA-00732.
Figure 22. Connector Schematic
D11
D23
VCC2
GND4
EN5
CLK6
U1
SN6505ADBVR
3
2
1
4
5
6
110µH
T1D1
MBR0520LT1G
D3
MBR0520LT1GGND
1µFC2
AGND_ISO
0.1µFC3
47µFC5
10µFC4
1000pFC7
AGND_ISO
0
R51
LDO_IN_ISO
0R53DNP
0R54DNP
0R550R56
DNP0R57
DNP0R580R59
DNP0R60
DNP
AGND_ISO
0.1R52
47µFC9
1µFC10
AGND_ISO
AGND_ISO
AGND_ISO
5V_ISO1
0.1µFC11 0.1µFC12
AGND_ISOGND
3P3V 3P3V_ISO
GND AGND_ISO
CONVST
CSn
SRESETn ISO_ADC_RESETn
ISO_ADC_CSn
ISO_ADC_CONVST
ISO_ADC_RVS
10.0k
R61
3P3V
10.0k
R623P3V_ISO
0.1µFC25 0.1µFC26
GND
3P3V 3P3V_ISO
GND AGND_ISO
SDI
SCLK ISO_ADC_SCLK
ISO_ADC_SDI
10.0k
R72
10.0k
R73
3P3V_ISO
0.1µFC440.1µFC43
ISO_ADC_SDO3
ISO_ADC_SDO2
ISO_ADC_SDO1SDO1
SDO2
SDO3
10.0k
R75
10.0k
R74
GND AGND_ISO
3P3V 3P3V_ISO
GND
TP1TP2
AGND_ISO
AGND_ISO
3P3V
3P3V
10µFC8
GND
+12VDC_IN
+12VDC_IN
1
2
J5
ED120/2DS
MBRS4201T3G
200V
D2
FB
118kR219
20.5kR224
249kR221
0.022µFC42
0.01µF
C41
10µF
C39
10µFC40 22µF
C91
600 ohm
L2VIN
1
EN3
SS5
GND4
FB6
RON2
VOUT7
EP8
U3
LMZ14203TZ-ADJ/NOPB
+12VDC 5VDC
5.62kR220
1.07kR223
0.01R225
Red
21
D8
1.2kR226
GND
Red
21
D7
1.2kR222
GNDGND GNDGND
GND
GNDGND
5016
TP16
5016
TP325016
TP3
ISOLATIONBARRIER
5016TP35
5016TP42
5016TP45
5VDC
3P3V
1P8V
5016TP461P2V
5016
TP26
5016
TP27
5016
TP28
5016
TP29
GND
5V_ISO
1P8V_ISO
3P3V_ISO1P2V_ISO
A1P8V_ISO5016
TP40
5016TP44
5016TP47
5016TP41
5016TP43
5016
TP36
5016
TP37
5016
TP38
5016
TP39
AGND_ISO
VCC11
GND12
INA3
INB4
OUTC5
OUTD6
EN17
GND18
GND29
EN210
IND11
INC12
OUTB13
OUTA14
GND215
VCC216
U9
VCC11
GND12
INA3
INB4
INC5
IND6
NC7
GND18
GND29
EN210
OUTD11
OUTC12
OUTB13
OUTA14
GND215
VCC216
U12
ISO7840DWR
SDO0 ISO_ADC_SDO03P3V_ISO
33.0
R207ADC_CONVST1ADC_CONVST_FPGA
VCC11
SDA12
SCL13
GND14
GND25
SCL26
SDA27
VCC28
U35
ISO1541DR
3P3V
0.1µFC229
GND
0.1µFC230
AGND_ISO
3P3V_ISO
GND AGND_ISO
1.5kR50
1.5k
R205
1.5kR204
1.5k
R206
NISO_SDA
NISO_SCL
ISO_SDA
ISO_SCL
33.0
R260
1000pF
C236
AGND_ISOGND
VCC11
GND12
INA3
INB4
INC5
IND6
NC7
GND18
GND29
EN210
OUTD11
OUTC12
OUTB13
OUTA14
GND215
VCC216
U5
ISO7840DWR
RVS
1 2
J25
61300211121
OUT1
NC2
SENSE3
6P4V24
6P4V15
3P2V6
GND7
1P6V8
0P8V9
0P4V10
0P2V11
0P1V12
EN13
NR14
IN15
IN16
NC17
NC18
NC19
OUT20
PAD21
U2
TPS7A4700RGWR
+12VDC
10µF
C6
100µF
C237
PLACE GND TESTPOINS FOUR CORNER OF PCBCORRESPOINDING LOCATION PLACE AGND_ISO TESTPOINS FOUR CORNER OF
PCBCORRESPOINDING LOCATION
Copyright © 2016, Texas Instruments Incorporated
Design Files www.ti.com
30 TIDUB85A–April 2016–Revised May 2016Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Figure 23. Power and Isolators Schematic
SDO-218
CONVST1
RST2
DVDD16
REFM4
SDO-317
REFP5
NC6
AVDD14
GND15
AVDD13
NC3
EP25
SDO-119
SDO-020
RVS21
SDI22
SCLK23
CS24
REFP7
REFM8
AINP9
AINM10
NC12
GND11
U19
ADS9110IRGER
3
1
2
4
6
5
V+
V-
U18OPA625IDBVR
2 4
53
U16SN74LVC1G17DCKR
3P3V_ISO
0.1µF
C50
100kR87
10.0k
R90
1µFC56
12
S1
EVQPNF04M
3P3V_ISO
ADC_RESETn
ADC_CSnADC_SCLKADC_SDIADC_RVS
ADC_SDO0ADC_SDO1ADC_SDO2ADC_SDO3
1µF
C63
1µFC62
1P8V_ISO
2
4
1
53
U17
SN74LVC1G08DCKR
ADC_MRESETn
ADC_SRESETn
0.1µF
C51
1P8V_ISO
10.0kR93
5V_ISO
AGND_ISO1.00k
R99
AGND_ISO
1.00k
R98
1000pFC67
1µFC65
AGND_ISO
OPA625_CM
2.21
R95
3
1
2
4
6
5
V+
V-
U20OPA625IDBVR
5V_ISO
AGND_ISO
1.00kR105
AGND_ISO
1.00k
R104
1000pFC73
1µFC70
AGND_ISO
2.21
R101
0.01µFC66
AGND_ISO
0.01µFC71
AGND_ISO
AGND_ISO
0
R102DNP
1µFC72DNP
10.0k
R100DNP
10µFC69DNP
AGND_ISO
AGND_ISO
5V_ISOAGND_ISO
AGND_ISO AGND_ISOAGND_ISO
AGND_ISO AGND_ISO
1
2 3 4 5
J7
142-0701-801
1
2 3 4 5
J8
142-0701-801
0
R97
0
R103
0.01µFC68
AGND_ISO
AGND_ISO
1
2
3
J6TSM-103-01-L-SV
AGND_ISO
100R96
10µFC64
1
2
3
J9
TSM-103-01-L-SV
AGND_ISO
100
R108
10µFC76
REFOUTTEST_4.3V
VIN+
VIN-
TEST_0.2V
AGND_ISO
ADC_CSn
ADC_SCLK
ADC_SDI
ADC_RVS
ADC_SDO0
ADC_SDO1
ADC_SDO2
ADC_SDO3
ADC_SRESETn
A1P8V_ISO
1P8V_ISO
AGND_ISO
BCLK_ISO
0R261
ADC_CONVST
0R45DNP
0.01µFC214DNP
10µF
C219
AGND_ISO
10µF
C228
AGND_ISO
0
R208
REFOUT
OPA625_CM
REFBUF
OPA625_CM
OPA625_CM
REFOUT
D1
CLK2
GND3
~Q4
VCC5
U33
SN74AUP1G80DCK
0.1µF
C192
AGND_ISO
ADC_MRESETn
ADC_RESETn511
R244
ADC_RESETn
Copyright © 2016, Texas Instruments Incorporated
www.ti.com Design Files
31TIDUB85A–April 2016–Revised May 2016Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Figure 24. Analog Front-End and ADC Schematic
IO_L01P_0110
IO_L01N_0111
IO_L02P_0/VREF_0112
IO_L02N_0113
IO_L04P_0114
IO_L03P_0115
IO_L04N_0116
IO_L03N_0117
IO_L05P_0120
IO_L05N_0121
IO_L06P_0/GCLK4124
IO_L07P_0/GCLK6125
IO_L06N_0/GCLK5126
IO_L07N_0/GCLK7127
IO_L08P_0/GCLK8129
IO_L09P_0/GCLK10130
IO_L08N_0/GCLK9131
IO_L09N_0/GCLK11132
IO_L10P_0134
IO_L10N_0135
IO_L11P_0138
IO_L11N_0139
IO_L12P_0/VREF_0141
IO_0142
IO_L12N_0/PUDC_B143
BA
NK
0
U24A
XC3S50AN-5TQG144C
IO_L02P_1/LDC175
IO_L01P_1/HDC76
IO_L02N_1/LDC077
IO_L01N_1/LDC278
IO_179
IO_L03P_182
IO_L04P_1/RHCLK083
IO_L03N_184
IO_L04N_1/RHCLK185
IO_L05P_1/RHCLK287
IO_L05N_1/TRDY1/RHCLK388
IO_L06P_1/RHCLK490
IO_L07P_1/IRDY1/RHCLK691
IO_L06N_1/RHCLK592
IO_L07N_1/RHCLK793
IO_L08P_196
IO_L08N_198
IO_L09P_199
IO_L09N_1101
IO_L10P_1102
IO_L11P_1103
IO_L10N_1104
IO_L11N_1105
BA
NK
1
U24B
XC3S50AN-5TQG144C
IO_L01P_2/M137
IO_L01N_2/M038
IO_L02P_2/M239
IO_L02N_2/CSO_B41
IO_L03P_2/RDWR_B42
IO_L04P_2/VS243
IO_L03N_2/VS144
IO_L04N_2/VS045
IO_L05P_246
IO_L06P_247
IO_L05N_2/D748
IO_L06N_2/D649
IO_L07P_2/D550
IO_L07N_2/D451
IO_L08P_2/GCLK1454
IO_L08N_2/GCLK1555
IO_L09P_2/GCLK057
IO_L10P_2/GCLK258
IO_L09N_2/GCLK159
IO_L10N_2/GCLK360
IO_2/MOSI/CSI_B62
IO_L11P_2/AWAKE63
IO_L11N_2/DOUT64
IO_L12P_2/INIT_B67
IO_L12N_2/D368
IO_L13P_2/D269
IO_L14P_2/D170
IO_L13N_2/D0/DIN/MISO71
IO_L14N_2/CCLK72
BA
NK
2
U24C
XC3S50AN-5TQG144C
IO_L02P_33
IO_L01P_34
IO_L02N_35
IO_L01N_36
IO_L03P_37
IO_L03N_38
IO_L04P_310
IO_L04N_3/VREF_311
IO_L05P_3/LHCLK012
IO_L05N_3/LHCLK113
IO_L06P_3/LHCLK215
IO_L06N_3/IRDY2/LHCLK316
IO_L07P_3/LHCLK418
IO_L08P_3/TRDY2/LHCLK619
IO_L07N_3/LHCLK520
IO_L08N_3/LHCLK721
IO_L09P_324
IO_L09N_325
IO_L10P_327
IO_L11P_328
IO_L10N_329
IO_L11N_330
IO_L12P_331
IO_L12N_332
BA
NK
3
U24D
XC3S50AN-5TQG144C
IP_L13P_333
IP_L13N_3/VREF_335
IP_2/VREF_253
IP_1/VREF_180
IP_1/VREF_197
IP_0/VREF_0123
IP_0140
U24E
XC3S50AN-5TQG144C
TMS1
TDI2
DONE73
TDO107
TCK109
PROG_B144
SUSPEND74
U24F
XC3S50AN-5TQG144C
VCCAUX36
VCCAUX66
VCCAUX108
VCCAUX133
VCCINT22
VCCINT52
VCCINT94
VCCINT122
VCCO_0119
VCCO_0136
VCCO_186
VCCO_195
VCCO_240
VCCO_261
VCCO_314
VCCO_323
U24G
XC3S50AN-5TQG144C
GND9
GND17
GND26
GND34
GND56
GND65
GND81
GND89
GND100
GND106
GND118
GND128
GND137
U24H
XC3S50AN-5TQG144C
AGND_ISO
3P3V_ISOVCCO_0
1P2V_ISO
AGND_ISO
ISO_ADC_CONVST
ISO_ADC_SCLK
ISO_ADC_SDI
ADC_CONVST
ADC_CSn
ADC_SCLK
ADC_SDI
ADC_RVSADC_SDO0
ADC_SDO1ADC_SDO2
ADC_SDO3
1P8V IO 3P3 V IO/ 3P3VI O
3P3V_ISO
5
4
1
2
3
6
J14
PEC06SAAN
3P3V_ISO
AGND_ISO
100R115100R116
100R117100R118TMS_ISO
TDI_ISOTDO_ISOTCK_ISO
TMS_ISOTCK_ISOTDO_ISOTDI_ISO
1.00kR119
1.00kR120
1.00kR121
X_SUSPENDX_DONE
X_PROG_B
Red
2 1
D5
3P3V_ISO
1.00kR122 X_INIT
X_SUSPEND
X_DONE
X_PROG_B
AGND_ISO
X_INIT
3P3V_ISO
33
R167
AGND_ISO
0.1µF
C85
AGND_ISO
33
R161
BCLK_ISO
ISO_ADC_RESETn
ISO_ADC_CSn
X_VS0
X_VS1
X_VS2
X_VS0X_VS1
X_VS2
3P3V_ISO1.00kR174
1.00kR1761.00kR178
1.00kR177
AGND_ISO
DNP33 MHz READ CLOCK
1.00kR165
X_M0X_M1
X_M2
X_M0X_M1X_M2
1.00kR154
1.00kR1561.00kR158
3P3V_ISO
AGND_ISO
DNP
TDI_ISOTCK_ISO
TDO_ISO
3P3V_ISO1.00kR153
1.00kR155
1.00kR157
1.00kR168
1.00kR159 TMS_ISO
ISO_ADC_SDO0
ISO_ADC_SDO3
ISO_ADC_SDO2
ISO_ADC_SDO1
1nF
C102
1nF
C103
1nF
C104
1nF
C105
47nF
C108
47nF
C109
47nF
C110
47nF
C111
10µF
C106
10µF
C107
AGND_ISO
1P2V_ISO
1nF
C92
1nF
C93
1nF
C94
1nF
C95
47nF
C98
47nF
C99
47nF
C100
47nF
C101
10µF
C96
10µF
C97
AGND_ISO
3P3V_ISO
1nF
C112
1nF
C113
1nF
C114
1nF
C115
47nF
C124
47nF
C125
47nF
C126
47nF
C127
10µF
C120
10µF
C121
AGND_ISO
1nF
C134
1nF
C135
1nF
C136
1nF
C137
47nF
C146
47nF
C147
47nF
C148
47nF
C149
10µF
C142
10µF
C143
AGND_ISO
1nF
C116
1nF
C117
1nF
C118
1nF
C119
47nF
C129
47nF
C130
47nF
C131
47nF
C132
10µF
C122
10µF
C123
AGND_ISO
3P3V_ISO
1nF
C138
1nF
C139
1nF
C140
1nF
C141
47nF
C151
47nF
C152
47nF
C153
47nF
C154
10µF
C144
10µF
C145
AGND_ISO
3P3V_ISO1P8V_ISO
3P3V_ISO
VCCAUX
VCCINT
VCCO_0VCCO_2
VCCO_1VCCO_3
Red
21
D9
330R227
3P3V_ISO
Red
21
D10
330R228
3P3V_ISO
Red
21
D11
330R229
3P3V_ISO
Red
21
D12
330R230
3P3V_ISO
STS0_LEDSTS1_LEDSTS2_LEDSTS3_LED
STS0_LEDSTS1_LEDSTS2_LEDSTS3_LED
1.00kR243
1
2
3
J22
HT
SW
-10
3-0
7-G
-S
AGND_ISO
3P3V_ISO
1.00kR107
1
2
3
J16
HT
SW
-10
3-0
7-G
-S
AGND_ISO
3P3V_ISO
MODE_SW1MODE_SW0
MODE_SW1
MODE_SW0
11
TP48
BCLK_ISO
EVM1_ADC_RESETn
EVM1_ADC_CONVSTEVM1_ADC_RVS
EVM1_ADC_SCLK
EVM1_ADC_CSn
EVM1_ADC_SDI
EVM1_ADC_SDO0EVM1_ADC_SDO3
EVM1_ADC_SDO2EVM1_ADC_SDO1
1
2
3
J24
HTSW-103-07-G-S
DNP
1P8V_ISO 3P3V_ISOVCCO_0
VCCO_0
1P8V_ISO
1P8V IO3P3 V IO
VCC4
E/D1
GND2
OUT3
125 MHz
Y1
MCLK
BCLK_ISO
ADC_CONVST1
ADC_SRESETn
ISO_ADC_RVS
ADC_MRESETn
Pin 2,3 Short(default)
Copyright © 2016, Texas Instruments Incorporated
Design Files www.ti.com
32 TIDUB85A–April 2016–Revised May 2016Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Figure 25. FPGA 1—Isolated End Schematic
IO_L01P_0110
IO_L01N_0111
IO_L02P_0/VREF_0112
IO_L02N_0113
IO_L04P_0114
IO_L03P_0115
IO_L04N_0116
IO_L03N_0117
IO_L05P_0120
IO_L05N_0121
IO_L06P_0/GCLK4124
IO_L07P_0/GCLK6125
IO_L06N_0/GCLK5126
IO_L07N_0/GCLK7127
IO_L08P_0/GCLK8129
IO_L09P_0/GCLK10130
IO_L08N_0/GCLK9131
IO_L09N_0/GCLK11132
IO_L10P_0134
IO_L10N_0135
IO_L11P_0138
IO_L11N_0139
IO_L12P_0/VREF_0141
IO_0142
IO_L12N_0/PUDC_B143
BA
NK
0
U25A
XC3S50AN-5TQG144C
IO_L02P_1/LDC175
IO_L01P_1/HDC76
IO_L02N_1/LDC077
IO_L01N_1/LDC278
IO_179
IO_L03P_182
IO_L04P_1/RHCLK083
IO_L03N_184
IO_L04N_1/RHCLK185
IO_L05P_1/RHCLK287
IO_L05N_1/TRDY1/RHCLK388
IO_L06P_1/RHCLK490
IO_L07P_1/IRDY1/RHCLK691
IO_L06N_1/RHCLK592
IO_L07N_1/RHCLK793
IO_L08P_196
IO_L08N_198
IO_L09P_199
IO_L09N_1101
IO_L10P_1102
IO_L11P_1103
IO_L10N_1104
IO_L11N_1105
BA
NK
1
U25B
XC3S50AN-5TQG144C
IO_L01P_2/M137
IO_L01N_2/M038
IO_L02P_2/M239
IO_L02N_2/CSO_B41
IO_L03P_2/RDWR_B42
IO_L04P_2/VS243
IO_L03N_2/VS144
IO_L04N_2/VS045
IO_L05P_246
IO_L06P_247
IO_L05N_2/D748
IO_L06N_2/D649
IO_L07P_2/D550
IO_L07N_2/D451
IO_L08P_2/GCLK1454
IO_L08N_2/GCLK1555
IO_L09P_2/GCLK057
IO_L10P_2/GCLK258
IO_L09N_2/GCLK159
IO_L10N_2/GCLK360
IO_2/MOSI/CSI_B62
IO_L11P_2/AWAKE63
IO_L11N_2/DOUT64
IO_L12P_2/INIT_B67
IO_L12N_2/D368
IO_L13P_2/D269
IO_L14P_2/D170
IO_L13N_2/D0/DIN/MISO71
IO_L14N_2/CCLK72
BA
NK
2
U25C
XC3S50AN-5TQG144C
IO_L02P_33
IO_L01P_34
IO_L02N_35
IO_L01N_36
IO_L03P_37
IO_L03N_38
IO_L04P_310
IO_L04N_3/VREF_311
IO_L05P_3/LHCLK012
IO_L05N_3/LHCLK113
IO_L06P_3/LHCLK215
IO_L06N_3/IRDY2/LHCLK316
IO_L07P_3/LHCLK418
IO_L08P_3/TRDY2/LHCLK619
IO_L07N_3/LHCLK520
IO_L08N_3/LHCLK721
IO_L09P_324
IO_L09N_325
IO_L10P_327
IO_L11P_328
IO_L10N_329
IO_L11N_330
IO_L12P_331
IO_L12N_332
BA
NK
3
U25D
XC3S50AN-5TQG144C
IP_L13P_333
IP_L13N_3/VREF_335
IP_2/VREF_253
IP_1/VREF_180
IP_1/VREF_197
IP_0/VREF_0123
IP_0140
U25E
XC3S50AN-5TQG144C
TMS1
TDI2
DONE73
TDO107
TCK109
PROG_B144
SUSPEND74
U25F
XC3S50AN-5TQG144C
VCCAUX36
VCCAUX66
VCCAUX108
VCCAUX133
VCCINT22
VCCINT52
VCCINT94
VCCINT122
VCCO_0119
VCCO_0136
VCCO_186
VCCO_195
VCCO_240
VCCO_261
VCCO_314
VCCO_323
U25G
XC3S50AN-5TQG144C
GND9
GND17
GND26
GND34
GND56
GND65
GND81
GND89
GND100
GND106
GND118
GND128
GND137
U25H
XC3S50AN-5TQG144C
GND
3P3V1P8V
1P2V
GND
1P8V IO
Text String
3P3VI O
3P3V
5
4
1
2
3
6
J19
PEC06SAAN
3P3V
GND 100R192100R194100R197100R198
TMSTDITDOTCK
TMSTCKTDOTDI
1.00kR184
1.00kR188
1.00kR191
X1_SUSPENDX1_DONE
X1_PROG_B
Red
2 1
D6
3P3V
1.00kR196 X1_INIT
X1_SUSPEND
X1_DONE
X1_PROG_B
X1_INIT
3P3V
33
R180
GND
0.1µF
C86
GND
33
R179
BCLK
BCLK
X1_VS0
X1_VS1
X1_VS2
X1_VS0X1_VS1
X1_VS2
3P3V1.00kR214
1.00kR2161.00kR218
1.00kR217GND
DNP33 MHz READ CLOCK
1.00kR185
X1_M0X1_M1
X1_M2
X1_M0X1_M1X1_M2
1.00kR181
1.00kR1821.00kR183
3P3V
GND
DNP
TDITCK
TDO
3P3V1.00kR201
1.00kR2021.00kR203
1.00kR187
1.00kR211 TMS
BBB_ADC_SDI
BBB_ADC_CSnBBB_ADC_SCLK
BBB_ADC_RESETn
BBB_GPIO8
BBB_GPIO9BBB_GPIO10
BBB_GPIO11
BBB_GPIO16
BBB_GPIO44
BBB_SYS_RESETN
GND
1nF
C166
1nF
C167
1nF
C168
1nF
C169
47nF
C172
47nF
C173
47nF
C174
47nF
C175
10µF
C170
10µF
C171
1P2V
1nF
C156
1nF
C157
1nF
C158
1nF
C159
47nF
C162
47nF
C163
47nF
C164
47nF
C165
10µF
C160
10µF
C161
3P3V
1nF
C176
1nF
C177
1nF
C178
1nF
C179
47nF
C188
47nF
C189
47nF
C190
47nF
C191
10µF
C184
10µF
C185
1P8V
1nF
C198
1nF
C199
1nF
C200
1nF
C201
47nF
C210
47nF
C211
47nF
C212
47nF
C213
10µF
C206
10µF
C207
3P3V
1nF
C180
1nF
C181
1nF
C182
1nF
C183
47nF
C193
47nF
C194
47nF
C195
47nF
C196
10µF
C186
10µF
C187
3P3V
1nF
C202
1nF
C203
1nF
C204
1nF
C205
47nF
C215
47nF
C216
47nF
C217
47nF
C218
10µF
C208
10µF
C209
3P3V
VCCAUX
VCCINT
VCCO_0
VCCO_2
VCCO_1
VCCO_3
11
TP49
EVM2_ADC_SDO0
EVM2_ADC_SDO3
EVM2_ADC_SDO2
EVM2_ADC_SDO1
EVM2_ADC_CSn
11
TP33
11
TP34
EVM2_ADC_CONVST
EVM2_ADC_RVS
EVM2_ADC_SCLKEVM2_ADC_SDI
EVM2_ADC_RESETn
BBB_GPIO23
CONVST
SDO0
SDO1
SDO2
SDO3
SCLK
RVS
SRESETn
BBB_ADC_SDO0
BBB_ADC_SDO1
BBB_ADC_SDO2BBB_ADC_SDO3
BBB_GPO1
GND
GND
GND
GND GND
GND
SDI
CSn
BBB_GPIO27
BBB_GPIO26BBB_GPIO25
BBB_GPIO24
BBB_GPIO7BBB_GPIO6
BBB_GPIO22
BBB_GPIO5BBB_GPIO21
BBB_GPIO4BBB_GPIO20
BBB_GPO0
BBB_GPIO19
BBB_GPIO3
BBB_GPIO2
BBB_GPIO18
BBB_GPIO1
BBB_GPIO17
BBB_GPIO0
BBB_GPIO32
BBB_GPIO35
BBB_GPIO47
BBB_GPIO36
BBB_GPIO48
BBB_GPIO37
BBB_GPIO49BBB_GPIO38
BBB_GPIO50BBB_GPIO39
BBB_GPIO54BBB_GPIO40
BBB_GPI0
BBB_GPIO42BBB_GPIO52
BBB_GPIO43
BBB_GPIO53
BBB_ADC_RVS
BBB_GPIO12BBB_GPIO29
BBB_GPIO13
BBB_GPIO30
BBB_GPIO14
BBB_GPIO31
BBB_GPIO28
BBB_GPIO15
NISO_SDA
NISO_SCL
Red
21
D22
330R209
Red
21
D23
330R264
Red
21
D24
330R265
Red
21
D25
330R266
3P3V 3P3V 3P3V 3P3V
VCC4
E/D1
GND2
OUT3
125 MHz
Y2
ADC_CONVST_FPGA
FSTS0_LEDFSTS1_LEDFSTS3_LEDFSTS2_LED
BBB_GPIO33BBB_GPIO45BBB_GPIO46BBB_GPIO34
BBB_GPIO33
BBB_GPIO45BBB_GPIO46
BBB_GPIO34
Copyright © 2016, Texas Instruments Incorporated
www.ti.com Design Files
33TIDUB85A–April 2016–Revised May 2016Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Figure 26. FPGA 2—Non-Isolated End Schematic
TP5
0.1µF
C16
TP4
10µF
C15
1µF
C13
0.1µF
C14
1P2V5VDC TP10
0.1µF
C30
TP9
10µF
C29
IN1
GN
D2
EN3
NC
4O
UT
5U6
TPS70918DBVT
1µF
C27
0.1µF
C28
1P8V_15VDC
GNDGND
OUT1
NC2
SENSE3
6P4V24
6P4V15
3P2V6
GND7
1P6V8
0P8V9
0P4V10
0P2V11
0P1V12
EN13
NR14
IN15
IN16
NC17
NC18
NC19
OUT20
PAD21
U13
TPS7A4700RGWR
47µF
C45
1000pF
C46
5VDC
0R77DNP
0R78DNP
0R79DNP
0R800R81
DNP0R82
DNP0R830R84
0.1R76
47µFC47
1µFC48
3P3V
GND
GND GND
TP17
GND
GND
TP13
0.1µF
C34
TP11
10µF
C33
1µF
C31
0.1µF
C32
A1P8V_ISOLDO_IN_ISO
TP8
0.1µF
C22
TP7
10µF
C21
IN1
GN
D2
EN3
NC
4O
UT
5
U4
TPS70912DBVT
1µF
C19
0.1µF
C20
1P2V_ISOLDO_IN_ISO
AGND_ISO
AGND_ISO
TP14
0.1µF
C38
TP12
10µF
C37
1µF
C35
0.1µF
C36
1P8V_ISO1LDO_IN_ISO
AGND_ISO
47µF
C17
1000pF
C18
AGND_ISO
LDO_IN_ISO
0R64DNP
0R65DNP
0R66DNP
0R670R68
DNP0R69
DNP0R700R71
0.1R63
47µFC23
1µFC24
3P3V_ISOTP6
AGND_ISO AGND_ISO
AGND_ISOAGND_ISO
Red
21
D16
3
1
2
Q2CMPT3904 LEAD FREE
GND
1P2V
3P3V
1.2kR235
330
R237
Red
21
D18
3
1
2
Q4CMPT3904 LEAD FREE
GND
1P8V
3P3V
1.2kR239
330
R241
Red
21
D15
3
1
2
Q1CMPT3904 LEAD FREE
1.2kR233
330
R234
Red
21
D17
3
1
2
Q3CMPT3904 LEAD FREE
1.2kR236
330
R238
Red
21
D19
3
1
2
Q5CMPT3904 LEAD FREE
1.2kR240
330
R242
Red
21
D14
3P3V
1.2kR232
GND
Red
21
D13
3P3V_ISO
1.2kR231
1P2V_ISO1P8V_ISOA1P8V_ISO
AGND_ISOAGND_ISOAGND_ISO
3P3V_ISO 3P3V_ISO3P3V_ISO
AGND_ISO
5V_ISO
5V_ISO1
1P8V_ISO
EVM1_DVDD 1P8V_ISO1
EVM1_REG_5V5
1P8V
1 2 3
J17HTSW-103-07-G-S
EVM2_DVDD 1P8V_1
NON-ISOLATED POWER RAIL ISOLATED POWER RAIL
IN1
GN
D2
EN3
NC
4O
UT
5
U8
TPS70918DBVT
IN1
GN
D2
EN3
NC
4O
UT
5
U10
TPS70918DBVT
IN1
GN
D2
EN3
NC
4O
UT
5
U11
TPS70912DBVT
OUT1
NC2
SENSE3
6P4V24
6P4V15
3P2V6
GND7
1P6V8
0P8V9
0P4V10
0P2V11
0P1V12
EN13
NR14
IN15
IN16
NC17
NC18
NC19
OUT20
PAD21
U7
TPS7A4700RGWR
1 2 3
J1261300311121
1 2 3
J1361300311121
Pin 2,3 Short(default)
Pin 2,3 Short(default)
Pin 2,3 Short(default)
Copyright © 2016, Texas Instruments Incorporated
Design Files www.ti.com
34 TIDUB85A–April 2016–Revised May 2016Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Figure 27. Isolated and Non-Isolated LDOs Schematic
3
4
1
62
V+
V-
5
U26TLV3012AIDCKR
3
4
1
62
V+
V-
5
U29TLV3012AIDCKR
2
4
1
53
U27SN74LVC1G08DCKR
LDO_EN1
0.1µF
C133
0.1µF
C128
0.1µF
C155
EVM1_ID_PWR
EVM1_ID_PWR
EVM1_1.25V_1
EVM1_1.25V_1
EVM1_1.25V_2
EVM1_1.25V_2
EVM1_ID_PWR
10.0kR249
10.0k
R252
32.4k
R248
25.5kR253
0.1µFC150
0.01µFC221
EVM1_DVDD
1
23
Q6NX3020NAKW,115
APT2012LZGCK
Gre
en
12
D20
10.0kR247
10.0kR250
1.8V
5.5V
1.3V
1.3V
3
4
1
62
V+
V-
5
U30TLV3012AIDCKR
3
4
1
62
V+
V-
5
U32TLV3012AIDCKR
2
4
1
53
U31SN74LVC1G08DCKR
LDO_EN2
0.1µF
C224
0.1µF
C223
0.1µF
C226
EVM2_ID_PWR
EVM2_ID_PWR
EVM2_1.25V_1
EVM2_1.25V_1
EVM1_2.25V_2
EVM2_1.25V_2
EVM2_ID_PWR
10.0kR256
10.0k
R258
32.4k
R255
25.5kR259
0.1µFC225
0.01µFC227
EVM2_DVDD
1
23
Q7NX3020NAKW,115
GND
APT2012LZGCK
Gre
en
12
D21
5VDC
5VDC
10.0kR254
10.0kR257
1.8V
5.5V
1.3V
1.3V
AGND_ISO AGND_ISO
AGND_ISO
AGND_ISO
AGND_ISO AGND_ISO
AGND_ISO AGND_ISO
AGND_ISO
AGND_ISO
AGND_ISO
PHI BOARD-1 POWER SENSING
PHI BOARD-2 POWER SENSING
LDO_IN_ISO
LDO_IN_ISO
GND
GND
GND
GND
GND GNDGND
GNDGND
GND
AGND_ISO
GND
Copyright © 2016, Texas Instruments Incorporated
www.ti.com Design Files
35TIDUB85A–April 2016–Revised May 2016Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Figure 28. Power Sense—PH1 and PH2 Interface Schematic
REF6045_BUF 0R48DNP
0R49
22µFC57
22µFC58
AGND_ISO
REFBUF
3
1
2
4
6
5
V+
V-
U15OPA625IDBVR1.00k
R85
1µFC53
0.1µFC55
0.1µFC60
0.1µFC54
2.49k
R86
4.99kR88
1
2
3
4
5
U14OPA378AIDBVT
AGND_ISO
AGND_ISO
5V_ISO
AGND_ISO
AGND_ISO
0.22µFC52
AGND_ISO
4.75R89
499
R92
5V_ISO
AGND_ISO
AGND_ISO
1.00k
R91
AGND_ISO
10pF
C61
10µF
C49
30.0k
R94
D4CUS05S40,H3F
5V_ISO
0.22R46
10µFC88
1µFC197
0.22R47
47µFC1
VIN1
EN2
FILT3
SS4
OUT_S5
OUT_F6
GND_F7
GND_S8
U34
REF6041AIDGK
5V_ISO
AGND_ISO
AGND_ISO AGND_ISO
AGND_ISO
REF5045_BUF
OE1
ADD2
GND3
SCL8
OUTP4
OUTN5
VDD6
SDA7
U36
LMK61E2-SIAR
3P3V_ISO
AGND_ISO
0.1µF
C232
10µF
C233
AGND_ISO
4.7kR270
4.7kR271
GND1
A2
B3
NC4
VCC5
NC6
GND7
R8
NC9
VDD10
U37
SN65LVDS4RSET
0.1µF
C234
0.1µF
C235
100R274
1P8V_ISO
BCLK_N
BCLK_P
MCLK33
R273
3P3V_ISO
AGND_ISO
BCLK_ISO33
R269
ISO_SDA
ISO_SCL
20.0k
R111
20.0kR114
280k
R109
10.0kR112
1
2
J11
87898-0204
12
J10
87898-0204
AGND_ISO
1µFC80
AGND_ISO
1
2
3
4
5
U23OPA376AIDBVR
1µF
C7420.0k
R106
499
R110
5V_ISO
0.1µF
C77
AGND_ISO
AGND_ISOOPA625_CM
REFOUT
REFBUF
OPA625_CM
VIN2
TEMP3
GND4
TRIM/NR5
VOUT6
U22A
REF5045AIDGKT1µFC79
10µFC81
0.22R113
5V_ISO
AGND_ISO
AGND_ISO
AGND_ISO
0.1R268
0.1R276
4.7kR267
3P3V_ISO
0.1µFC59
0.1µFC231
1P8V_ISO 3P3V_ISO
AGND_ISO AGND_ISO
4.7kR277
REF5045
REF6041
COMMON MODE REFERENCE GENERATION
PROG MASTER CLOCK GENERATION
REFOUT
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Figure 29. ADC Reference Selection Schematic
white space
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
9.2 Bill of MaterialsTo download the bill of materials (BOM), see the design files at TIDA-00732.
Table 12. BOM
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION PACKAGEREFERENCE
1 !PCB1 1 TIDA-00732 Any Printed Circuit Board
2 C1 1 47uF GRM32ER71A476KE15L MuRata CAP, CERM, 47 µF, 10 V, +/-10%, X7R, 1210 1210
3C2, C10, C24, C48, C53, C56,C62, C63, C65, C70, C74, C79,C80
13 1uF GRM188R71E105KA12D MuRata CAP, CERM, 1 µF, 25 V, +/-10%, X7R, 0603 0603
4
C3, C11, C12, C25, C26, C43,C44, C51, C59, C75, C78, C85,C86, C128, C133, C150, C155,C192, C220, C222, C223,C224, C225, C226, C229,C230, C231
27 0.1uF GRM155R71C104KA88D MuRata CAP, CERM, 0.1 µF, 16 V, +/-10%, X7R, 0402 0402
5 C4, C64, C76, C81, C82, C83,C84, C87, C89, C90 10 10uF GRM21BR71A106KE51L MuRata CAP, CERM, 10 µF, 10 V, +/-
10%, X7R, 0805 0805
6 C5, C9, C17, C23, C45, C47 6 47uF C3216X5R1E476M160AC TDK CAP, CERM, 47 µF, 25 V, +/-20%, X5R, 1206_190 1206_190
7 C6, C8 2 10uF C3216X7R1E106M160AE TDK CAP, CERM, 10 µF, 25 V, +/-20%, X7R, 1206_190 1206_190
8 C7, C18, C46, C67, C73 5 1000pF GRM1885C1H102FA01J MuRata CAP, CERM, 1000 pF, 50 V,+/- 1%, C0G/NP0, 0603 0603
9 C13, C19, C27, C31, C35 5 1uF 08055C105KAT2A AVX CAP, CERM, 1uF, 50V, +/-10%, X7R, 0805 0805
10 C14, C16, C20, C22, C28, C30,C32, C34, C36, C38 10 0.1uF C0603C104K5RACTU Kemet CAP, CERM, 0.1uF, 50V, +/-
10%, X7R, 0603 0603
11 C15, C21, C29, C33, C37 5 10uF 0805YD106MAT2A AVX CAP, CERM, 10uF, 16V, +/-20%, X5R, 0805 0805
12 C39, C40 2 10uF UMK325AB7106KM-T Taiyo Yuden CAP, CERM, 10 µF, 50 V, +/-10%, X7R, 1210 1210
13 C41 1 0.01uF C0603C103J5RACTU Kemet CAP, CERM, 0.01uF, 50V, +/-5%, X7R, 0603 0603
14 C42 1 0.022uF 08055C223KAT2A AVX CAP, CERM, 0.022uF, 50V,+/-10%, X7R, 0805 0805
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Table 12. BOM (continued)
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION PACKAGEREFERENCE
15
C49, C96, C97, C106, C107,C120, C121, C122, C123,C142, C143, C144, C145,C160, C161, C170, C171,C184, C185, C186, C187,C206, C207, C208, C209,C219, C228, C233
28 10uF ZRB18AD71A106KE01L MuRata CAP, CERM, 10 µF, 10 V, +/-10%, X7T, 0603 0603
16 C50 1 0.1uF 0603YC104JAT2A AVX CAP, CERM, 0.1 µF, 16 V, +/-5%, X7R, 0603 0603
17 C52 1 0.22uF 0805YC224JAT2A AVX CAP, CERM, 0.22 µF, 16 V,+/- 5%, X7R, 0805 0805
18 C54, C55, C60, C77, C232 5 0.1uF C0603C104J3RACTU Kemet CAP, CERM, 0.1 µF, 25 V, +/-5%, X7R, 0603 0603
19 C57, C58 2 22uF GRM188R60J226MEA0J MuRata CAP, CERM, 22 µF, 6.3 V, +/-20%, X5R, 0603 0603
20 C61 1 10pF C0603C100F5GAC7867 Kemet CAP, CERM, 10 pF, 50 V, +/-1%, C0G/NP0, 0603 0603
21 C66, C71, C221, C227 4 0.01uF GRM155R71H103KA88D MuRata CAP, CERM, 0.01 µF, 50 V,+/- 10%, X7R, 0402 0402
22 C68 1 0.01uF C0805C103F1GACTU Kemet CAP, CERM, 0.01 µF, 100 V,+/- 1%, C0G/NP0, 0805 0805
23 C88 1 10uF GRM21BR71A106KE51L MuRata CAP, CERM, 10uF, 10V, +/-10%, X7R, 0805 0805
24 C91 1 22uF C3225X5R1A226M TDK CAP, CERM, 22uF, 10V, +/-20%, X5R, 1210 1210
25
C92, C93, C94, C95, C102,C103, C104, C105, C112,C113, C114, C115, C116,C117, C118, C119, C134,C135, C136, C137, C138,C139, C140, C141, C156,C157, C158, C159, C166,C167, C168, C169, C176,C177, C178, C179, C180,C181, C182, C183, C198,C199, C200, C201, C202,C203, C204, C205
48 1000pF C1005X7R1H102M TDK CAP, CERM, 1000 pF, 50 V,+/- 20%, X7R, 0402 0402
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Table 12. BOM (continued)
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION PACKAGEREFERENCE
26
C98, C99, C100, C101, C108,C109, C110, C111, C124,C125, C126, C127, C129,C130, C131, C132, C146,C147, C148, C149, C151,C152, C153, C154, C162,C163, C164, C165, C172,C173, C174, C175, C188,C189, C190, C191, C193,C194, C195, C196, C210,C211, C212, C213, C215,C216, C217, C218
48 0.047uF GRM155R61A473KA01D MuRata CAP, CERM, 0.047 µF, 10 V,+/- 10%, X5R, 0402 0402
27 C197 1 1uF GRM188R71A105KA61D MuRata CAP, CERM, 1uF, 10V, +/-10%, X7R, 0603 0603
28 C234, C235 2 0.1uF GRM155R61E104KA87D MuRata CAP, CERM, 0.1 µF, 25 V, +/-10%, X5R, 0402 0402
29 C236 1 1000pF 202R18W102KV4E Johanson Technology CAP, CERM, 1000 pF, 2000V, +/- 10%, X7R, 1206_190 1206_190
30 C237 1 100uF 293D107X9020E2TE3 Vishay-Sprague CAP, TA, 100 µF, 20 V, +/-10%, 0.5 ohm, SMD 7343-43
31 D1, D3 2 20V MBR0520LT1G ON Semiconductor Diode, Schottky, 20 V, 0.5 A,SOD-123 SOD-123
32 D2 1 200V MBRS4201T3G ON Semiconductor Diode, Schottky, 200V, 4A,SMC SMC
33 D4 1 40V CUS05S40,H3F Toshiba Diode, Schottky, 40 V, 0.5 A,SOD-323 SOD-323
34D5, D6, D7, D8, D9, D10, D11,D12, D13, D14, D15, D16, D17,D18, D19, D22, D23, D24, D25
19 Red 150060RS75000 Wurth Elektronik LED, Red, SMD LED_0603
35 D20, D21 2 Green APT2012LZGCK Kingbright LED, Green, SMD LED_0805
36 FID4, FID5, FID6, FID7, FID8 5 N/A N/A Fiducial mark. There isnothing to buy or mount. Fiducial
37H1, H2, H3, H4, H17, H18, H21,H22, H23, H24, H25, H26, H27,H28, H29
15 PMSSS 440 0025 PH B&F Fastener Supply MACHINE SCREW PANPHILLIPS 4-40
Machine Screw, 4-40, 1/4"
38 H5, H6, H7, H8, H13, H14, H15,H16 8 9774050360R Wurth Elektronik ROUND STANDOFF M3
STEEL 11MMROUND STANDOFF
M3 STEEL 11MM
39 H9, H10, H11, H12, H19, H20,H30 7 1902C Keystone Standoff, Hex, 0.5"L #4-40
Nylon Standoff
40 J1, J2 2 TSW-123-07-G-D Samtec Header, 2.54 mm, 23x2, Gold,TH
Header, 2.54 mm,23x2, TH
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Table 12. BOM (continued)
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION PACKAGEREFERENCE
41 J3, J18 2 QTH-030-03-L-D-A Samtec Header(Shrouded), 19.7mil,30x2, Gold, SMT
Header (Shrouded),19.7mil, 30x2, SMT
42 J4, J21, J25 3 61300211121 Wurth Elektronik eiSos Header, 2.54 mm, 2x1, Gold,TH
Header, 2.54mm,2x1, TH
43 J5 1 ED120/2DS On-Shore Technology TERMINAL BLOCK 5.08MMVERT 2POS, TH
TERM_BLK, 2pos,5.08mm
44 J6, J9 2 TSM-103-01-L-SV Samtec Header, 100mil, 3x1, Gold,SMT
Samtec_TSM-103-01-X-SV
45 J7, J8 2 142-0701-801 Johnson Connector, End launch SMA,50 ohm, SMT End Launch SMA
46 J10, J11 2 87898-0204 Molex Header, 2.54 mm, 2x1, Gold,R/A, SMT
Header, 2.54 mm,2x1, R/A, SMT
47 J12, J13 2 61300311121 Wurth Elektronik eiSos Header, 2.54 mm, 3x1, Gold,TH
Header, 2.54mm,3x1, TH
48 J14, J19 2 PEC06SAAN Sullins ConnectorSolutions Header, 100mil, 6x1, Tin, TH
TH, 6-Leads, Body608x100mil, Pitch
100mil
49 J16, J17, J22 3 HTSW-103-07-G-S Samtec Header, 100mil, 3x1, Gold, TH Header, 100mil, 3x1,TH
50 L1 1 600 ohm HZ0805E601R-10 Laird-Signal IntegrityProducts
Ferrite Bead, 600 ohm @ 100MHz, 0.5 A, 0805 0805
51 L2 1 600 ohm MPZ2012S601A TDK Ferrite Bead, 600 ohm @100MHz, 2A, 0805 0805
52 LBL1 1 THT-14-423-10 BradyThermal Transfer PrintableLabels, 0.650" W x 0.200" H -10,000 per roll
PCB Label 0.650"Hx 0.200"W
53 Q1, Q2, Q3, Q4, Q5 5 40 V CMPT3904 LEAD FREE Central Semiconductor Transistor, NPN, 40 V, 0.2 A,SOT-23 SOT-23
54 Q6, Q7 2 30V NX3020NAKW,115 NXP Semiconductor MOSFET, N-CH, 30 V, 0.18A, SOT-323 SOT-323
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Table 12. BOM (continued)
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION PACKAGEREFERENCE
55
R1, R2, R3, R4, R5, R6, R7,R8, R9, R10, R11, R12, R13,R14, R15, R16, R17, R18, R19,R20, R21, R22, R23, R24, R25,R26, R27, R28, R29, R30, R31,R32, R33, R34, R35, R36, R37,R38, R39, R40, R41, R42, R43,R44, R123, R124, R125, R126,R127, R128, R129, R130,R131, R132, R133, R134,R135, R136, R137, R138,R139, R140, R141, R142,R143, R144, R145, R146,R147, R148, R149, R150,R151, R152
74 10.0 CRCW040210R0FKED Vishay-Dale RES, 10.0, 1%, 0.063 W,0402 0402
56 R46, R47 2 0.22 ERJ-3RQFR22V Panasonic RES, 0.22 ohm, 1%, 0.1W,0603 0603
57 R49, R97, R103 3 0 ERJ-3GEY0R00V Panasonic RES, 0, 5%, 0.1 W, 0603 0603
58 R50, R204, R205, R206 4 1.5k CRCW08051K50JNEA Vishay-Dale RES, 1.5 k, 5%, 0.125 W,0805 0805
59 R51 1 0 CRCW12060000Z0EA Vishay-Dale RES, 0, 5%, 0.25 W, 1206 120660 R52, R63, R76 3 0.1 ERJ-3RSFR10V Panasonic RES, 0.1, 1%, 0.1 W, 0603 0603
61
R55, R58, R67, R70, R71, R80,R83, R84, R160, R162, R163,R164, R166, R169, R170,R171, R172, R173, R175,R186, R189, R190, R193,R195, R199, R200, R208,R210, R212, R213, R215
31 0 ERJ-2GE0R00X Panasonic RES, 0, 5%, 0.063 W, 0402 0402
62R61, R62, R72, R73, R74, R75,R90, R93, R247, R250, R254,R257
12 10.0k ERJ-2RKF1002X Panasonic RES, 10.0 k, 1%, 0.1 W, 0402 0402
63 R85, R91, R98, R99, R104,R105 6 1.00k RG1608P-102-B-T5 Susumu Co Ltd RES, 1.00 k, 0.1%, 0.1 W,
0603 0603
64 R86 1 2.49k RG1608P-2491-B-T5 Susumu Co Ltd RES, 2.49 k, 0.1%, 0.1 W,0603 0603
65 R87 1 100k CRCW0402100KFKED Vishay-Dale RES, 100 k, 1%, 0.063 W,0402 0402
66 R88 1 4.99k RG1608P-4991-B-T5 Susumu Co Ltd RES, 4.99 k, 0.1%, 0.1 W,0603 0603
67 R89 1 4.75 CRCW06034R75FKEA Vishay-Dale RES, 4.75, 1%, 0.1 W, 0603 060368 R92, R110 2 499 RG1608P-4990-B-T5 Susumu Co Ltd RES, 499, 0.1%, 0.1 W, 0603 0603
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Table 12. BOM (continued)
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION PACKAGEREFERENCE
69 R94 1 30.0k RG1608P-303-B-T5 Susumu Co Ltd RES, 30.0 k, 0.1%, 0.1 W,0603 0603
70 R95, R101 2 2.21 CRCW06032R21FKEA Vishay-Dale RES, 2.21, 1%, 0.1 W, 0603 0603
71 R96, R108, R115, R116, R117,R118, R192, R194, R197, R198 10 100 RG1608P-101-B-T5 Susumu Co Ltd RES, 100, 0.1%, 0.1 W, 0603 0603
72 R106, R111, R114 3 20.0k RG1608P-203-B-T5 Susumu Co Ltd RES, 20.0 k, 0.1%, 0.1 W,0603 0603
73
R107, R119, R120, R121,R122, R153, R154, R155,R156, R157, R158, R159,R165, R168, R174, R176,R177, R178, R181, R182,R183, R184, R185, R187,R188, R191, R196, R201,R202, R203, R211, R214,R216, R217, R218, R243
36 1.00k RC0603FR-071KL Yageo America RES, 1.00 k, 1%, 0.1 W, 0603 0603
74 R109 1 280k RG2012P-2803-B-T5 Susumu Co Ltd RES, 280 k, 0.1%, 0.125 W,0805 0805
75 R112, R249, R252, R256, R258 5 10.0k RG1608P-103-B-T5 Susumu Co Ltd RES, 10.0 k, 0.1%, 0.1 W,0603 0603
76 R113 1 0.22 ERJ-3RQFR22V Panasonic RES, 0.22, 1%, 0.1 W, 0603 0603
77 R161, R167, R179, R180,R269, R273 6 33 CRCW040233R0JNED Vishay-Dale RES, 33, 5%, 0.063 W, 0402 0402
78 R207, R260 2 33.0 RC0603FR-0733RL Yageo America RES, 33.0, 1%, 0.1 W, 0603 0603
79R209, R227, R228, R229,R230, R234, R237, R238,R241, R242, R264, R265, R266
13 330 RC0603JR-07330RL Yageo America RES, 330, 5%, 0.1 W, 0603 0603
80 R219 1 118k RT0805BRD07118KL Yageo America RES, 118k ohm, 0.1%,0.125W, 0805 0805
81 R220 1 5.62k RT0805BRD075K62L Yageo America RES, 5.62 k, 0.1%, 0.125 W,0805 0805
82 R221 1 249k CRCW0805249KFKEA Vishay-Dale RES, 249k ohm, 1%, 0.125W,0805 0805
83 R222, R226, R231, R232,R233, R235, R236, R239, R240 9 1.2k CRCW06031K20JNEA Vishay-Dale RES, 1.2 k, 5%, 0.1 W, 0603 0603
84 R223 1 1.07k RT0805BRD071K07L Yageo America RES, 1.07 k, 0.1%, 0.125 W,0805 0805
85 R224 1 20.5k CRCW080520K5FKEA Vishay-Dale RES, 20.5 k, 1%, 0.125 W,0805 0805
86 R225 1 0.01 WSL0805R0100FEA18 Vishay-Dale RES, 0.01, 1%, 0.25 W, 0805 0805
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Table 12. BOM (continued)
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION PACKAGEREFERENCE
87 R244 1 511 RC0603FR-07511RL Yageo America RES, 511, 1%, 0.1 W, 0603 060388 R246, R251 2 10.0k CRCW060310K0FKEA Vishay-Dale RES, 10.0 k, 1%, 0.1 W, 0603 0603
89 R248, R255 2 32.4k RG1608P-3242-B-T5 Susumu Co Ltd RES, 32.4 k, 0.1%, 0.1 W,0603 0603
90 R253, R259 2 25.5k RG1608P-2552-B-T5 Susumu Co Ltd RES, 25.5 k, 0.1%, 0.1 W,0603 0603
91 R261 1 0 CRCW04020000Z0ED Vishay-Dale RES, 0, 5%, 0.063 W, 0402 0402
92 R267, R270, R271, R277 4 4.7k CRCW04024K70JNED Vishay-Dale RES, 4.7 k, 5%, 0.063 W,0402 0402
93 R268, R276 2 0.1 ERJ-2BSFR10X Panasonic RES, 0.1, 1%, 0.125 W, 0402 040294 R274 1 100 CRCW0402100RJNED Vishay-Dale RES, 100, 5%, 0.063 W, 0402 0402
95 S1 1 EVQPNF04M Panasonic Switch, Tactile, SPST-NO,0.05A, 12V, SMD
SMD, 2-Leads, Body6x4mm
96 T1 1 110uH 750315240 Wurth Elektronik Transformer, 110 uH, SMT 10.41x12.32mm
97TP1, TP2, TP4, TP5, TP6, TP7,TP8, TP9, TP10, TP11, TP12,TP13, TP14, TP17
14 STD STD STD Test Point 40mil pad 20mildrill
98
TP3, TP16, TP26, TP27, TP28,TP29, TP32, TP35, TP36,TP37, TP38, TP39, TP40,TP41, TP42, TP43, TP44,TP45, TP46, TP47
20 SMT 5016 Keystone Test Point, Compact, SMT Testpoint_Keystone_Compact
99
TP15, TP18, TP19, TP20,TP21, TP22, TP23, TP24,TP25, TP30, TP31, TP33,TP34, TP48, TP49, TP50, TP51
17 STD STD STD Test Point, O.025"
100 U1 1 SN6505ADBVR Texas Instruments
LOW-NOISE 1ATRANSFORMER DRIVERSFOR ISOLATED POWERSUPPLIES, DBV0006A
DBV0006A
101 U2, U7, U13 3 TPS7A4700RGWR Texas Instruments36-V, 1-A, 4.17-µVRMS, RFLDO Voltage Regulator,RGW0020A
RGW0020A
102 U3 1 LMZ14203TZ-ADJ/NOPB Texas Instruments
3A SIMPLE SWITCHER®Power Module with 42VMaximum Input Voltage, 7-pinTO-PMOD, Pb-Free
TZA07A
103 U4, U11 2 TPS70912DBVT Texas Instruments IC REG LDO 1.2V 0.15ASOT23-5 DBV0005A
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Table 12. BOM (continued)
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION PACKAGEREFERENCE
104 U5, U12 2 ISO7840DWR Texas InstrumentsHigh-Performance, 8000 VPKReinforced Quad-ChannelDigital Isolator, DW0016B
DW0016B
105 U6, U8, U10 3 TPS70918DBVT Texas Instruments IC REG LDO 1.8V 0.15ASOT23-5 DBV0005A
106 U9 1 ISO7842DWR Texas InstrumentsHigh-Performance, 8000 VPKReinforced Quad ChannelDigital Isolator, DW0016B
DW0016B
107 U14 1 OPA378AIDBVT Texas Instruments
Low-Noise, 900 kHz, RRIO,Precision OperationalAmplifier, Zerø-Drift Series,2.2 to 5.5 V, -40 to 125 degC,5-pin SOT23 (DBV0005A),Green (RoHS & no Sb/Br)
DBV0005A
108 U15, U18, U20 3 OPA625IDBVR Texas Instruments
High-Bandwidth, High-Precision, Low THD+N, 16-Bitand 18-Bit Analog-to-DigitalConverter (ADC) Drivers,DBV0006A
DBV0006A
109 U16 1 SN74LVC1G17DCKR Texas Instruments SINGLE SCHMITT-TRIGGERBUFFER, DCK0005A DCK0005A
110 U17, U27, U31 3 SN74LVC1G08DCKR Texas Instruments Single 2-Input Positive-ANDGate, DCK0005A DCK0005A
111 U19 1 ADS9110IRGER Texas Instruments18-Bit, 2-MSPS, 20-mW, SARADC with Enhanced SerialInterface, RGE0024H
RGE0024H
112 U21, U28 2 BR24G32FVT-3AGE2 Rohm I2C BUS EEPROM (2-Wire),TSSOP-B8 TSSOP-8
113 U22 1 REF5045AIDGKT Texas Instruments
Low Noise, Very Low Drift,Precision Voltage Reference, -40 to 125 degC, 8-pin MSOP(DGK), Green (RoHS & noSb/Br)
DGK0008A
114 U23 1 OPA376AIDBVR Texas Instruments
Precision, Low Noise, Low IqOperational Amplifier, 2.2 to5.5 V, -40 to 125 degC, 5-pinSOT23 (DBV0005A), Green(RoHS & no Sb/Br)
DBV0005A
115 U24, U25 2
Spartan-3AN Non-VolatileFPGA, 108 User I/Os, 144-PinTQFP, Standard Performance,Commercial Grade
TQ144
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNRand Sampling Rate
Table 12. BOM (continued)
ITEM DESIGNATOR QTY VALUE PARTNUMBER MANUFACTURER DESCRIPTION PACKAGEREFERENCE
116 U26, U29, U30, U32 4 TLV3012AIDCKR Texas InstrumentsNanopower, 1.8V, Comparatorwith Voltage Reference,DCK0006A
DCK0006A
117 U33 1 SN74AUP1G80DCK SN74AUP1G80DCK TI IC, Single Positive-Edge-
Triggered D-Type Flip-Flop SC-70
118 U34 1 REF6041AIDGK Texas Instruments
High-Precision VoltageReference with IntegratedHigh-Bandwidth Buffer,DGK0008A
DGK0008A
119 U35 1 ISO1541DR Texas Instruments Low-Power Bidirectional I2CIsolators, D0008A D0008A
120 U36 1 LMK61E2-SIAR Texas InstrumentsUltra-Low Jitter ProgrammableOscillator with InternalEEPROM, SIA0008B
SIA0008B
121 U37 1 SN65LVDS4RSET Texas Instruments
500 Mbps High-SpeedDifferential Line Driver /Receivers with LVDS Inputand LVTTL / LVCMOSOutput, 1 Rx, -40 to +85degC, 10-pin UQFN (RSE),Green (RoHS & no Sb/Br)
RSE0010A
122 Y1, Y2 2 ASTMLPE-125.000MHZ-LJ-E-T ABRACON OSC, 125 MHz, 3.3V, SMD 3.2x2.5mm
123 C69 0 10uF GRM21BR71A106KE51L MuRata CAP, CERM, 10 µF, 10 V, +/-10%, X7R, 0805 0805
124 C72 0 1uF GRM188R71E105KA12D MuRata CAP, CERM, 1 µF, 25 V, +/-10%, X7R, 0603 0603
125 C214 0 0.01uF GRM155R71H103KA88D MuRata CAP, CERM, 0.01 µF, 50 V,+/- 10%, X7R, 0402 0402
126 FID1, FID2, FID3 0 N/A N/A Fiducial mark. There isnothing to buy or mount. Fiducial
127 J24 0 HTSW-103-07-G-S Samtec Header, 100mil, 3x1, Gold, TH Header, 100mil, 3x1,TH
128 R45 0 0 CRCW04020000Z0ED Vishay-Dale RES, 0, 5%, 0.063 W, 0402 0402129 R48 0 0 ERJ-3GEY0R00V Panasonic RES, 0, 5%, 0.1 W, 0603 0603
130R53, R54, R56, R57, R59, R60,R64, R65, R66, R68, R69, R77,R78, R79, R81, R82, R102
0 0 ERJ-2GE0R00X Panasonic RES, 0, 5%, 0.063 W, 0402 0402
131 R100 0 10.0k ERJ-2RKF1002X Panasonic RES, 10.0 k, 1%, 0.1 W, 0402 0402
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18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for MaximumSNR and Sampling Rate
9.3 Layout PrintsTo download the layer plots, see the design files at TIDA-00732.
9.4 Altium ProjectTo download the Altium project files, see the design files at TIDA-00732.
9.5 Layout Guidelines
Figure 30. Board Layout Guidelines
9.6 Gerber FilesTo download the Gerber files, see the design files at TIDA-00732.
9.7 Assembly DrawingsTo download the assembly drawings, see the design files at TIDA-00732.
10 Software FilesTo download the software files, see the design files at TIDA-00732.
11 References
1. Texas Instruments, 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion andNoise, TIPD115 Design Guide (SLAU515)
12 About the AuthorANBU MANI is a Systems Engineer at Texas Instruments where he is responsible for developingreference design solutions for the industrial segment. Anbu has fifteen years of experience in analogcircuit design and digital circuit design for the Automatic Test Equipment in Modular platform. He is alsoengaged with the design and development of embedded products.
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Changes from Original (April 2016) to A Revision .......................................................................................................... Page
• Changed from preview page............................................................................................................. 1
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