1
Abstract & Main Goal
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
The focus of this project was the creation of an analyzing
device for a std. PCI-Express (1.0) communication line at
speeds of 2.5Gb/sec. by means of a VHDL core on a Xilinx
“Virtex II pro” FPGA platform.
The core implements Real Time Hardware based algorithms
and enables the user to monitor and analyze PCI-Express
transactions using a simple register based interface .
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Architecture Development
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
ISAParallel
PCIParallel
Signaling Rate [Ghz]
1980’s 1990’s 2000’s
~~1
5
10
15
Parallel Bus limit
PCI-Express3rd Generation I/O
Serial Protocol
3
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
Vs Classic PCI
Endpoint
LegacyEnd
point
Switch Switch
Switch
CPU
Root ComplexPCI Express
GFX
PCIBridge
PCI
LegacyEnd
point
Endpoint
Memory
Switched Fabric Arch
PCI-XDevice
PCI-X Device
CPU
Host BridgeAGPGFX
PCIBridge
PCI
PCI-XBridge
PCIBridge
PCI-XBridge
PCI-XDevice
PCI-X Device
Memory
BUS Arch
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PCI-Express - ArchitectureHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
CLK CLK
Dev
ice
A Device B
TX+TX-
RX+RX-
TX+TX-
RX-RX+
CLK CLK
Dev
ice
A Device B
TX+TX-
RX+RX-
TX+TX-
RX-RX+ Dual Simplex
Differential
2.5 Gbps/direction
Separate clock !
x1 Lane Wide Link
Switch OperationTraffic Direction
Device C
Device A
Switch
End Point
End Point
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PCI-Express - ProtocolHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
Split Transaction - Request/Complete
• Memory
• I/O
• Configuration
• Message
Transaction Layer
DataHeader
Transaction Layer
DataHeader
Data Link Layer
CRCSequenceNumber
Data Link Layer
CRCSequenceNumber
Physical Layer
FrameFrame
Physical Layer
FrameFrame
Transaction
Data Link
Physical
CompletionPacket
CRC SequenceNumber
Frame Frame
RequestPacket CRCSequence
NumberFrameFrame
Dev
ice
A Device B
CompletionPacket
CRC SequenceNumber
Frame FrameCompletion
PacketCRC Sequence
NumberFrame Frame
RequestPacket CRCSequence
NumberFrameFrame
RequestPacket CRCSequence
NumberFrameFrame
Dev
ice
A Device B
3 Layers
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R&D – Signal IntegritySystem Under Test Digital signal requirements :
• Complete and Unimpaired
• Accurate placement in time
• Stable, valid logic levels
• Clean, fast transitions
• Transient free
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
Analyzers offer a vital validation Tool !
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R&D – Data IntegritySystem Under Test Data Packets requirements :
• Complete & Unimpaired
• Protocol Compliant
• Valid structures
• Valid symbols
• Error free
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
Data Integrity is the main focus of this
project !
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Analyzers - Market Survey• Algorithms – Software manifested
• Offline filtering - Storage Limit
• Stand alone Tool
• No open source
• High Cost – 30,000 $
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
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Project Goals• Standard Hardware – Low Cost
• Low Storage Demand
• PCIe (1.0) Compliant
• Bit Level Filtering Control
• Simple User Friendly Interface
• Educational Merits – Lab Experiment
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
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Overcoming Technical Hardships• Real Time Algorithms
• High Speed Synchronization
• Data Masses Handling
• Decryption and Descrambling
• Extensive Spec Survey
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
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PCI-Express AnalyzerHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
A
Mother Board
Stub
Switch
B
Transaction Layer
DataHeader
Transaction Layer
DataHeader
Data Link Layer
CRCSequenceNumber
Data Link Layer
CRCSequenceNumber
Physical Layer
FrameFrame
Physical Layer
FrameFrame
PCI-Express Analyzer
FmtFmt
Address/RoutingAddress/Routing
TypeType Requestor IDRequestor ID RsrvRsrv Traffic ClassTraffic Class
LengthLength AttrAttr TagTag RsrvRsrv Byte EnablesByte Enables
• Line Sniffing
• Data Sampling
• Analyzing and Filtering
• Displaying Results
HeaderHeader
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High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
PCIe
MCL PDM
SDMPLA
Modular Single-channel Unit 1
MEM
MCSU
AD
DR
DA
TA
CCIU
LQAM MGR
Modular Single-channel Unit 2
PCIe
Dev
ice
A
Tx
Rx
PCIe Analyzer –Arch.
Gigabit Receiver1
1
Decryption Module2
Wrap Filter3
Packet Filter4
MSU Control5
Link Assessment6
2
34
5
6 Memory Controller7
Central Controller8
7
8
Physical
Physical
Transaction
Physical
Physical
Data Link
Transaction
Physical Data Link
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Originality• Minimized – Synthesis Oriented Programming
• Unique Algorithm Development
• Mathematical – Logical Solutions
• Optimized Performance
• Code - 10,000 Lines Open Source
• Embedded PCIe Generator
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
1)( 4131516 XXXXXG
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Innovation• Minimization - Entire System on Single Chip
• Unique Tool using Standard Hardware (300$)
• Minimal Resources yield Maximal Result
• Real Time Hardware Processing
• Open Code flexibility
• Embedded into System under Test
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
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Project Development Process
High Speed Communication Fundamentals
Semester A
Final ConceptRequirements Doc
PCI ExpressArchitecture Concepts
market surveyCurrent Available Products
Existing Infrastructure
Constructing Analyzer CoreBuilding Blocks
Semester B
Analyzer CoreDevelopment report
Debugging & TestingEach block
Final Core Integration
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות