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ECE615 Lecture 8
Mohamed Dessouky
Integrated Circuits Laboratory
Ain Shams University
Cairo, Egypt
Design of Analog Integrated
Systems (ECE 615)
Lecture 8
Delta-Sigma A/D Converters
ECE615 Lecture 8
Outline
Introduction
Oversampling
A/D Converters
Implementation
Converter Non-Idealities
M. Dessouky - ASU - ICL 2
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ECE615 Lecture 8
Introduction
How to obtain an ENOB of 20 bits using a 1-bit ADC!!
VLSI offers high speed devices and high density.
Such trend is also accompanied with reduced accuracy for
analog components and reduced supply, or signal range, which
causes reduced dynamic range.
Oversampling converters exchange digital complexity and time
resolution (speed) for signal amplitude resolution.
It uses what the advanced technologies offer in favor of ADCs.
M. Dessouky - ASU - ICL 3
ECE615 Lecture 8
Nyquist Rate A/D Converter
f
Xd
t
t
t
t
t
t
xin
xlpf
xs
xsh
xq
xd
f
Xlpf
f
Xs
f
Xin
fo fs 2fs 3fs 4fs
f
Xsh
Anti-Aliasing
Filter
Sample
& Hold
Quantizer
Encoder
xin
xlpf
xs
xsh
xq
xdb
xd
0010110
f
Xq
fo fs 2fs 3fs 4fs
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ECE615 Lecture 8
Oversampling
t
t
t
t
xs
xsh
xq
xd
f
Xd
f
Xs
fo fsfs/2
xd
Sample
& Hold
Quantizer
Down-
Sampling
xs
xsh
xq
xd
Encoderxdb
xd
0010110
Digital LPF f
Xq
fs/2
f
Xd
fo
f
Xsh oversampling
xlpf
Total noise powerNis spread fS/2 < f < fS/2
In-band noise power decreases
M. Dessouky - ASU - ICL 5
ECE615 Lecture 8
Oversampling
In-band Noise
For sampled noise, since the total noise powerNis
concentrated between fS/2 < f < fS/2, therefore the noise PSD is
The signal in-band noise is therefore
where is defined as the oversampling ratio.
Increasing the OSR by a factor of 4 will decrease the noise by6dB, thus increasing the DR by the same amount and
increasing the effective number of bits ENOB by 1 bit!
OSR
Nf
f
Ndf
f
NN
Q
o
s
Qf
f s
Qo
o
2
o
s
f
fOSR
2
s
Q
nf
NS
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ECE615 Lecture 8
Oversampling Antialiasing Filter
Relaxed transition band requirements for analog antialiasing(and reconstruction) filters.
Input
Nyquist Sampling
fS = fS(minimum) = 2fB
Oversampling
fS > 2fB
M. Dessouky - ASU - ICL 7
ECE615 Lecture 8
Outline
Introduction
Oversampling
A/D Converters
Implementation
Converter Non-Idealities
M. Dessouky - ASU - ICL 8
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ECE615 Lecture 8
Oversampling & Noise Shaping
Decimation
t
t
t
t
xlpf
xsh
xds
xd
f
Xd
f
Xlpf
fo fsfs/2
xd
Sample& Hold
Modulator
Digital LPF
Down-
Sampling
xlpf
xsh
xds
xd
xd
Encoder
xd
f
Xds
0010110
f
Xd
f
Xsh Oversampling
Noise is moved to high frequencis, then filtered.
M. Dessouky - ASU - ICL 9
ECE615 Lecture 8
Analog input fin
t
xin xd
Low Frequency (2fin)
High ResolutionHigh Frequency Large Noise
xq
A/D Converters
Time Domain
Digital LPF (averager)
Accumulates the difference between the inputxin , and the quantized signalxq.
A/D+
D/A
Decimationxinxq
xd
fsamp
Negative feedback subtracts an
analog version of the output from
the input signal.
+ Down-sampling
The integrator output is bounded only if its input (xin - xq) average is zero
D/A output tracks
the input
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ECE615 Lecture 8
A/D Converters Time Domain Assume 1-bit A/D: 1V, i.e.=2.
For an average zero, the output
should keep switching between
1V. Duty cycle=(/2)/=1/2.
For an average of 0.6V, i.e. 0.4V
from the lower limit=(0.4/2), the
output will be in average 4 times 1V
and 16 times 1V each 20 cycles.
Duty cycle=(4/20) /=1/5
Interpolation between 1V.
The modulator virtually adds extra
steps in the A/D.
The higher the frequency, the
higher the resolution of such
interpolation. DAC levels
Effective modulator
levels
eff
M. Dessouky - ASU - ICL 11
ECE615 Lecture 8
Modulators
Frequency Domain
H(s)Loop filter Quantizer
x y+
General Modulator
H(s)Loop filter
x y+
e
+ +
Linear Model
EsH
XsH
sHY)(1
1)(1
)(:ionsuperpositUsing
1(STF)FunctionTransferSignal)()(1
)(
sH
sH
sHx
)(
1(NTF)FunctionTransferNoise)(
)(1
1
sHsH
sHe
M. Dessouky - ASU - ICL 12
Assuming non-correlated white noise e. More valid for higher number
of quantizer bits.
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ECE615 Lecture 8
Modulators In-Band Noise For an n-th order integrator
or
Output Noise PSD
In-band Noise Power
ns
s
fsH
)(
ns
fj
fjH
2)(
n
ss
QNNyN
f
f
f
N
fHSNTFSS
222 2
)(
1
12
2
2
1
12
2
n
n
Q
f
f
n
ss
Qf
f
yN
OSRnN
dff
f
f
NdfSN
o
o
o
o
M. Dessouky - ASU - ICL 13
ECE615 Lecture 8
Dynamic Range
Thus, for an nth order modulator,every doubling ofOSRresults inan increase in DR of 6n+3 dB,ENOB by n+0.5 bits.
At high OSRs, every increase offilter order results in a largeincrease in DR.
Increasing quantizer by 1 bitreduces NQ by 6dB (1 extraENOB) as in a normal ADC.
OSRnn
NdBNn
Q log121012
log10log10)(2
Slight noise increase
at very low OSR
Dominant at high OSR
OversamplingNoise shaping
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ECE615 Lecture 8
Loop Filter: First-Order Modulators
Integrator
u v+
+ ++
+
1z
e
ezuzv )1( 11
1
1
1)(
z
zzH
11)( zzNTF
s
fTj
f
f
efNTFs
sin21)(2
sf
ffNTF
2)(
Integrator
u v+
+ ++
+
e
1z
1z
ezuv )1( 1
11
1)(
zzH causality
delay
In both cases:
In the frequency domain:
At f
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ECE615 Lecture 8
Second-Order Modulatorse
Integrator 1
u v+
+ ++
+1
z
Integrator 2
++
1z+
ezuzezzuzv 211211 )1()21(
s
fTj
f
fefNTF s
2
22
sin41)(
M. Dessouky - ASU - ICL 17
ECE615 Lecture 8
First order
Output Power Spectral Density (PSD)
-20dB/decade
n
ss
Q
NNyNf
f
f
N
fHSNTFSS
22
2 2
)(
1
s
Q
s
yNf
N
f
fnS log10
2log102)dB(
Second order
-40dB/decade
Third order
-60dB/decade
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ECE615 Lecture 8
Outline
Introduction
Oversampling
A/D Converters
Implementation
Converter Non-Idealities
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ECE615 Lecture 8
Linear Analysis ??
White noise assumption is only
valid for high number of
quantizer bits.
Otherwise, the model becomes
dependent on the input signal
statistics!!
Noise statistical analysis has
been done for 1st and 2nd order.
Higher order analysis is verycomplicated!!
Design is based on simulation
of the non-linear model.
Simulations reveal stability
problems non-predictable with
linear analysis.
H(s)Loop filter
u v+
e
+ +
Linear Model
H(s)Loop filter Quantizer
u v+
Non-linear Model
!!
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ECE615 Lecture 8
Practical
Max. SQNR
SQNR increases with OSR and Modulator order n (noiseshaping).
Practical SQNR is less than the theoritical one.
n = noise-shaping order
Theoritical
M. Dessouky - ASU - ICL 21
ECE615 Lecture 8
Implementation
To reduce output noise power
Reduce quantizer step: A/D and D/A with more bits.
Increase loop filter order: Larger circuit. Stability issues.
Increase the OSR: More speed
Each of the above leads to more complex design and more
power consumption
System-level compromise depends on the application to
minimize power consumption
H(s) A/DLoop filter
x y+
D/A
12
22 1
1212
n
n
yOSRn
N
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ECE615 Lecture 8
Loop Filter
Discrete-time implementation
More popular
Design experience
Inherent sampling errors
sC
G
V
V m
i
o
H(s) A/DLoop filter
x y+
D/A
H(z)x +
H(s)x +
Continuous-time implementation
No sampling errors
Less power
Clock jitter
M. Dessouky - ASU - ICL 23
ECE615 Lecture 8
SC Integrator: Inverting
zVCzVCzzVCioo 12
1
2
11
1
2
11
2
1
z
z
C
C
zC
CzH
nVCnVCnVC ioo 122 1
Same as the inverting amplifier,
but C2 is not discharged each
cycle.
C2 accumulates a negative
charge each 1 such that
which gives in the z-domain
The transfer function becomes
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ECE615 Lecture 8
SC Integrator: Non-Inverting
zVCzzVCzzVC ioo 11
21
2
1
1
1 2
11
1
2
1
zCC
z
zCCzH
11 122 nVCnVCnVC ioo
Same circuit but with different
phase control.
During 1, C1 is charged.
During 2, C1 is discharged in
C2 such that
which gives in the z-domain
The transfer function becomes
M. Dessouky - ASU - ICL 25
ECE615 Lecture 8
Feedback DAC
Uses an input switched-capacitor branch to subtract the reference
voltage from the input.
If the feedback coefficient equals to the input coefficient we can
use only one sampling capacitor.
inverting
SC branch
invertingamplifier
non-inverting
integrator
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ECE615 Lecture 8
Outline
Introduction
Oversampling
A/D Converters
Implementation
Converter Non-Idealities
M. Dessouky - ASU - ICL 27
ECE615 Lecture 8
ADC Errors
ADC quantization error is shaped by the modulator loop.
If ADC errors (offset, gain and nonlinearity) are smaller than the
quantization error, they will affect the modulator performance. Since the ADC already has a large quantization step (small
number of bits), usually other errors have a big margin.
Another explanation: ADC errors when referred to the input, are
divided by a large loop filter gain in the signal band. Errors are
greatly attenuated.
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ECE615 Lecture 8
DAC Errors
DAC errors are directly injected at
the input of the modulator together
with the input signal.
Gain and offset errors are translated
to gain and offset errors for the
modulator. Easily removed.
Modulator interpolating levels will
join consecutive DAC big steps.
DAC linearity errors (d) should be of the same accuracy as the
complete ADC, i.e.
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ECE615 Lecture 8
Integrator Errors
Offset of the first integrator
contributes to an ADC offset.
Offset of following integrators are
divided by a high dc gain of
previous integrators.
Finite opamp gain, bandwidth and
slew-rate cause modifications to
the STF and NTF by adding extra
poles and zeros.
M. Dessouky - ASU - ICL 31
Such modifications cause an increase in the noise in the signal
band.
The effect of such errors are often studied using system-level
simulations.
ECE615 Lecture 8
Signal Levels
The reference voltage is the maximum obtainable voltage.
All signals are normalized to the reference voltage.
For the modulator to be realizable on the circuit level, all
normalized internal signals must be confined to 1.
H(s) A/DLoop filter
x y+
D/A
VREF
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ECE615 Lecture 8
Example: Second-Order Modulator
e
Integrator 1
u v+
+ ++
+1
z
Integrator 2
++
1z+
Integrator 1
u v+
+ ++e
Integrator 2
++
1z
+
1/2 1/2
+
1z
Second
integrator
outputhistogram
First
integratoroutput
histogram
M. Dessouky - ASU - ICL 33
Modified architecture with smaller signal ranges at integrator outputs
ECE615 Lecture 8
Error Simulation
Integrator 1
u v+
+ ++e
Integrator 2
++
1z
+
+
1z
1/zSLEW
psf
pinf
gsf
ginfx y
Integrator model
Block
Non-Ideality
Modeling
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ECE615 Lecture 8
Building Block Specifications
Using non-ideal block models, simulate the Sub-System
Study the effect of each non-ideality on the overall performance
Deduce the block specifications
DC gain GBW/fs SR/(Vref/Ts)
M. Dessouky - ASU - ICL 35
ECE615 Lecture 8
SC Second-Order Modulator
Integrator 1
u v+
+ ++e
Integrator 2
++
1z
+
1/2 1/2
+
1z
Architecture with smaller signal ranges at integrator outputs
2
1
2
1 C
C
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ECE615 Lecture 8
SC Second-Order Modulator
Sample inputs(integrator)
Compare outputs
Enable feedback(inverting amplifier)
Integrate
Reset comparator
2
1
2
1 C
C
M. Dessouky - ASU - ICL 37
ECE615 Lecture 8
Total Noise
Circuit noise is reduced with more power consumtion.
Quantization noise is usually designed less than circuit noise (by
~3 dB).
Noise
Quantization
Noise
Circuit
Noise
Switching
Noise (kT/C)
Opamp
1/f Noise
Thermal
Noise
Opamp
Noise
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References
Steven R. Norsworthy, Richard Schreier, and Gabor C. Temes
(editors), Delta-Sigma Data Converters Theory, Design, and
Simulation, IEEE Press, 1997.
Franco Maloberti, Data Converters, Springer, 2008.
Bruce Wooley & Katelijn Vleugels, EE315: VLSI Data Conversion
Circuits Handouts , Department of Electrical Engineering,
Stanford University, http://www.stanford.edu/class/ee315/
David Johns & Ken Martin, Analog Integrated Circuit Design , John
Wiley & Sons, Inc., 1997.
Behzad Razavi, Design of Analog CMOS Integrated Circuits ,
McGraw-Hill, 2001.
Error Simulation: P. Malcovati et.al., Behavioral Modeling of
Switched-Capacitor Sigma-Delta Modulators, IEEE Trans. Circuits and
Systems-I: Fundamental Theory and Applications, Vol. 50, No. 3,March 2003
M. Dessouky - ASU - ICL 39