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Logic Level Design Automation
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n u Transistor-Level u Switch-Level u Gate-Level u Register-Transfer-Level u System-Level u Mixed-Level (Mixed-Mode)
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n Transistor-level u u SPICE :
n Switch-level u
. u ,
. u SPICE net-list
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n Gate-level or logic-level
u 1 . u . u Verilog, VHDL
n Register-transfer-level (RTL) u . u
u Verilog, VHDL
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n System-Level
t t t SystemC, System-Verilog, Spec-C
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n Mixed-level u ,
n Mixed-mode
u The simulator use different mechanism for different levels (e.g. a timing-driven numerical integration and event-driven technique)
n Hardware-Software co-simulator u The solution for digital design problems contains
programmable hardware.
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n The simulator kernel u .
n u
u . u .
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n u u
n u u u u
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Gate-level modeling and simulation n Signal modeling n Gate modeling n Delay modeling n Connectivity modeling n Simulation mechnism
u Event-driven u Compiler-driven u Demand-driven
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Signal modeling
n Binary or Boolean signals u ‘0’ , ‘1’ u ‘X’ : unknown u ‘U’ : uninitialized u strength of signal
t weak, strong, etc.
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Gate modeling
n Truth table u the table has a row for
each conbination of input signal value.
n Subroutine u By machine instructions
A truth-table modeling of a two input NAND gate.
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Delay modeling
n The propagation delay model u Fixed delay with the gate’s output u A delay depend on “the output’s fanout” u Zero-delay u Unit-delay
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Delay modeling cont’d. n The rise/fall delay model
u Different delay are used when when an output signals rise and when it falls
n The inertial delay model u The property observed in physical circuits. u The input pulse should have minimal width in order
to have any effect at the output. n The inertial delay model can be combined with both
the propagation and the rise/fall delay model.
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A 2-input NAND gate and its switching input signals (a); the corresponding output signal in the propagation delay model (b), in the rise/fall delay model.
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Connectivity modeling
n Simulator should have suitable data structure to represent the connectivity of all gates in the network.
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Compiler-driven simulation
n The best choice occurs in the context of synchronous circuits.
The core of synchronous circuit.
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A simple circuits composed of logic gates
Code for the zero-delay simulation
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The appearing of a “glitch” on net n9 in the circuit when using unit-delay model.
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Pseudo-code meant for the compiler-driven simulation of the circuit using the unit-delay model DesingAutomation Handsout 2
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Event-driven simulation
n Recompute signals that are actually changing. n A signal change is called an event. n Different delay models can be incorporated in
the simulator relatively easily. n event-queue or event-list is the central data
structure.
DesingAutomation Handsout 2 36 The array implementation of the event-queue
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The time-wheel implementation of the event-queue DesingAutomation Handsout 2 38
Pseudo-code of event-driven simulation function
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