documentation standards
DESCRIPTION
Documentation Standards. Block diagrams first step in hierarchical design Schematic diagrams Timing diagrams Circuit descriptions. Documentation standard. Block Diagram. Schematic diagrams. Details of component inputs, outputs, and interconnections Reference designators Title blocks - PowerPoint PPT PresentationTRANSCRIPT
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Designing with MSI
Documentation Standards
Block diagramsfirst step in hierarchical design
Schematic diagrams Timing diagrams Circuit descriptions
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Designing with MSI
Documentation standard
Block Diagram
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Designing with MSI
Schematic diagrams
Details of component inputs, outputs, and interconnections Reference designators Title blocks Names for all signals Page-to-page connectors
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Designing with MSI
Input keys
Digit1 Digit0
8
8
Select one of Mux
Display
D1 D0
8
8
Error_Key1
Error_Key0
(warmer + cooler) From BCD calculator
To BCD calculator
To Error Display
Wake Period
Block Diagram For Wake
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Designing with MSI
Chapter : Design modules
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Designing with MSI
I. Using MUX to Implement logic function
A multiplex (Data selector) is a CLN module with: – 2n data inputs– n control inputs– 1 output Depending on the control inputs, the multiplexer connects one of the inputs
to the output line. Block diagram of an 4-to-1 multiplexer:
D0D1D2D3
C1 C0
I0I1I2I3
Y4-to-1 MUXData inputs
Data select
Y’
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Designing with MSI
I. Using MUX to Implement logic function
Circuit of an 4-to-1 multiplexer
D0
D1
D2
D3
C1 C0
C1’C0’D0
C1’C0D1
C1C0’D2
C1C0D3
Y
Y’
OR
May add an enable signal E
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Designing with MSI
I. Using MUX to Implement logic function
Block diagram of an 8-to-1 multiplexer:
D0D1D2D3D4D5D6D7
C2 C1 C0
I0I1I2I3I4I5I6I7
Output8-to-1 MUXData inputs
Data select
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Designing with MSI
I. Using MUX to Implement logic function
Circuit of an 8-to-1 mulmtiplexer
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Designing with MSI
I. Using MUX to Implement logic function
Truth table of an 8-to-1 mulmtiplexer
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Designing with MSI
I. Using MUX to Implement logic function
A 2n input lines and n selection lines MUX may be used to realize any function of (n+1) variables
Example of design
Example
Use an 8-to-1 MUX to realize the following function of 4 variables
F( A,B,C,D) = (0,2,4,5,6,8,10,13) = A’B’C’D’ + A’B’CD’ + A’BC’D’ + A’BC’D + A’BCD’ + AB’C’D’ + AB’CD’ + ABC’DSolution Use the variables A, B, C as the control (selection) inputs and use the
remaining variable D to determine the input lines. Rewrite F to to determine a factor for each input combination ABC: F( A,B,C,D) = A’B’C’D’ + A’B’CD’ + A’BC’(D’ + D) + A’BCD’ + AB’C’D’ + AB’CD’ + ABC’D + ABC (0)
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Designing with MSI
I. Using 8-to-1 MUX to Implement logic functionExample
Solution (Continued ….)F( A,B,C,D) = A’B’C’D’ + A’B’CD’ + A’BC’(D’ + D) + A’BCD’ + AB’C’D’ + AB’CD’ + ABC’D + ABC (0)So the input to the 8-to-1 MUX are given by :I0=D’, I1=D’, I2=1, I3=D’, I4=D’, I5=D’, I6=D, I7=0
1
D0D1D2D3D4D5D6D7 C2 C1 C0
D’D’1D’D’D’D0
F(A,B,C,D)8-to-1 MUX
A B C
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Designing with MSI
I. Using 8-to-1 MUX to Implement logic function
Same function F(A,B,C,D) Use BCD as the selection (control ) lines
F( A,B,C,D) = (0,2,4,5,6,8,10,13) = A’B’C’D’ + A’B’CD’ + A’BC’D’ + A’BC’D + A’BCD’ + AB’C’D’ + AB’CD’ + ABC’D = B’C’D’ ( ) + B’C’D ( ) + B’CD’ ( ) + B’CD ( ) + BC’D’ ( ) + BC’D ( ) + BCD’ ( ) + BCD ( )
= B’C’D’ ( A+A’ ) + B’C’D ( 0 ) + B’CD’ (A’ + A) + B’CD ( 0 )
+ BC’D’ ( A’) + BC’D ( A’+A ) + BCD’ ( A’ ) + BCD ( 0 )
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1
Example
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Designing with MSI
I. Using 8-to-1 MUX to Implement logic function
D0D1D2D3D4D5D6D7 C2 C1 C0
1010A’1A’0
F(A,B,C,D)8-to-1 MUX
B C D
ExerciseRepeat using as selection lines:•A, C, D•A, B, D
Example
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Designing with MSI
I. Using 4-to-1 MUX to Implement logic function
F(A,B,C,D) = (3,4,8,9,10,13,14,15) = A’B’CD + A’BC’D’ + AB’C’D’ + AB’C’D + AB’CD’ + ABC’D + ABCD’ + ABCD
Use AB for Selection lines and factor out the various combinations of AB = A’B’ ( CD ) + A’B ( C’D’ ) + AB’( C’D’ + C’D + CD’ ) + AB ( CD’ + CD’ + CD ) = A’B’ ( CD ) + A’B ( C’D’ ) + AB’( C’ + D’ ) + AB ( C + D )
Implement the circuit of the input lines using NAND (or other) gates
Example
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Designing with MSI
I. Using 4-to-1 MUX to Implement logic function
D0
D1
D2
D3 C1 C0
F4-to-1 MUX
A B
F’
C
D
C’
D’
Example
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II. Decoders
Depending on the control inputs, the multiplexer connects one of the inputs to the output line.
Block diagram of an 4-to-1 multiplexer:
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Designing with MSI
II. Decoders
General decoder structure
Map each input code to one of the output Typically n inputs, 2n outputs
– 2-to-4, 3-to-8, 4-to-16, etc.
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II. Decoders
Note “x” (don’t care) notation.
Binary 2-to-4 decoder
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II. Decoders
00
01
10
11
2-to-4-decoder logic diagram
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Designing with MSI
II. Decoders
Input buffering (less load) NAND gates (faster)
00
01
10
11
MSI 2-to-4 decoder
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II. Decoders
Decoder Symbol
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II. Decoders
Complete 74x139 Decoder
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Designing with MSI
II. Decoders
More decoder symbols
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Designing with MSI
II. Decoders000
001
010
011
100
101
110
111
3-to-8 Decoder
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II. Decoders
74x138 3-to-8-decoder symbol
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Designing with MSI
I. Using decoders to Implement logic function
01234567
Example: Given F1 = X,Y,Z (1,2,3) and F2 = X,Y,Z (3,5,6,7)
Implementation using 3-to-8 Decoder
XYZ
OR F1
OR F2
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Designing with MSI
I. Using decoders to Implement logic function
01234567
Example: Given F = X,Y,Z (0,2,3,4,6,7)
Implementation using 3-to-8 Decoder
We will implement the complement of F and “NOT” the resultF’ = m1 + m5
XYZ
OR F’ F
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Designing with MSI
III. Programmable Logic devices
Any combinational logic function can be realized as a sum of products.
Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections.– n inputs
AND gates have 2n inputs -- true and complement of each variable.
– m outputs, driven by large OR gates Each AND gate is programmably connected to each output’s
OR gate.– p AND gates (p<<2n)
Programmable Logic Arrays (PLAs)
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Example: 4x3 PLA, 6 product terms
III. Programmable Logic devices
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Compact representationIII. Programmable Logic devices
Input programming
Output programming
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Some product terms
III. Programmable Logic devices
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Designing with MSI
General description
IV. Demultiplexer
1-to-2n Demultiplexer has: – 1- input– Multiple outputs – n select lines
Function: Route the single input to the selected output
I
1-to-2n DEMUX
Data input
Select lines
…
...
O0
O1
Om
m = 2n - 1
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Function table of a 1-to-4 Demux
IV. Demultiplexer
I
1-to-4 DEMUX
Data input
Select lines
O0
O1
O2 O3
x y
x y
0 0
O0 O1 O2 O3
I 0 0 00 1 0 I 0 01 0 0 0 I 01 1 0 0 0 I
O1 = x‘y’IO2 = x’y IO3 = x y’IO4 = x y I
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Designing with MSI
V.Design by Cascading
Cascading MUXesDesign an 8-to-1 MUX using 4-to-1 MUX and other gates
D0D1D2D3D4D5D6D7
C2 C1 C0
I0I1I2I3I4I5I6I7
Output8-to-1 MUXData inputs
Data select
En
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Designing with MSI
V.Design by Cascading
Cascading MUXesDesign an 8-to-1 MUX using 4-to-1 MUX and other gates
D0D1D2D3
C1 C0
I0I1I2I3
Output4-to-1 MUX
En
D0D1D2D3
C1 C0
I0I1I2I3
4-to-1 MUX
En
0
1
C2 C1 C0
I4I5I6I7
OR
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Designing with MSI
V. Design by cascading Decoders
Note “x” (don’t care) notation.
Cascading Decoders
Recall: Decoder with an enable signal En
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Designing with MSI
V. Design by cascading Decoders
Cascading DecodersRecall: Decoder with an enable signal En
Decoder2-to-4
d0d1d2d3
i0i1
En
1-to-2d0d1i0
En
En i0 d0 d10 X1 01 1
0 01 00 1
En i0 i1 d0 d1 d2 d30 X X1 0 01 0 11 1 01 1 1
0 0 0 01 0 0 00 1 0 00 0 1 00 0 0 0
i0 En
d0
d1
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Designing with MSI
V. Design by cascading Decoders
Cascading DecodersDesign of a 2-to-4 decoder using 1-to-2 decoders
Decoder2-to-4
d0d1d2d3
i0i1
En
1-to-2d0’d1’
i0’
En’
1-to-2d0’d1’i0’
En’
En i1 i0
d0d1
d2d3
2-to-4 Decoder
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Designing with MSI
V. Design by cascading DecodersCascading Decoders
Design of a 2-to-4 decoder using 1-to-2 decoders
1-to-2d0’d1’
i0’
En’
1-to-2d0’d1’i0’
En’
En i1 i0
d0d1
d2d3
2-to-4 Decoder
Operation•En enable or disable the decoder•i1=0 enables the top decoder•I1=1 enables the lower decoder
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Designing with MSI
V. Design by cascading DecodersCascading Decoders
Design of a 4-to-16 decoder using 2-to-4 decoders
2-to-4
d0 d1 d2 d3
En i1 i0 2-to-4
d0 d1 d2 d3
En i1 i0 2-to-4
d0 d1 d2 d3
En i1 i0 2-to-4
d0 d1 d2 d3
En i1 i0
2-to-4
d0 d1 d2 d3
En i1 i0
Eni3i2i1i0
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
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Designing with MSI
VI.Modular Design
Goal– Use existing components or design subcomponents as building
blocks of higher circuit Types of solutions
– Casdading components– Ripple design
Some outpout at level i are used input at the next level (i+1) Linear cascading of elements
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VI.Modular Design
Design of a 2 bits binary adder
Motivations
Binary adderX
YS
S = X + Y X=[X1X0], Y=[Y1Y0], S=[S2S1S0]
Two types of design possible:• Brute force approach: Draw a truth table and derive the expressions of the output variable •Iterative design
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VI.Modular Design
Example: 2 bits binary adder
X1 X0 Y1 Y00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
0 0 00 0 10 1 00 1 10 0 10 1 00 1 11 0 00 1 00 1 11 0 01 0 10 1 11 0 01 0 11 1 0
S0 S1 S0
What if we want to do design a 5 bits adder:-Truth table with 10 variables-Not pratical
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Designing with MSI
VI.Modular Design
Iterative design •Identify a basic component: 1-bit adder with carry in•Use the basic component iteratively
Basic component
1-bit Full adder
XiYi Ci
SiCi-1
Design of Basic component•Draw its truth table•Design the corresponding circuit
Iterative design of n-bit adder
Xn-1 Yn-1
Cn-2
Sn-1
Cn-1
Xn-2 Yn-2
Cn-3
Sn-2
C0
X0 Y0
C-1
S0
…1-bit Full adder
1-bit Full adder
1-bit Full adder
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VI.Modular Design
Design an n-bit comparator to produce the following output F: •F=1 if X > Y•F= 0 otherwise X, Y are n-bit binaries
Another Example of Modular Design
Basic component C1 •A 1-bit comparator with comparaison result from preceeding stage•3 inputs
Xi and Yi bit at stage i, and Fi-1 Result from stage i-1• 1 output: Fi result of stage I
Iterative comparaison of two n-bits X=[Xn-1 …X0] and Y=[Yn-1 …Y0]
Xn-1
Yn-1Fn-1
Xn-2
Yn-2
X1
Y1Fn-2
X0
Y0F1 F0Fn-3 0Cn-1 Cn-2 C1 C0
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VI.Modular Design
Design of the Basic 1-bit Comparator CiAnother Example of Modular Design
Xi
YiFi Fi-1Ci
Fi-1 Xi Yi0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 0 101011
Fi
Truth Table XiYiFi-1
0
1
00 01 11 10
1
1 1 1
Fi = XiFi-1 + XiYi’ + Yi’Fi-1Xi Yi
Fi-1
Fi-1
0 1
4-to-1MUX
Fi
K-map
MUX implementation
Simplified SOP Logic Expression