industrial control system for a back-to-back multilevel npc converter based on dsp and fpga

Industrial control system for a back-to-back multilevel NPC converter based on DSP and

FPGAMarta Alonso, Francisco Huerta, Carlos Girón, Emilio Bueno,

Álvaro Hernández, Francisco J. Rodriguez, Santiago Cóbreces

Department of Electronics. Alcalá [email protected]

[email protected]

ISIE2007

Alcalá University Department of Electronics

Researching group of Electronic Engineering applied to Renewable Energy Systems (GEISER)

Contents

1. Introduction2. Proposed Control Electronic

System3. Computational and Coprocessor

Module Design4. FPGA implementation5. Simulation Results6. Conclusions


ISIE2007Researching group of Electronic Engineering applied to Renewable Energy Systems (GEISER)

1. Introduction (1/1)Alcalá University Department of Electronics


ezDSP F2812+

turbine interface

WIND TURBINE CONTROL

Power Electronic System

AC Motor

VSC 1 VSC 2

Sa2

Sa1

Sa2

Sa1

Sb2

Sb1

Sb2

Sb1

Sc2

Sc1

Sc2

Sa2

Sa1

Sa2

Sa1

Sb2

Sb1

Sb2

Sb1

Sc2

Sc1

Sc2

Sc1

3*L1 3*L2

3*Co

CDC2

NP

P

N

CDC1

Da2

Da1

Db2

Db1

Dc2

Dc1

Da2

Da1

Db2

Db1

Dc2

Dc1

ea eb ec

PCC

n

ADC’s Measure of grid filter

variables

ADC’s Measure of DC-bus

variables

ADC’s Measure of motor

variables

PWM VSC 1 PWM VSC 2 FPGA SPARTAN II

DSP TMS6713 VSC 1 Control

VSC 2 Control

Sc1

Communication Board Interface Board between Computational

Module - Power Electronic System

Computational Module

Control Electronic System

USB communication

CAN Bus

Generator driving

Exterior world communication (Ethernet, SCADA, etc.)

CAN Bus

CA

N B

us

FPGA SPARTAN III

Contents






Proposed Control Electronic System (1/2)Alcalá University Department of Electronics

ISIE2007

DSP FPGA

Analog SignalsAdaptation

Data acquisitionA/D conversion

Driving ofIGBTs.

Faults ofIGBT drivers.

Driving ofrelays.

Opticaltransmitters

OpticalreceiversA

nalo

gsi

gnal

s

Relays

System referencesProcessor Module Coprocessor Module

ToIGBT drivers

ToIGBT drivers

Computational Module

• IGBT Swiching periodTpwm=400μs.

• Sampling periodTs=Tpwm/2=200 μs.


Proposed Control Electronic System (2/2)Alcalá University Department of Electronics

ISIE2007

Selection of DSP

Integrated peripherals

☺☺☺Simplicity of programming

Data precision

☺☺☺☺Cost

FloatingPoint

Fixed Point

Characteristics

DSP TI TMS320C6713


Selection of FPGAXC3S500E PQ208

(Spartan 3E of Xilinx):

500K system gates

10476 equivalent logical cells

232 maximum user I/O

360Kbit blocks RAM

Contents






Computational and coprocessor module design (1/3)

Task distribution:–Tasks with data dependences should be located in the same

device–The lack of integrated periphery of the DSP selected are

solved by the FPGA–High computational and repetitive tasks are implemented by

the FPGA–Variable tasks are executed by the DSP–Non critical tasks are placed in the DSP



DSPHigh computational tasks:

· Signal processing· Monitoring· User interface

FPGAConcurrency, flexilibility and portability:

· Data acquisition· Signal adapting· Data storage


Department of ElectronicsUniversity of Alcalá

FPGAParallel-200μsAcquisition data

FPGAParallelArithmetic200μsEncoder reading

FPGAParallelArithmetic200μsPWM generation (carrier frequency 2.5KHz and 24 signals)

For the two converters

DSPArithmetic200μsTurbine controller. Tracking of the

maximum power point.

DSPControl

Trigonometric and matrix

<200μs

200μsVector controller.

For the generator-side converter

DSPArithmetic200μsDC-bus voltage controller

DSPArithmetic200μsSPLL [17]

FPGA200μsDSC (Delay Signal Cancellation) [17]

FPGA200μsIdentification of different disturbances

DSP

Control

Trigonometricand matrix

<200μs

200μsCurrent vector controller

For the line-side converter

Selected DeviceAlgorithm type

Operation typeTrunTSTasks



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Block diagram of the modules implemented in the FPGA

Contents






FPGA implementation: DSP-FPGA Synchronization (1/12)



FPGA implementation: DSP-FPGA Synchronization (2/12)


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• SYNC signal: every 200μs.• The PWM carrier signals are generated

with a period of 400μs.• At every maximum and minimum of

these signals:SYNC is triggered DSP external interruption is activated. • FPGA acquires samples, while the

DSP remains stalled until acquired data are available.

• The FPGA provides these data to the DSP, and the DSP transmits the new references for the FPGA PWM generator.


FPGA implementation:Acquisition of Analog Signals (3/12)




Acquisition specifications:12-bit precisionSampling frequency: 5kHzSynchronization (SYNC signal)Simultaneous sampling of 20 channels (5 ADCs)





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Acquisition Finite State Machine


FPGA implementation: PWM generation (6/12)




• IGBTs are limited by a minimum swicthing time


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• Narrow pulses are removed:– Filtering– Changing reference

signal

• Narrow pulses are extended




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• THSPWM techniques

Carriergeneration

Referencesignal withzerosequence

Modulatedsignals(withdeadtime)


FPGA implementation: Speed measurement (9/12)




• First method:– Encoder pulses are counted– Limitation: Low accuracy in high

speed measurements


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#pulses: number of counted pulsesLinecount: number of encoder linesTact: Time between two values are stored

actTcountlinepulsesv

·#

=

)(·

60 rpmcountlinepulseperiod

v =

Acquisition Finite State Machine


• Second method:– Period of the encoder pulses is

measured by using the clock signal of the FPGA

– Limitation: Minimum speed with a 24 bit register 0.1746 rpm




· 20ns ≈ 80μs · 20ns ≈ 160μs

FPGA implementation: Other peripherals (12/12)



• Boot-loader.• USB communication.

Contents



Module Design4. FPGA implementation5. Experimental Results6. Conclusions



Experimental results (1/5)



TMS320C6713 DSK Acquisition block

Compact Flash

Optical transmitters and receivers

Communication USB module FPGA

XC3S250E

Experimental results: DSP execution (2/5)



TS

Control algorithm execution

k-1 k k+1 k+2

Number of cycles

Execution graph

Universidad de Alcalá Departamento de Electrónica

1,35%2,4%2,4510μs

0,04%0,05%0,04%200μs

<0,01%<0,01%<0,01%1 s

64 Bytes124 Bytes128 Bytes

Frame sizeSamplingtime


Experimental results: USB communication (3/5)

TS




0 20 40 60 80 100 120 1400

500

1000

1500

2000

0 20 40 60 80 100 120 140550

600

650

700

750

time(s)

uDC*(V)

uDC (V)

wgenerator* (rpm)

wgenerator (rpm)




0 20 40 60 80 100 120 140

0

100

200

300

400

0 20 40 60 80 100 120 140-10

-5

05

1015

2025

time(s)

edp (V)

eqp (V)

idmot (A)

iqmot (A)

Contents



Module Design4. FPGA implementation5. Experimental Results6. Conclusions



ConclusionsAlcalá University Department of Electronics


A novel real-time controller for a NPC multilevel converter based on a floating DSP and an FPGA has been presented.

The use of these two processors allows the parallel implementation of algorithms, increasing the processing rate.

It is necessary to achieve an optimal task distribution to improve the control electronic system performance. This work has been focused to the implementation of the FPGA tasks.The FPGA programming has been tested in the interface board, the communication between the different modules is right and the expected results have been achieved.

Industrial control system for a back-to-back multilevel NPC converter based on DSP and

FPGA

Marta Alonso, Francisco Huerta, Carlos Girón, Emilio Bueno, Álvaro Hernández, Francisco J. Rodriguez,

Santiago CóbrecesDepartment of Electronics. Alcalá University

[email protected]@depeca.uah.es

ISIE2007



ACKNOWLEDGMENTS

This work has been financied by the Spanishadministration (ENE2005-08721-C04-01)

industrial control system for a back-to-back multilevel npc converter based on dsp and fpga

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