DESIGN OF LOW POWER SRAM CELL WITH IMPROVED STABILITY

DISSERTATION REPORT SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE AWARD OF THE DEGREE OF MASTER OF TECHNOLOGY

IN CONTROL AND INSTRUMENTATION SYSTEMS

Submitted By

JAVED AKHTAR ANSARI (Roll no. - 13MCIS-07)

Under the Supervision of

Prof. ABDUL QUAIYUM ANSARI

Department of Electrical Engineering

Faculty of Engineering and Technology

Jamia Millia Islamia

New Delhi - 110025

2015

DEPARTMENT OF ELECTRICAL ENGINEERING

FACULTY OF ENGINEERING AND TECHNOLOGY

JAMIA MILLIA ISLAMIA

CERTIFICATE

This is to certify that the project titled “ DESIGN OF LOW POWER SRAM CELL WITH

IMPROVED STABILITY ” submitted in partial fulfillment of the requirements of the award

of the degree of Master of Technology in Control and Instrumentation System by “JAVED

AKHTAR ANSARI (13CIS-07)” is a bona fide record of the candidate’s own work carried out

by him/her under my supervision and guidance.

This work has not been submitted earlier in any university or institute for the award of any

degree to the best of my knowledge.

Professor A. Q. Ansari (Supervisor) Department of Electrical Engineering Faculty of Engineering and Technology Jamia Millia Islamia

New Delhi – 110025 (India) Prof. Majid Jamil (HOD)

ACKNOWLEDGEMENT

I thank almighty Allah (swt) who is the source of all type of knowledge and

deserves all kind of praises and thanks.

It is my proud privilege to express deep sense of gratitude, heartfelt regards,

appreciation and indebtedness to my supervisor Prof. A. Q. Ansari, Department of Electrical

Engineering, Faculty of Engineering & Technology, Jamia Millia Islamia for his invaluable

guidance, deep-rooted interest, inspiration & continuous encouragement throughout the project

work. He gave me the opportunity to work on such an interesting theme and he has essentially

contributed to this work through his guidance and encouragement. Words do not come easy and I

found myself in difficult position of attempting to express my deep indebtedness to all Faculty

Members of Electrical Engineering Department. I am very thankful to Dr. M. S. Hashmi, IIIT

Delhi, for his support and guidance

I owe my heartfelt regards to my parents, my brother and my friends who have been

my constant source of inspiration, motivation and encouragement.

Javed Akhtar Ansari Roll no. 13MCIS-07 M. Tech (CIS)

Department of Electrical Engineering

Faculty of Engineering and Technology

Jamia Millia Islamia

New Delhi – 110025 (India)

CONTENTS PARTICULARS PAGE NO LIST OF TABLES vi

LIST OF FIGURES vi

ABBREVIATIONS viii

ABSTRACT ix

CHAPTER 1 INTRODUCTION 1

1.1 Background...................................................................................................... 1

1.2 Motivation......................................................................................................... 4

1.3 Literature Review............................................................................................. 5

1.3 Objective........................................................................................................... 10

CHAPTER 2 THEORATICAL BACKGROUND 11

2.1 Introduction...................................................................................................... 11

2.2 SRAM............................................................................................................... 13

2.2.1 SRAM CELL............................................................................................... 13

2.2.2 Read operation............................................................................................. 14

2.2.3 Write operation............................................................................................ 15

2.2.4 Cell stability.................................................................................................. 15

2.3 Performance parameters of SRAM cell............................................................ 16

2.4 Calculation of Static Noise Margin.................................................................. 16

CHAPTER 3 POWER CONSIDERATION IN SRAM CELL 19

3.1 Low power techniques in SRAM memory……………………………………. 19

3.1.1 Gate clocking………………………………………………………………. 19

3.1.2 Multi-Vth optimization……………………………………………………... 20

3.1.3 Multi supply voltage………………………………………………………. 21

3.2 Dominant leakage mechanism in CMOS transistors…………………………. 21

3.2.1 Junction leakage…………………………………………………………… 21

3.2.2 Gate induced drain leakage………………………………………………… 22

3.2.3 Gate direct tunneling leakage……………………………………………… 22

3.2.4 Subthreshold leakage……………………………………………………… 23

CHAPTER 4 SIMULATION OF SRAM CELLS 25

4.1 Software tool.................................................................................................... 25

4.2 Schematic and working of 6T SRAM cell........................................................ 25

4.2.1 Output waveform of 6T SRAM cell......................................................... 26

4.3 Schematic and working of 8T SRAM cell...................................................... 29

4.3.1 Output waveform of 8T SRAM cell.......................................................... 30

4.4 Schematic and working of 9T SRAM cell....................................................... 32

4.4.1 Output waveform of 9T SRAM cell........................................................... 33

4.5 Schematic and working of proposed 7T SRAM cell....................................... 35

4.5.1 Output waveform of proposed 7T SRAM cell........................................... 36

4.6 Result................................................................................................................ 39

CHAPTER 5 CONCLUSION AND FUTURE SCOPE 40

5.1 Conclusion…………………………………………………………………… 40

5.2 Future work………………………………………………………………..... 40

REFERENCES 41

APPENDIX A 45

LIST OF TABLES

Table 1. …………………………………...………………………………………. 22

Table 2. ……………………………………..…………………………………….. 22

LIST OF FIGURES

Fig. 1.1 Transistors in Intel microprocessors [Intel10]…………………………... 3

Fig 2.1 Categories of memory arrays……………………………………………. 11

Fig. 2.2 Memory array architecture……………………………………………… 12

Fig. 2.3 6T SRAM cell…………………………………………………………… 13

Fig. 2.4 Read operation for 6T SRAM cell……………………………………….. 14

Fig 2.5 Write operation for 6T SRAM cell………………………………………. 15

Fig 2.6 (a) Cross-coupled inverters with noise sources for hold margin…………. 16

Fig 2.6 (b) Butterfly diagram indicating hold margin…………………………….. 16\

Fig 2.7 (a) Cross-coupled inverters with noise sources for read margin…………. 17

Fig 2.7 (b) Butterfly diagram indicating read margin…………………………….. 17

Fig 2.8 (a) Cross-coupled inverters with noise sources for write margin…………. 18

Fig 2.8 (b) Butterfly diagram indicating write margin…………………………….. 18

Fig 3.1 Total power………………………………………………………………... 19

Fig 3.2 Clock gating………………………………………………………………. 20

Fig 3.3 Multi-Vth optimization……………………………………………………. 20

Fig 3.4 Main source of leakage current…………………………………………… 21

Fig 4.1 Schematic of basic 6T CMOS SRAM cell……………………………….. 25

Fig 4.2 Output waveform of 6T SRAM cell during read………………………… 26

Fig 4.3 Output waveform of 6T SRAM cell during write………………………… 27

Fig 4.4 Hold SNM of 6T SARM cell……………………………………………… 27

Fig 4.5 Read SNM of 6T SARM cell……………………………………………… 28

Fig 4.6 Write SNM of 6T SARM cell……………………………………………… 28

Fig 4.7 Schematic of 8T SRAM cell………………………………………………. 29

Fig 4.8 Output waveform of 8T SRAM cell during read…………………………. 30

Fig 4.9 Output waveform of 8T SRAM cell during write………………………… 30

Fig 4.10 Hold SNM of 8T SARM cell…………………………………………….. 31

Fig 4.11 Read SNM of 8T SARM cell…………………………………………….. 31

Fig 4.12 Write SNM of 8T SARM cell…………………………………………….. 31

Fig 4.13 Schematic of 9T SRAM cell…………….……………………………….. 32

Fig 4.14 Output waveform of 9T SRAM cell during read………………………… 33

Fig 4.15 Output waveform of 9T SRAM cell during write………………………… 33

Fig 4.16 Hold SNM of 9T SARM cell……………………………………………… 34

Fig 4.17 Read SNM of 9T SARM cell……………………………………………… 34

Fig 4.18 Write SNM of 9T SARM cell……………………………………………… 34

Fig 4.19 Schematic of proposed 7T SRAM cell……………………………………... 35

Fig 4.20 Output waveform of proposed 7T SRAM cell during read……………….. 36

Fig 4.21 Output waveform of proposed 7T SRAM cell during write……………….. 37

Fig 4.22 Hold SNM of proposed 7T SARM cell…………………………………….. 37

Fig 4.23 Read SNM of proposed 7T SARM cell……………………………………… 38

Fig 4.24 Write SNM of proposed 7T SARM cell………………………………….…. 38

ABBREVIATIONS

RAM Random Access Memory

SRAM Static Random Access Memory

DRAM Dynamic Random Access Memory

ROM Read Only Memory

EPROM Erasable Programmable Read Only Memory

EEPROM Electrically Erasable Programmable Read Only Memory

SDRAM Synchronous Dynamic Random Access Memory

MRAM Magneto resistive RandomAccess Memory

nMOS n-type MOSFET

pMOS p-type MOSFET

SoC System on Chip

USRS Upper Supply Rejection Scheme

LPRS Lower Potential Raising Scheme

WL Word Line

BL Bit line

BLB Bit line bar

SNM Static Noise Margin

ABSTRACT

The need for low power integrated circuits is well known because of their extensive use in the

electronic portable equipments. On chip SRAMs (Static Random Access Memory) determine the

power dissipation of SoCs (System on Chips) in addition to its speed of operation. Hence it is

very important to have low power SRAMs.

From the last more than five decades we are scaling down the size of the CMOS devices

to make the devices portable and compact in size and to get better performance in terms of

access time, power dissipation, delay etc. Thus the demand for low size and low power memory

has increased. Working on low supply voltage and leakage energy has become main concern as

the power consumption can be reduced significantly. As the IC process technology scales, the

oxide thickness and operating voltage continues to decrease. Lower operating voltage will lower

the stability of SRAM cell resulting in lower value of static noise margin.

Power consumption and the speed are the major factors of concern for designing a chip along

with the leakage power. The consumption of power and speed of SRAMs are some important

issues among a number of factors that provides a solution which describes multiple designs that

minimize the consumption of power and this article is also based on that. This article presents the

simulation of 6T, 8T and 9T SRAM cells using low power reduction techniques and develops a

modified model that provides the consumer with a product that costs less and having reduced

power delay product.

We, in our work, have designed and compared SRAM cells under different configurations (6T, 8T & 9T) on the basis of read and write delay, leakage power consumption and stability i.e., noise margins.

We have also proposed a 7T SRAM cell which has better performance metrics with existing memory cells.

All the simulation work had been carried out using Eldo SPICE tool of Mentor Graphics.

CHAPTER 1

INTRODUCTION

1.1 BACKGROUND

The scaling of semiconductor process technologies has been continuing for more than five

decades. Advancements in process technologies are the fuel that has been moving the

semiconductor industry. In response to growing customer demand for enhanced performance and

functionality at reduced cost, a new process technology generation has been introduced by the

semiconductor industry every two to three years during the past four decades.

Both the performance and the complexity of integrated circuits have grown dramatically since

the invention of the integrated circuit in 1959. Microphotographs of the first monolithic

integrated circuit (Fairchild Semiconductor, 1959), the first microprocessor (Intel 4004, 1971),

and a recent microprocessor (Intel Pentium 4, 2002) are shown in Figure 1.1. Technology scaling

reduces the delay of the circuit elements. The density and number of transistors on an IC are

increased by scaling the feature size. By utilizing this growing number of available transistors in

each new process technology, novel circuit techniques and micro-architectures can be employed.

In 1958, Jack Kilby built the first integrated circuit flip-flop with two transistors at Texas

Instruments. In 2008, Intel’s Itanium microprocessor contained more than 2 billion transistors

and a 16 Gb Flash memory contained more than 4 billion transistors. This corresponds to a

compound annual growth rate of 53% over 50 years. No other technology in history has

sustained such a high growth rate lasting for so long.

This incredible growth has come from steady miniaturization of transistors and

improvements in manufacturing processes. Most other fields of engineering involve tradeoffs

between performance, power, and price. However, as transistors become smaller, they also

become faster, dissipate less power, and are cheaper to manufacture. This synergy has not only

revolutionized electronics, but also society at large.

The processing performance once dedicated to secret government supercomputers is now

available in disposable cellular telephones. The memory once needed for an entire company’s

accounting system is now carried by a teenager in her iPod. Improvements in integrated circuits

have enabled space exploration, made automobiles safer and more fuel efficient, revolutionized

the nature of warfare, brought much of mankind’s knowledge to our Web browsers, and made

the world a flatter place.

Transistors can be viewed as electrically controlled switches with a control terminal and two

other terminals that are connected or disconnected depending on the voltage or current applied to

the control. Soon after inventing the point contact transistor, Bell Labs developed the bipolar

junction transistor. Bipolar transistors were more reliable, less noisy, and more power-efficient.

Early integrated circuits primarily used bipolar transistors. Bipolar transistors require a small

current into the control (base) terminal to switch much larger currents between the other two

(emitter and collector) terminals. The quiescent power dissipated by these base currents, drawn

even when the circuit is not switching, limits the maximum number of transistors that can be

integrated onto a single die. By the 1960s, Metal Oxide Semiconductor Field Effect Transistors

(MOSFETs) began to enter production. MOSFETs offer the compelling advantage that they

draw almost zero control current while idle. They come in two flavors: nMOS and pMOS, using

n-type and p-type silicon, respectively. The original idea of field effect transistors dated back to

the German scientist Julius Lilienfield in 1925 [US patent 1,745,175] and a structure closely

resembling the MOSFET was proposed in 1935 by Oskar Heil [British patent 439,457], but

materials problems foiled early attempts to make functioning devices.

In 1963, Frank Wanlass at Fairchild described the first logic gates using MOSFETs

[Wanlass63]. Fairchild’s gates used both nMOS and pMOS transistors, earning the name

Complementary Metal Oxide Semiconductor, or CMOS. The circuits used discrete transistors

but consumed only nanowatts of power, six orders of magnitude less than their bipolar

counterparts.

In 1965, Gordon Moore observed that plotting the number of transistors that can be most

economically manufactured on a chip gives a straight line on a semi logarithmic scale

[Moore65]. At the time, he found transistor count doubling every 18 months. This observation

has been called Moore’s Law and has become a self-fulfilling prophecy. Figure 1.1 shows that

the number of transistors in Intel microprocessors has doubled every 26 months since the

invention of the 4004.

Fig. 1.1 Transistors in Intel microprocessors [Intel10]

1.2 MOTIVATION

Memory is used widely in all electrical systems: mainframes, microcomputers and cellular

phones, etc. The growing demand of portable battery operated systems has made energy efficient

processors a necessity. The performance of these devices is limited by the size, weight and

lifetime of batteries. Serious reliability problems, increased design costs and battery-operated

applications prompted the IC design community to look more aggressively for new approaches

and methodologies that produce more power-efficient designs, which means significant

reductions in power consumption for the same level of performance. Memory circuits form an

integral part of every system design as Dynamic RAMs, Static RAMs, Ferroelectric RAMs,

ROMs or Flash Memories, significantly contributing to the system level power consumption.

Reducing the power dissipation in memories can significantly improve the system power-

efficiency, performance, reliability and overall costs. RAMs have experienced a very rapid

development of low-power low-voltage memory design during recent years due to an increased

demand for notebooks, laptops, hand-held communication devices and IC memory cards.

There are various approaches that are adopted to reduce power dissipation, like design of

circuits with power supply voltage scaling, power gating and drowsy method. Lower power

supply voltage reduces the dynamic power in quadratic fashion and leakage power in exponential

way. But power supply voltage scaling results in reduced noise margin. Many SRAM arrays are

based on minimizing the active capacitance and reducing the swing voltage. In sub-100nm

region leakage currents are mainly due to gate leakage and sub threshold leakage current. High

dielectric constant gate technology decreases the gate leakage current. Forward body biasing

methods and dual Vt techniques are used to reduce sub threshold leakage current. In sub

threshold SRAMs power supply voltage (VDD) is lower than the transistor threshold voltage

(Vt) and the sub threshold leakage current is the operating current.

1.3 LITERATURE REVIEW Zhu and Kursun, 2014 [1] : Conventional Static Random Access Memory (SRAM) cells suffer

from an intrinsic data instability problem due to directly-accessed data storage nodes during a

read operation. Noise margins of memory cells further shrink with increasing variability and

decreasing power supply voltage in scaled CMOS technologies. A seven-transistor (7T), an

eight-transistor (8T), a nine-transistor (9T), and 3 conventional six-transistor (6T) memory

circuits are characterized for layout area, data stability, write voltage margin, data access speed,

active power consumption, idle mode leakage currents, and minimum power supply voltage in

this paper. A comprehensive electrical performance metric is evaluated to compare the memory

cells considering process parameter and supply voltage fluctuations. The triple-threshold-voltage

8T and 9T SRAM cells provide up to 2.5x stronger data stability and 765.9x higher overall

electrical quality as compared to the traditional 6T SRAM cells in a TSMC 65 nm CMOS

technology.

Hussain and Jahinuzzaman, 2012 [2] : In this work, a gated ground SRAM architecture based

on a seven transistor (7T) bit-cell is proposed. The proposed cell shows higher data stability and

yield under varying process, voltage, and temperature (PVT) conditions than the conventional 6T

cell. A single-ended sense amplifier is also presented to read from the proposed cell while a

unique write mechanism is used to reduce the write power to less than half of the write power of

the 6T cell. The proposed cell consumes similar silicon area and leakage power as the 6T cell

when laid out and simulated using a commercial 65-nm CMOS technology. The ground gating is

done by selectively controlling the column virtual ground (CVG) of accessed word in a row. This

significantly reduces the leakage power consumption and enables implementing multiple words

per row, which lowers multiple-bit data upset in the event of radiation induced single event upset

or soft error. In addition, the proposed cell inherently has a 30% larger soft error critical charge,

making its soft error rate (SER) less than the half of that of the 6T cell.

Seevinck, 1987 [3] : The stability of both resistor-load (R-load) and full-CMOS SRAM cells is

investigated analytically as well as by simulation. Explicit analytic expressions for the static-

noise margin (SNM) as a function of device parameters and supply voltage are derived. The

expressions are useful in predicting the effect of parameter changes on the stability as well as in

optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the

results of which are in good agreement with the results predicted by the analytic SNM

expressions. It is further concluded that full-CMOS cells are much more stable than R-load cells

at a low supply voltage.

Mitra, 2014 [4] : Speed, power consumption and area, are some of the most important factors of

concern in modern day memory design. As we move towards Deep Sub-Micron Technologies,

the problems of leakage current, noise and cell stability due to physical parameter variation

becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port

SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay,

read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling

improves the Read Noise Margin and static power dissipation is reduced by using Dual-Vt

transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which

shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE

using 90nm CMOS process.

Athe and Gupta, 2009 [5] : Data retention and leakage current reduction are among the major

area of concern in today’s CMOS technology. In this paper 6T, 8T and 9T SRAM cell have been

compared on the basis of read noise margin (RNM), write noise margin (WNM), read delay,

write delay, data retention voltage (DRV), layout and parasitic capacitance. Corner and statistical

simulation of the noise margin has been carried out to analyze the effect of intrinsic parameter

fluctuations. Both 8T SRAM cell and 9T SRAM cell provides higher read noise margin (around

4 times increase in RNM) as compared to 6T SRAM cell. Although the size of 9T SRAM cell is

around 1.35 times higher than that of the 8T SRAM cell but it provides higher write stability.

Due to single ended bit line sensing the write stability of 8T SRAM cell is greatly affected. The

8T SRAM cell provides a write “1” noise margin which is approximately 3 times smaller than

that of the 9T SRAM cell. The data retention voltage for 8T SRAM cell was found to be

93.64mV while for 9T SRAM cell it was 84.5mV and for 6T SRAM cell it was 252.3mV. Read

delay for 9T SRAM cell is 98.85ps while for 6T SRAM cell it is 72.82ps and for 8T SRAM cell

it is 77.72ps. The higher read delay for 9T SRAM cell is attributed to the fact that dual threshold

voltage technology has been in it in order to reduce the leakage current. Write delay for 9T

SRAM cell was found to be 10ps, 45.47ps for 8T SRAM cell and 8.97ps for 6T SRAM cell. The

simulation has been carried out on 90nm CMOS technology.

Mohammad, 2011 [6]: Leakage power becomes big percentage of total active power especially

for small geometry CMOS technology. It is estimated that 20-50% of total average power during

normal operation lost to leakage power. Leakage power is even more important for mobile

devices where ideal time is long and battery life is important. This paper presents a low leakage

SRAM cell and array architecture targeting high performance, low power embedded memory.

The proposed novel 7-Transistor (7T) based memory provides 50% lower leakage power

compare to 8T cell and 30% faster access time than traditional 6-Transistor (6T) SRAM cell with

increased area of20% compared to the compact 6T cell. All comparisons are based on 28nm

foundry low power process technology.

Cheng and Huang, 2005 [7]: This paper presents a low-power SRAM design with quiet-bitline

architecture by incorporating two major techniques. Firstly, the authors use a one-side driving

scheme for the write operation to prevent the excessive full-swing charging on the bitlines.

Secondly, they use a precharge free pulling scheme for the read operation so as to keep all

bitlines at low voltages at all times. SPICE simulation on a 2K-bit SRAM macro shows that such

architecture can lead to a significant 84.4% power reduction over a self-designed baseline low-

power SRAM macro.

W.Mann et. al., 2010 [8]: Large scale 6T SRAM beyond 65 nm will increasingly rely on assist

methods to overcome the functional limitations associated with scaling and the inherent read

stability/write margin trade off. The primary focus of the circuit assist methods has been

improved read or write margin with less attention given to the implications for performance. In

this work, they introduce margin sensitivity and margin/delay analysis tools for assessing the

functional effectiveness of the bias based assist methods and show the direct implications on

voltage sensitive yield. A margin/delay analysis of bias based circuit assist methods is presented,

highlighting the assist impact on the functional metrics, margin and performance. A means of

categorizing the assist methods is developed to provide a first order understanding of the

underlying mechanisms. The analysis spans four generations of low power technologies to show

the trends and long term effectiveness of the circuit assist techniques in future low power bulk

technologies.

Ming, 2005 [9]: This paper describes a low-power write scheme by adopting charge sharing

technique. By reducing the bitlines voltage swing, the bitlines dynamic power is reduced. The

memory cell's static noise margin (SNM) is discussed to prove it is a feasible scheme. Simulation

results show compare to conventional SRAM, in write cycle this SRAM saves more than 20%

dynamic power.

Itoh, 1995 [10]: Trends in low-power circuit technologies of CMOS RAM chips are reviewed in

terms of three key issues: charging capacitance, operating voltage, and dc current. The discussion

includes a general description of power sources in a RAM chip, and covers both DRAM’s and

SRAM’s. In DRAM’s, successive circuit advancements have produced a power reduction

equivalent to two to three orders of magnitude over the last decade for a fixed memory capacity

chip. Coupled with the low-power advantage of CMOS circuits, two technologies have been the

major contributors to power reduction: lower charging capacitance due to partial activation of

multi-divided arrays that use multi-divisions of data and word lines and lower operating voltage

resulting from external power supply reduction, half-VDD pre-charging, and on-chip voltage

down converting scheme. In SRAM’s, partial activation of a multi-divided word line drastically

reduces the dc current from the data-line load to the selected cell. In addition to advances in the

sense amplifier circuit, an auto power down scheme that uses address transition detection for

word driver and column circuitry further reduces the dc current. It is also shown that to design

ultralow voltage DRAM’s and SRAM’s, the application of sub threshold current reduction

circuits (such as source-gate back biasing) to cell and iterative circuit blocks will be

indispensable in the future.

Aly and Bayoumi, 2014 [11] : On-chip cache consumes a large percentage of the whole chip

area and expected to increase in advanced technologies. Charging/discharging large bit lines

capacitance represents a large portion of power consumption during a write operation. We

propose a novel write mechanism which depends only on one of the two bit lines to perform a

write operation. Therefore, the proposed 7T SRAM cell reduces the activity factor of discharging

the bit line pair to perform a write operation. Experimental results using HSPICE simulation

shows that the write power saving is at least 49%. Both read delay and static noise margin are

maintained after carefully sizing the cell transistors.

Karimi and Alimoradi, 2011 [12]: Rapid growth in semiconductor technology has led to

shrinking of feature sizes of transistors using deep submicron (DSM) process. As MOS

transistors enter deep submicron sizes, undesirable consequences regarding power consumption

arise. Until recently, dynamic or switching power component dominated the total power

dissipated by an IC. Voltage scaling is perhaps the most effective method to decrease dynamic

power due to the square law dependency of digital circuit active power on the supply voltage. As

a result, this demands a reduction of threshold voltage to maintain performance. Low threshold

voltage results in an exponential increase in the sub-threshold leakage current. On the other hand

as technology scales down, shorter channel lengths result in increased sub-threshold leakage

current through an off transistor. Therefore, in DSM process static or leakage power becomes a

considerable proportion of the total power dissipation. For these reasons, static power

consumption, i.e. leakage power dissipation, has become a significant portion of total power

consumption for current and future silicon technologies.

1.4 OBJECTIVE To design low power SRAM memory cells of different configurations like 6T, 8T and 9T (where

T represents the transistor) and compare their performance parameters like-

- Read and write delay

- Leakage power consumption

- Static noise margins (during hold, read and write)

Lowering of supply and threshold voltages to satisfy enhanced Performance requirements with a

limited power Consumption budget causes significant degradation in SRAM data stability with

the scaling of CMOS technology. Noise margins of memory cells further shrink with increasing

process parameter and supply voltage fluctuations. So the pull-down transistors in the cross-

coupled inverters are typically strengthened as compared to the bitline access transistors for

enhancing the read data stability in conventional 6T SRAM cells. An alternative way to enhance

data stability is to modify the structure of the memory cell transistor network.

For low power operation power wastage during bitlines charging and discharging can be

minimized by using lesser number of bitlines. To achieve this a 7T SRAM cell is proposed using

single bitline.

CHAPTER 2

THEORATICAL BACKGROUND

2.1 INTRODUCTION

Memory arrays often account for the majority of transistors in a CMOS system-on-chip. Arrays

may be divided into categories as shown in Figure 2.1.

Fig 2.1 Categories of memory arrays Random access memory is accessed with an address and has a latency independent of the

address. In contrast, serial access memories are accessed sequentially so no address is necessary.

Content addressable memories determine which address(es) contain data that matches a specified

key.

Random access memory is commonly classified as read-only memory (ROM) or read/write

memory (confusingly called RAM). Even the term ROM is misleading because many ROMs can

be written as well. A more useful classification is volatile vs. nonvolatile memory. Volatile

memory retains its data as long as power is applied, while nonvolatile memory will hold data

indefinitely. RAM is synonymous with volatile memory, while ROM is synonymous with

nonvolatile memory.

Like sequencing elements, the memory cells used in volatile memories can further be

divided into static structures and dynamic structures. Static cells use some form of feedback to

maintain their state, while dynamic cells use charge stored on a floating capacitor through an

access transistor. Static RAMs (SRAMs) are faster and less troublesome, but require more area

per bit than their dynamic counterparts (DRAMs).

A memory array contains 2n words of 2m bits each. Each bit is stored in a memory cell.

Figure 2.2 shows the memory array architecture.

The row decoder uses the address to activate one of the rows by asserting the word line. During a

read operation, the cells on this word line drive the bit lines, which may have been conditioned to

a known value in advance of the memory access.

The column circuitry may contain amplifiers or buffers to sense the data. A typical memory array

may have thousands or millions of words of only 8–64 bits each, which would lead to a tall,

skinny layout that is hard to fit in the chip floor plan and slow because of the long vertical wires.

Therefore, the array is often folded into fewer rows of more columns. After folding, each row of

the memory contains 2k words, so the array is physically organized as 2 n–k rows of 2 m+k

columns or bits. Figure 2.2 shows a two-way fold (k = 1) with eight rows and eight columns. The

column decoder controls a multiplexer in the column circuitry to select 2m bits from the row as

the data to access. Larger memories are generally built from multiple smaller sub arrays so that

the word lines and bit lines remain reasonably short, fast, and low in power dissipation.

Fig. 2.2 Memory array architecture

2.2 SRAM Static RAMs use a memory cell with internal feedback that retains its value as long as power is

applied. It has the following attractive properties:

- Denser than flip-flops

- Compatible with standard CMOS processes

- Faster than DRAM

- Easier to use than DRAM

For these reasons, SRAMs are widely used in applications from caches to register files to tables

to scratchpad buffers. The SRAM consists of an array of memory cells along with the row and

column circuitry. This section begins by examining the design and operation of each of these

components. It then considers important special cases of SRAMs, including multiported register

files, large SRAMs and subthreshold SRAMs.

2.2.1 SRAM CELL A SRAM cell needs to be able to read and write data and to hold the data as long as the power is

applied. An ordinary flip-flop could accomplish this requirement, but the size is quite large.

Figure 2.3 shows a standard 6-transistor (6T) SRAM cell that can be an order of magnitude

smaller than a flip-flop. The 6T cell achieves its compactness at the expense of more complex

peripheral circuitry for reading and writing the cells [5].

Fig. 2.3 6T SRAM cell

This is a good trade-off in large RAM arrays where the memory cells dominate the area. The

small cell size also offers shorter wires and hence lower dynamic power consumption.

The 6T SRAM cell contains a pair of weak cross-coupled inverters holding the state and a pair of

access transistors to read or write the state. The positive feedback corrects disturbances caused

by leakage or noise. The cell is written by driving the desired value and its complement onto the

bitlines, bit and bit_b, then raising the wordline, word. The new data overpowers the cross-

coupled inverters. It is read by precharging the two bitlines high, then allowing them to float.

When word is raised, bit or bit_b pulls down, indicating the data value. The central challenges in

SRAM design are minimizing its size and ensuring that the circuitry holding the state is weak

enough to be overpowered during a write, yet strong enough not to be disturbed during a read.

2.2.2 READ OPERATION Figure 12.4 shows a SRAM cell being read. The bitlines are both initially floating high. Without

loss of generality, assume Q is initially 0 and thus Q_b is initially 1. Q_b and bit_b both should

remain 1. When the wordline is raised, bit should be pulled down through driver and access

transistors D1 and A1. At the same time bit is being pulled down, node Q tends to rise. Q is held

low by D1, but raised by current flowing in from A1. Hence, the driver D1 must be stronger than

the access transistor A1. Specifically, the transistors must be ratioed such that node Q remains

below the switching threshold of the P2/D2 inverter. This constraint is called read stability.

Waveforms for the read operation are shown in Figure 12.4(b) as a 0 is read onto bit. Observe

that Q momentarily rises, but does not glitch badly enough to flip the cell.

Fig. 2.4 Read operation for 6T SRAM cell

2.2.3 WRITE OPERATION Figure 2.5 shows the SRAM cell being written. Again, assume Q is initially 0 and that we wish

to write a 1 into the cell. bit is precharged high and left floating. bit_b is pulled low by a write

driver. We know on account of the read stability constraint that bit will be unable to force Q high

through A1. Hence, the cell must be written by forcing Q_b low through A2. P2 opposes this

operation; thus, P2 must be weaker than A2 so that Q_b can be pulled low enough. This

constraint is called writability. Once Q_b falls low, D1 turns OFF and P1 turns ON, pulling Q

high as desired.

Fig 2.5 Write operation for 6T SRAM cell

2.2.4 CELL STABILITY To ensure both read stability and writability, the transistors must satisfy ratio constraints. The

nMOS pulldown transistor in the cross-coupled inverters must be strongest. The access

transistors are of intermediate strength, and the pMOS pull up transistors must be weak. To

achieve good layout density, all of the transistors must be relatively small. For example, the pull

downs could be 8/2 λ, the access transistors 4/2, and the pull ups 3/3. The SRAM cells must

operate correctly at all voltages and temperatures despite process variation.

The stability and writability of the cell are quantified by the hold margin, the read margin, and

the write margin, which are determined by the static noise margin of the cell in its various modes

of operation. A cell should have two stable states during hold and read operation, and only one

stable state during write.

2.3 PERFORMANCE PARAMETERS OF SRAM Read delay: Read delay is the delay involved in allowing the bit lines to discharge by about 10%

of the peak value or the delay between the application of the WL signal and the response time of

the sense amplifier.

Write delays: It is the delay between the applications of the word line WL signal and the time at

which the data is actually written.

Leakage power: The power consumed by a device not related to state changes (also referred to

as static power). Leakage power is actually consumed when a device is both static and switching,

but generally the main concern with leakage power is when the device is in its inactive state, as

all the power consumed in this state is considered “wasted” power.

Static Noise Margin: The static noise margin (SNM) measures how much noise can be applied

to the inputs of the two cross-coupled inverters before a stable state is lost (during hold or read)

or a second stable state is created (during write) [3].

2.4 CALCULATION OF STATIC NOISE MARGIN Hold Margin: Figure 2.6 (a) shows the test circuit for determining the hold margin (i.e., the

static noise margin while the cell is holding its state and being neither read nor written. A noise

source Vn is applied to each of the cross-coupled inverters. The access transistors are OFF and do

not affect the circuit behavior.

Fig2.6 (a) Cross-coupled inverters with noise (b) Butterfly diagram indicating hold margin sources for hold margin The static noise margin can be determined graphically from a butterfly diagram shown in Figure

2.6 (b). The plot is generated by setting Vn = 0 and plotting V2 against V1 (curve I) and V1

against V2 (curve II). If the inverters are identical, the DC transfer curves are mirrored across the

line of V1 = V2. The butterfly plot shows two stable states (with one output low and the other

high) and one meta stable state (with V1 = V2).

The static noise margin is determined by the length of the side of the largest square that can be

inscribed between the curves. If the inverters are identical, the butterfly diagram is symmetric, so

the high and low static noise margins are equal. If the inverters are not identical, the static noise

margin is the lesser of the two cases.

Read margin: When the cell is being read, the bitlines are initially precharged and the access

transistor tends to pull the low node up. This distorts the voltage transfer characteristics. The

static noise margin under these circumstances is called the read margin and is smaller than the

hold margin. It can be obtained by performing the same simulation on the circuit in Figure 2.7(a)

with the bitlines tied to VDD. Figure 2.7 (b) shows the results.

Fig2.7 (a) Cross-coupled inverters with noise (b) Butterfly diagram indicating read margin sources for read margin The read margin depends on the relative strength of the pulldown transistor D to the access

transistor A. The ratio of these two transistors’ widths is called the beta ratio or cell ratio.

Write margin: When the cell is being written, the access transistor A must overpower the pull

up P to create a single stable state. The write margin is determined by a similar simulation as

read margin, with one access transistor pulling to 0 and the other to 1. If |Vn| is too large, a

second stable state will exist, preventing the function of writes. Figure 2.8 (b) shows the

characteristics while bit is held at 0. The write margin is the size of the smallest square inscribed

between the two curves.

Fig2.8 (a) Cross-coupled inverters with noise (b) Butterfly diagram indicating write margin sources for write margin

CHAPTER 3

POWER CONSIDERATION IN SRAM CELL

Power consumption has two aspects:

Dynamic power – The power that is consumed by a device when it is actively switching from

one state to another. Dynamic power consists of switching power, consumed while charging and

discharging the loads on a device, and internal power (also referred to as short circuit power),

consumed internal to the device while it is changing state

Figure 3.1: Total power

Leakage power – The power consumed by a device not related to state changes (also referred to

as static power). Leakage power is actually consumed when a device is both static and switching,

but generally the main concern with leakage power is when the device is in its inactive state, as

all the power consumed in this state is considered “wasted” power.

Various techniques have been developed to reduce both dynamic and leakage power.

3.1 LOW POWER TECHNIQUES IN SRAM MEMORY: 3.1.1 Clock gating – The disconnecting of the clock from a device it drives when the data going

into the device is not changing. This technique is used to minimize dynamic power [6].

Fig. 3.2 Clock gating

3.1.2 Multi-Vth optimization – The replacement of faster Low-Vth cells, which consume more

leakage power, with slower High-Vth cells, which consume less leakage power. Since the High-

Vth cells are slower, this swapping only occurs on timing paths that have positive slack and thus

can be allowed to slow down( Fig. 3.3 [12]).

Figure: 3.3 Multi Vth optimization

As technologies have shrunk, leakage power consumption has grown exponentially, thus

requiring more aggressive power reduction techniques to be used. Similarly, clock frequency

increases have caused dynamic power consumption of the devices to outstrip the capacity of the

power networks that supply them, and this becomes especially acute when high power

consumption occurs in very small geometries, as this is a power density issue as well as a power

consumption issue.

3.1.3Multi supply voltage - Multiple voltage rails (multi-Vdd) can be supplied to a design to

impact power and performance. A higher voltage yields a faster the circuit, but with higher the

dynamic power. In many designs, only discrete portions of the design need to run at high speed.

Other portions may only operate at lower speeds, and thus require lower voltages (and therefore

consume less power [12]).

3.2 DOMINANT LEAKAGE MECHANISM IN CMOS TRANSISTOR: There are four main source of leakage current in a CMOS transistor as shown in figure:

1. Reverse biased junction leakage (Irev)

2. Gate induced drain leakage (IGIDL)

3. Gate direct tunneling leakage (IG)

4. Subthreshold leakage (Isub)

Figure 3.4 Main source of leakage current

3.2.1 Junction leakage: The junction leakage occurs from the source or drain to the substrate

through the reverse biased diodes when a transistor is OFF. A reverse-biased P-N junction

leakage has two main components: one in minority carrier diffusion/drift near the edge of the

depletion region, the other is due the electron-hole pair generation in the depletion region of the

reverse biased junction. For example in the case of inverter with a low input voltage, the NMOS

is OFF, PMOS is ON and the output voltage is high. Subsequently the drain to substrate voltage

of the OFF NMOS transistor is equal to the supply voltage. This result in a leakage current from

the drain to the substrate through the reverse-biased diode. The magnitude of the diode leakage

current depends on the area of the drain diffusion and the leakage current density which is in turn

determined by the doping concentration.

If both the n and p regions are heavily doped, band to band tunneling (BTBT) dominates the p-n

junction leakage. Junction leakage has a very high dependency on the temperature. However

junction reverse leakage components from the both source drain diodes and the well diodes are

generally negligible with respect to the other three leakage components.

3.2.2 Gate Induced Drain Leakage: The gate induced drain leakage (GIDL) is caused by high

field effect in the drain junction of MOS transistors. For a NMOS transistor with grounded gate

and drain potential at VDD, a significant band bending in the drain allow electron-hole pair

generation through avalanche multiplication and the band to band tunneling. A deep depletion

condition is created since the holes are rapidly swept out to the substrate. At the same time

electrons are collected by the drain, resulting in GIDL current. This leakage mechanism is made

work by high drain to body voltage and high drain to gate voltage.

Transistor scaling has led to the increasingly steep halo implants, where the substrate doping at

the junction interface is increased, while the channel doping is low. This is done mainly to

control punch-through and drain-induced barrier lowering while having a low impact on the

carrier mobility in the channel. The resulting steep doping profile at the drain edge increases

band to band tunneling current there, particularly a VDB is increased. Thinner oxide and higher

supply voltage increases GIDL current.

3.2.3 Gate Direct Tunneling Leakage: With scaling of the channel length, maintaining good

transistor aspect ratio by the comparable scaling of the gate oxide thickness, junction depth and

depletion depth are important for ideal MOS transistor behavior. Unfortunately with the

technology scaling, maintaining good transistor aspect ratio has been a challenge. In other words,

reduction of the vertical dimensions has been harder than that of horizontal dimensions with the

silicon oxide gate thickness approaching scaling limits there is now a rapid increase in gate direct

tunneling leakage current.

Due to quantum mechanical and poly silicon gate depletion effects, both the gate charge and

inversion layer charge will be located at the finite distance from the oxide channel interface with

the charge location being a strong function of bias applied to the gate. The location of the

inversion layer in the silicon substrate for a transistor with a typical bias when quantum

mechanical effects are taken into account is 1 nm from the oxide channel interface. This increase

the effective oxide thickness by 0.3 nm. Taking charge spread on the both sides of the interface

along with poly depletion charge the 1nm oxide tunneling limit into an effective oxide thickness

of 1.7 nm.

To compact this limit researchers have been exploring several alternatives including the use high

permittivity gate dielectric, metal gate, novel transistor structure and circuit based techniques.

The use of high permittivity gate dielectric will result in thicker and easier to fabricate dielectric

for iso- gate oxide capacitance with potential for significant reduction in gate leakage.

Identification of a proper high permittivity dielectric material that has good interface state with

silicon along with limited gate leakage is in progress. However it has also been shown that use of

high permittivity gate dielectric has limited value. In addition novel transistor structure such as

self aligned double gate. FinFET and tri-gate MOS transistors that promise better aspect ratio are

being explored.

3.2.4 Subthreshold Leakage: The subthreshold leakage is current flowing from drain to source

when a transistor operated in weak inversion region. Unlike the strong inversion region in which

the drift-current dominates, the subthreshold conduction is due to the diffusion current of the

minority carriers in the channel for a MOS device. For instance, in case of an inverter with a low

input voltage, the NMOS is turned off and the output voltage is high. In this case, although VGS

is 0V, there is still a current flowing in the channel of the OFF NMOS transistor due to the VDD

potential of the VDS. The magnitude of the sub threshold current is a function of temperature,

supply voltage, device size and the process parameter out of which the threshold voltage plays a

dominant role.

For the current CMOS technologies, the sub threshold leakage current, ISUB is much larger than

the other leakage current components. This is much larger than the other leakage current

퐼 = 푊퐿 휇푉 퐶푒 1− 푒

components. This is mainly because VT is lower in modern device Equation describes sub

threshold current in terms of other device parameters

Here W and L denotes the transistor width and length, µ denotes the carrier mobility

푉 =

Vth is the thermal voltage.

3.3 POWER REDUCTION IN SRAM CELL: To reduce the power consumption in SRAMs all contributors to the total power must be targeted.

The most efficient techniques used in recent memories are:-

1. Capacitance reduction of word-lines and the number of cells connected to them, data lines,1/0

lines and decoders.

2. DC current reduction by using new pulse operation techniques for word-lines, periphery

circuits and sense amplifiers.

3. AC current reduction by using new decoding techniques (i.e. multi-stage static CMOS

decoding)

4. Operating voltage reduction.

5. Leakage current reduction (in active and standby mode) by utilizing multiple threshold voltage

(MT-CMOS) or variable threshold voltage technologies (VT-CMOS).

CHAPTER 4

SIMULATION OF SRAM CELLS

4.1 SOFTWARE TOOL

All the simulations of 6T, 8T and 9T SRAM cells have been carried out on 65nm at Eldo SPICE

tool of Mentor graphics.

The Eldo™ analog simulator is the core component of a comprehensive suite of analog and

mixed-signal simulation tools. Eldo offers a unique partitioning scheme allowing the use of

different algorithms on differing portions of design. It allows the user a flexible control of

simulation accuracy using a wide range of device model libraries, and gives a high accuracy

yield in combination with high speed and high performance.

4.2 SCHEMATIC AND WORKING OF BASIC 6T CMOS SRAM CELL Figure 3.1 shows the schematic of basic cell structure it consists of six transistors where

NMOS_5 and NMOS_6 is called the access transistor and NMOS_1 and NMOS_2 is called the

driver transistor and PMOS_1 and PMOS_2 called the load transistor. Vdd supply is 1.2-volt

. Fig. 4.1 Schematic of basic 6T CMOS SRAM Cell

Word line is applied to the gates of both the access transistors. Substrate of P channel transistor

is connected to the Vdd supply and substrate of N channel is connected to the ground terminal.

To understand the working of basic cell we have to assume the previous state of cell. Basically

by this circuit we can do only read operation. By taking the input voltage we can store the value

SRAM cell. First we applied the input voltage to the inverter one. Then we got the output of

inverter one that is input of the second inverter. After the pass transistor gets turn on by the word

selection .The value is passing through the access transistor to the bit line and bit line bar. From

the bit line and bit line bar, finally we got output. In this way the read operation gets performed.

4.2.1 OUTPUT WAVEFORMS OF 6T SRAM CELL

READ WAVEFORM

Fig 4.2 output waveform of 6T SRAM cell during read

WRITE WAVEFORM

Fig 4.3 output waveform of 6T SRAM cell during write

STATIC NOISE MARGINS

Fig 4.4 Hold SNM of 6T SRAM cell

Fig 4.5 Read SNM of 6T SRAM cell Fig 4.6 Write SNM of 6T SRAM cell

Current industry standard SRAM cells are composed of six transistors (6T) as shown in Fig.4.1.

In a conventional 6T SRAM cell, the data storage nodes (Node 1 and Node 2 ) are directly

accessed through the bitline access transistors ( and ) during a read operation. The storage nodes

are disturbed due to voltage division between cross-coupled inverters and bitline access

transistors while reading. The data is most vulnerable to external noise during a read operation

due to the intrinsic disturbance produced by a standard 6T SRAM cell (destructive read) [3].

The pull-down transistors in the cross-coupled inverters are typically strengthened as compared

to the bitline access transistors for enhancing the read data stability in conventional 6T SRAM

cells. Various data stability enhancement techniques based on dynamically adjusting the

strengths of the access and pull-down transistors with specialized peripheral circuitry has been

explored. The pros and cons of different read and write assist circuitry are analyzed and

qualitatively compared [1]. An alternative way to enhance data stability is to modify the structure

of the memory cell transistor network. The data storage nodes are isolated from the bitlines for

enhanced data stability during read operations with the eight-transistor (8T) and nine-transistor

(9T) SRAM cells.

4.3 SCHEMATIC AND WORKING OF 8T CMOS SRAM CELL To address the read destructive problem, the read and write operations are separated by adding

transistor stack to the conventional 6T SRAM cell, thus it has the area penalty but operates

efficiently than the 6T SRAM cell at lower VDD. The schematic of the 8T SRAM cell with

transistors sized for a 65-nm CMOS technology is shown below

Fig. 4.7 Schematic of 8T CMOS SRAM Cell

READ & WRITE OPERATION OF 8T SRAM CELL

The disturbance of bit lines during read operation is the primary source of instability problem in

SRAM operation. The stability in 8T SRAM cell can be enhanced by isolating the read port from

the write bit lines. The 8T SRAM cell composed of conventional 6T SRAM cell for writing

operation and a transistor stack, which can be used for read operation. The read and write

operations are controlled by separate signals Write Word Line (WWL) and Read Word Line

(RWL). During the read operation Read Bit Line (RBL) is pre charged to VDD and WWL is

maintained at GND. Depends on the value stored in cross coupled inverters RBL, discharges (or)

maintained at VDD. If RBL discharges, it can be treated as the stored bit is „1 , otherwise it is

„0 . The storage nodes are completely isolated from the write bit lines, which can increases the

stability of the SRAM cell [3]. During the write operation WBL and WBLB lines are precharged

to predetermined values. Then, asserting the write word line WWL and nodes attain the

corresponding values from the bit lines. It uses the two additional Word Lines to perform read

and write operations, when compared with 6T SRAM cell, which could increase the metal

density, wire delay and dynamic power consumption and leakage power.

4.3.1 OUTPUT WAVEFORMS OF 8T SRAM CELL READ WAVEFORM

Fig 4.8 output waveform of 8T SRAM cell during read

WRITE WAVEFORM

Fig 4.9 output waveform of 8T SRAM cell during write

STATIC NOISE MARGINS

Fig 4.10 Hold SNM of 8T SRAM cell

Fig 4.11 Read SNM of 8T SRAM cell Fig 4.12 Write SNM of 8T SRAM cell

4.4 SCHEMATIC AND WORKING OF 9T CMOS SRAM CELL To address the read destructive problem, the read and write operations are separated by adding

transistor stack to the conventional 6T SRAM cell, thus it has the area penalty but operates

efficiently than the 6T SRAM cell at lower VDD. The schematic of the 8T SRAM cell with

transistors sized for a 65-nm CMOS technology is shown below

Fig. 4.13 Schematic of 9T SRAM Cell

READ AND WRITE OPERATION OF 9T SRAM CELL

The upper sub-circuit of the 9T memory cell is essentially a conventional 6T SRAM cell. The

write operation is identical with the conventional 6T SRAM cell. For write operation write signal

WWL is set to 1 and read signal RWL is made 0.

The lower sub-circuit of the 9T memory cell is a differential read port. Prior to a read operation,

both bitlines are precharged to VDD . To start a read operation, the read signal RWL transitions

from 0 to 1 and write signal WWL goes to low. One of the bitlines is discharged depending on

the data that is stored in the cell.

4.4.1 OUTPUT WAVEFORMS OF 9T SRAM CELL READ WAVEFORM

Fig 4.14 output waveform of 9T SRAM cell during read

WRITE WAVEFORM

Fig 4.15 output waveform of 9T SRAM cell during write

STATIC NOISE MARGINS

Fig 4.16 Hold SNM of 9T SRAM cell

Fig 4.17 Read SNM of 9T SRAM cell Fig 4.18 Write SNM of 9T SRAM cell

4.5 SCHEMATIC AND WORKING OF PROPOSED 7T SRAM CELL Main objective of proposing this new 7T SRAM cell is to have good Read Stability and static

Noise Margins (SNMs). Proposed 7T SRAM cell is shown in fig.4.14. This new SRAM cell is

made up of seven transistors, uses single bit-line (BL), a word line (WL), and a read line (RL).

Fig. 4.19 Schematic of proposed 7T SRAM Cell

Since 7TSRAM cell uses only one bit line, power required for charging and discharging of one

more bitline will be reduced. Hence usage of only one bit line reduces power required to charge

and discharge the bit lines approximately to half, because only one bit line is charged during read

operation instead of two. The bit line is charged during the write operation about half of the time

instead of every time when a write operation is required, here we are assuming equal probability

of writing 0 and 1. The proposed 7T SRAM cell uses two transistors N4 and N5 with read-line

(RL) for read operation.

READ AND WRITE OPERATION OF PROPOSED 7T SRAM CELL

While writing, the data need to be written will be loaded on bit-line (BL) and then word-line

(WL) will be activated. Strong access transistor N3 allows bit line to overpower the cell, so that

required data will be written into the cell. To write ‘1’ into the cell, the bit-line (BL) is charged

to VDD. If the data need to be written is ‘0’, bit-line should be at logic low, and then word-line

(WL) should be pulled to VDD. In write mode read-line (RL) will be inactive (i.e. at logic ‘0’).

To read data from the cell, initially bit line (BL) is being pre-charged to VDD. After pre-

charging the bit line read line (RL) is activated. Depending upon whether the bit line (BL)

discharges or holds the held charge, data stored in the 7T SRAM cell can be decided. If BL

discharges after pulling the read line to VDD, it indicates 7T SRAM cell is storing ‘0’ in it. If bit

line holds the held charge then the data stored is ‘1’. In read mode (WL) is inactive (i.e. at logic

‘0’).

4.5.1 OUTPUT WAVEFORMS OF PROPOSED 7T SRAM CELL READ WAVEFORM

Fig 4.20 output waveform of proposed 7T SRAM cell during read

Fig 4.21 output waveform of proposed 7T SRAM cell during write

STATIC NOISE MARGINS

Fig 4.22 Hold SNM of proposed 7T SRAM cell

Fig 4.23 Read SNM of proposed 7T SRAM cell Fig 4.24 Write SNM of proposed 7T SRAM cell

4.6 RESULTS

TABLE 1

SRAM CELL READ DELAY (ns)

WRITE DELAY (ns)

LEAKAGE POWER CONSUMPTION (nW)

6T

41.5 03 2.892

8T

45.0 12 5.808

9T

46.5 20 7.260

New 7T

41.5 01 2.41

TABLE 2

SRAM CELL HOLD SNM (mV) READ SNM (mV) WRITE SNM (mV) 6T

440 223.5 430

8T

440 440 430

9T

440 320 410

New 7T

440 410 290

CHAPTER 5

CONCLUSION AND FUTURE SCOPE

5.1 CONCLUSION

The simulation of 6T, 8T and 9T SRAM cells has been carried out successfully with the help of

Eldo SPICE tool of Mentor Graphics on 65nm technology at 25 degree celsius. The compared

parameters were read delay, write delay, leakage power consumption and static noise margin

(during hold, read and write).

After the analysis we see that by increasing the numbers of transistors read and write delays and

leakage power consumption is increased as the cell area increases. This shows that the 6T SRAM

cell is better but based on noise margin it shows poor data stability. 8T and 9T has better data

stability because they provide dual port operation that is different read and write stack for read

and write operation respectively.

The proposed 7T SRAM cell gives the low power and better stability as the structure is such

modified that it uses the single bitline for charging and discharging and providing dual port

operation also. To increase their reliability of SRAM cell, the lifetime of battery is a prime

concerned at the cost of speed. Reduction in the power consumption reduces the problems

associated with high temperature and also provides an additional benefit in terms of the extended

life of the battery.

5.2 FUTURE SCOPE To perform the write operation in the SRAM cell to flip the data value, nearly full voltage swings

is required on the bit line. This full voltage swing on the highly capacitive bit lines will consume

a greater amount of power according to law of CV2f. Thus voltage swing reduction is an

effective way to decrease the power dissipation. the future course of action involves effective

reduction of leakage in an SRAM cell. It is proposed here that appropriate leakage reduction

techniques would be developed with an emphasis on the reduction of gate leakage. Leakage

reduction in SRAM is also possible using self controllable switch either at the upper end of the

cell to reduce supply voltage (USR scheme) or at the lower end of the cell to raise the potential

of the ground node (LPR scheme). This method would also be tested for its efficacy when this

work is advanced.

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[28] M. A. Khan, A. Q. Ansari, “n-Bit Multiple Read and Write FIFO Memory Model for

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(WICT 2012), Mumbai, pp. 1322 – 1327, Dec. 2011.

[29] A. Q. Ansari, Neeraj Gupta, “MIPS-NF Instructions for Fourth Generation Processor,” Proc.

2nd IEEE Conf. on Comp., Control, and Comm., Pakistan, pp. 01 – 05, February 2009.

[30] Anwar Jamil, A. Q. Ansari, and Ranjit Biswas, “A Proposal for a New Generation of

Computers,” Proc. International Conference on Fuzzy Theory and Technology, U.S.A., pp.

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[31] A. Q. Ansari, “Development of a Switch-Level Simulator for Ternary Logic Circuits,” Proc.

National Conference on Technology Convergence for Information, Communication, and

Entertainment (NICE’2001), IETE, Cochin, India, pp.141-144, Feb. 23 –24, 2001.

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[33] M Ayoub Khan, A Q Ansari, “A Journey from Computer Networks to Networks-on-Chip”,

IEEE Beacon, Vol. 31, No. 1, pp. 71-77, March 2012.

[34] M Ayoub Khan, A Q Ansari, “High-Speed Dynamic TDMA Arbiter for Inter-Layer Communications in 3-D Network-on-Chip”, Journal of High Speed Networks, IOS Press, Netherlands, Vol. 18, Issue 3, pp.141-155, 2012.

[35] M. A. Khan, A. Q. Ansari, “Modelling and Simulation of 128-Bit Crossbar switch for Network-on-Chip”, International Journal of VLSI and Communications System, AIRCC, Australia, Vol. 2, No. 3, pp. 213 – 222, September 2011.

[36] M. A. Khan, A. Q. Ansari, “A Quadrant-XYZ Routing Algorithm for 3-D Asymmetric Torus Network-on-Chip,” International Journal of ACM Jordan, Vol. 2, No. 2, pp. 11 – 18, June 2011.

[37] A. Q. Ansari, “Hierarchical Fuzzy Control for Industrial Automation”, Scholar’s Press, Germany, 2013. ISBN: 978-3-639-51592, 2013.

[38] M. A. Khan, A. Q. Ansari, Ajith Abraham, eds. “International Journal of Embedded Systems,” Special issue on Emerging Trends in On-Chip Communications. Publisher: InderScience, Switzerland, Vol. 5, Nos. 1 and 2, 2013.

[39] M. A. Khan, A. Q. Ansari, “Handbook of Research on Industrial Informatics and Manufacturing Intelligence: Innovations and Solutions." Publisher: IGI Global, U.S.A., 2012.

[40] M Ayoub Khan, A. Q. Ansari, “Efficient Topologies for 3-D Network-on-Chip”, Multicore Technology Architecture, Reconfiguration, and Modelling, Chapter-12, pp. 335-353, M. Y. Qadri and S. J. Sangwine(Editors), Publisher: CRC Press (Taylor and Francis) U.K., 2013.

[41] A. Q. Ansari, M. A. Khan, "Fundamentals of Industrial Informatics and Communication Technologies," Handbook of Research on Industrial Informatics and Manufacturing Intelligence: Innovations and Solutions. Chapter-1, pp. 1-19, M. A. Khan and A. Q. Ansari(Editors), IGI Global, USA, March 2012.

[42] M. A. Khan, A. Q. Ansari, “An Efficient Tree-Based Topology for Network-on-Chip,” Proc. World Congress on Information and Communication Technology (WICT 2012), Mumbai, pp. 1316 – 1321, Dec. 2011.

[43] M. A. Khan, A. Q. Ansari, “Design of 8-Bit Programmable Crossbar Switch for Network-on-Chip Router,” Int. Workshop on VLSI, Chennai, Springer-Verlag Berlin Heidelberg, CCIS 197, Lecture Notes in Trends in Network and Communication, D.C. Wyld et al. (Eds.), pp. 526 – 535, July 2011.

[44] M. A. Khan, A. Q. Ansari, “From Computer Networks to Network-on-Chip”, Proc. International Conference on Nanoscience, Engineering, and Advanced Computing, India, pp. 28-33, 8 - 10 July, 2011.

[45] M. A. Khan, A. Q. Ansari, “Quadrant-Based XYZ Dimension Order Routing Algorithm for 3-D Asymmetric Torus Routing Chip,” Proc. International Conference on Emerging Trends in Networks and Computer Communications, (ETNCC 2011), Udaipur, India, pp. 121 – 124, April 22 – 24, 2011.

[46] M. A. Khan, A. Q. Ansari, “Low-Power Architecture for dTDMA Transmitter and Receiver for Vertical BUS”, Proc. IEEE International Conference on Emerging Trends in Networks and Computer Communications, April 22-24, 2011. Udaipur, India pp. 350 – 354.

[47] M. A. Khan, A. Q. Ansari, “128-Bit High-Speed FIFO Design for Network-on-Chip,” Proc. IEEE International Conference on Emerging Trends in Computing (ICETC 2011), Coimbatore, pp. 116 – 121, March 17 - 18, 2011.

[48] M. A. Khan, A Q Ansari, “A Review of Hyper-Torus based Topologies for Network-on-Chip”, Proc. IEEE International Conference on Emerging Trends in Computing (ICETC 2011), Coimbatore, pp. 109 – 115, March 17 - 18, 2011.

[49] A. Q. Ansari, Neeraj Gupta, “MIPS-NF Instructions for Fourth Generation Processor,” Proc. 2nd IEEE Conf. on Comp., Control, and Comm., Pakistan, pp. 01 – 05, February 2009.

[50] Anwar Jamil, A. Q. Ansari, and Ranjit Biswas, “A Proposal for a New Generation of Computers,” Proc. International Conference on Fuzzy Theory and Technology, U.S.A., pp. 97 – 100, March 2002.

[51] A. Q. Ansari, Mohammad Ayoub Khan, Mohammad Rashid Ansari, “Advancement in Energy Efficient Routing Algorithms for 3-D Network-on-Chip Architecture,” Proc. National Conference on Emerging Trends and Electrical and Electronics Engg. (ETEEE-2015), New Delhi, pp. 104 – 110, 2-3 February, 2015.

[52] A. Q. Ansari, Javed Akhtar Ansari, “Design and Comparison of Single Bit SRAM Cell under Different Configurations,” Proc. National Conference on Emerging Trends and Electrical and Electronics Engg. (ETEEE-2015), New Delhi, pp. 73 – 78, 2-3 February, 2015.

[53] A. Q. Ansari, “Development of a Switch-Level Simulator for Ternary Logic Circuits,” Proc. National Conference on Technology Convergence for Information, Communication, and Entertainment (NICE’2001), IETE, Cochin, India, pp.141-144, February 23 –24, 2001.

[54] N. Chaturvedi, S. Gupta, V. Sinha, A. Q. Ansari, “Gallium Arsenide (GaAs) High Frequency Clock Generator,” Proc. National Symposium on Recent Advances in Electronics, Amritsar, India, pp. 323 - 329, March 1996.

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