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Design Review: 1 OOW, 400kHz, DC/DC ConverterWith Current Doubler Synchronous Rectification

Achieves 92% EfficiencyLaszlo Balogh

ductor switches are also discussed. Operatingwaveforms and measurement results complementthe paper.

ABSTRACTA high efficiency, 1001N; DC-to-DC convelter

design is presented and reviewed. This designemploys a phase shifted full bridge primary powerstage and the current doubler output with synchro-nous rectification on the secondary. This topologyis palticularly suited to supply low voltage, highcurrent loads in distributed power systems. Lowprofile, off-the-shelf magnetic components are fea-tured. Over 92% efficiency is achieved in anisolated, SV output modular approach where con-velters can be paralleled for load-sharing. Designconsiderations for optimized zero voltage transitionoperation and critical timing issues of all semicon-

TOPOLOGY OVERVIEWFull Bridge Converter

At high power levels or extreme efficiencyrequirements where the use of four controlledswitches are justifiable, the full bridge converter isprobably the best choice. A conventional full bridgeconverter and its most important waveforms areshown in Figure 1. The converter is operated witha three-state PWM signal. During the first state the

Conventional Full Bridge SchematicFigure

~- 2-1 DC/DC Converter


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diagonal switches, OA and OD conduct, followedby State 2 when all four switches are turned off.The third state is the conduction period of OB andOC transistors which is again followed by State 2.

While the utilization of the magnetic compo-nents in this circuit are really excellent, thedynamic losses of the switching semiconductors athigher operating frequencies and/or elevated inputvoltages are excessive. The switching losses canbe reduced by using snubbers (as shown in Figure1 , quasi- or fully resonant techniques, or soft-switching (ZVT) circuits. Soft-switching, also calledZero Voltage Transitions, is preferred because ofits simpler power circuit, high efficiency, low EMIlevels and simpler analysis than its resonantcompetitors.Full-Bridge Converter with Phase ShiftedControlOutstanding performance of the phase shifted,ZVT full bridge converter in DC/DC applicationsare well documented in the literature ([6]-[10]). Thiscircuit is capable of delivering high efficiency athigh operating frequencies because it combinesthe advantages of zero voltage resonant transi-

tions to reduce switching losses and square wavepower conversion to maintain optimal utilization ofthe semiconductors. Additional benefits are con-stant frequency operation, reduced EMI and theintegration of the parasitic circuit components,junction capacitances, leakage inductance andMOSFET body diodes in the power circuit. A fewpossible shortcomings of the circuit include the rel-atively complex phase-shift PWM algorithm andthe potential loss of soft-switching at light load.

The circuit on the primary side resembles theconventional full bridge converter without the usualsnubber circuits. Due to the phase-shift PWM con-trol method applied to the circuit, the dominantturn-on losses of the MOSFET transistors are elim-inated while soft-switching is maintained. However,turn-off losses are still present in the circuit. Theycan be significantly reduced by using a low imped-ance gate drive circuit for quick turn-off of theswitching devices. The greatly reduced switchinglosses explain the absence of the snubber circuitscommonly present in the conventional full bridgeconverters.

As shown in Figure 2, this circuit is controlledby a four-state PWM signal. According to the four

Figure 2. Phase Shifted Full Bridge Schematicl1::!)--2C/DC Convel1er


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states of the PWM controller, the operation of thecircuit is divided into four major intervals. Operationat high load in continuous conduction mode areshown in Figure 2(b) and discussed next.

State 1 (tO~tl):During this state, QA and QD are on and the

voltage is positive at the dotted end of the trans-former windings. The magnetizing current startsramping up from -IM towards +IM. The reflectedload current also flows through QA, the primaryand QD. On the secondary side, D2 is on while D1is reverse biased. The voltage across L is positive,which produces a positive slope in IL

State 2 (tl ~t2):In State 2, QA and QC are on, shorting the pri-

mary at the positive supply rail. The voltage VT, onthe secondary side equals OV too. D1 and D2 areon, L freewheels. The output voltage across Lmakes IL decrease. Note that despite both diodesare forward biased and connected in parallel, mostof IL keeps flowing through that half of the sec-ondary which was conducting during State 1because of the combined effect of the shortedprimary winding and the parasitic inductances.

State 3 (t2~t3):In this interval, QB and QC are on. VT is nega-tive and IM goes from +IM to -IM. The reflected load

current also flows through the primary compo-nents. At the same time, D1 conducts and D2 is offon the output side. The voltage across L is positiveagain and IL starts rising.

State 4 (t3~t4):The full operating cycle is completed by anoth-

er freewheeling period when QB and QD are on,shorting the transformer primary at the negativesupply rail. Consequently, VT on the secondary iszero. Diodes D1 and D2 are on simultaneously.The voltage across L is -Vo to establish the free-wheeling mode for L.

Soft-switching operation of all four primarysemiconductors is achieved by inserting a delaytime between the consecutive operating states.

During this delay time, a resonant action takesplace between the various capacitances andinductances connected to the center point of thebridge leg. This resonant transition is driven by theinductive energy stored in the magnetic compo-nents of the circuit. They are the magnetizing andleakage inductances of the transformer, any exter-nal commutating inductor might be used in serieswith the primary and the output filter inductor. Thestored inductive energy has to overcome thecapacitively stored energies in the Coss capaci-tances of the MOSFETs, in the parasiticcapacitance of the isolation transformer and in anyexternal capacitors might be needed to limit dv/dtduring the resonant transitions. Since the storedinductive energy declines exponentially atdecreasing current levels, achieving soft-switchingunder light load conditions can be troublesome.Phase Shifted Full Bridge Converter withCurrent Doubler Synchronous Rectifiers

The introduction of several integrated circuits[11] has provided effortless implementation of thecomplex phase-shift PWM control. On the otherhand, designs with potential failure of soft-switch-ing at light load can not really take advantage othe lower EMI generated at nominal load.Significant efforts have been made to retain soft-switching at light load ([9],[10]). In this paper, thecurrent doubler technique with synchronous rectifiers [1] will be used to extend the soft-switchingcapability of the phase shifted full bridge converterunder all load conditions.

Figure 3 introduces the power stage and itsbasic waveforms. The operation of the primary sidewas already discussed and this part focuses on theunique properties of the current doubler rectifiers.

The current doubler rectifier can be derivedfrom the full-wave rectifier circuit using a simpleconversion of the different current and voltagesources of the circuit. Figure 4 shows the steps othe transformation leading from the full wave to thecurrent doubler configuration with synchronousrectifiers.

The current doubler offers an alternativerectification method for forward, push-pull anbridge type converters where bipolar voltages ar

[1:D- 2-3 DC/DC Converter


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OA CLQC

VI -Tp1"mm

OB J:: aD

I I j IGATEA--t ~--1 : r-=GATEB I I I I f-GATEC I. : L--L-GA EV~EH

ITf-=-=i~ LUVL'~~ t--FU

GATE-L L-- I r=-:-T::~: :fi-+-

'LI-~--~--l--J-VL2 F=1: --t f ---j=GATE =i I-~t---~~---\-

I~I I~II~IL2 -L L --~ i ---I -I I I I ItO tl t2 t3 t4-tO

LI~

:La1

--Q +Lc Yor

rQ2L2

~

(.)

(b)

Figure 3. Phase Shifted Full Bridge Converter with Current Doubler Synchronous Rectifiersutilized at the secondary side of the isolation trans-former. Circuit operation greatly depends on theprimary power stage since it has a profound effecton the current distribution during the passive orfreewheeling period. In those cases, reported in[2], [3] and in the full bridge converter with phaseshifted control, used in this design, currents canfreely flow in the primary and in the secondarytransformer windings during the freewheeling peri-od. Thus, the current of the output inductors, IL1and IL2 can change direction as is required by theload to extend the range of continuous conductionmode operation to lower output current values.

The circuits in Figure 4(d) and 4(e) are com-posed of the secondary winding of the isolationtransformer which is not center-tapped now, tworectifier diodes, two identical filter inductors and anoutput capacitor. It offers a simpler structure, betterwindow and copper utilization for theisolation transformer and a reduced turns ratiocompared to full wave rectifiers. This techniquerequires two identical output inductors, L 1 and L2,

01

Figure 4. Derivation of the CurrentDoubler Rectifierboth working at half the operating frequency and athalf the rated current of their full wave counterpart,L. One unique set of benefits of the circuit is thatthe diode and output capacitor stresses areidentical to the full-wave technique.

[1::0--4C/DC Converter


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...IT - 1I" " I

"-4-1---II' IiIII II:J--t i- i- .:.-11IGATE Q1 1 1II

II1 III1 1-- --II

VL1 -

~ 'II I II I I I II I I I II 1"'-- I I... I --1- IILl -L---~---~ I--:::",-~---I l-I I I ---l II I I I ---It" I I I..'I I I I II I I I I

GATE a2 -~ ~ L=r

1IIJ 1...I, 1...' II... I 'L2 -1- -:.'0,.-~ +-- ---1- ~- --1- l-

1 '", I I IIII'" 1 1 II I '-+' IIIII II~ ~ ~III 1 II III 11 ~~+, I ~~+, IIO .I L1 +1 I ~ ~ , 1 ~ ~ 1 ' .l2 -~--7 + ~ ~- -L..~~ I' 1 ~~~ I '-JII y 1 II I I I

to 11 t2 13 t4.1O

Figure 5. Operation of the Current Doubler Rectifier

[1::0- 2-5 DC/DC Converter


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starts increasing. In this state, IT equals IL2, thusonly half of the load current flows in the secondaryagain. L 1 freewheels through 01 and IL1 decaysby the rate of -VO /L 1.

State 4 (t3~t4=tO):The full operating cycle is completed by anoth-

er freewheeling period. The voltage VT becomeszero and 01 and 02 are on simultaneously. -Voappears across L2 causing its current to decreaseand freewheel through 02 while L 1 continues tofreewheel as in State 3.

The no load operation of the circuit is illustrat-ed by the dashed lines in the current waveforms.Both filter inductors have bi-directional currents,hence the duty ratio does not change to accom-modate the lower output current level. The currentdoubler preserves continuous conduction modeoperation of the converter under all load condi-tions. There are two significant advantagesassociated with this effect. One is that the convert-er gain will not collapse. This phenomena wouldtake place at the onset of discontinuous conductionmode, which is completely eliminated in this circuit.The other advantage is the constant amplitude ofthe magnetizing current from zero to full load. Thisrepresents a significant benefit to ensure softswitching at light loads.

The current doubler working under the sameconditions as a full wave rectifier will reduce thecopper loss in the transformer secondary byapproximately 50%, as reported in [4]. Convertersusing the current doubler rectifier might achievelower and better distributed power dissipation andsmaller overall volume for magnetic components.An integrated magnetic solution for further reduc-tion in size and cost has been also reported in [2],using a half-bridge converter as the primary powerstage.

Figure 4(f) shows the two controlled switchesfor synchronous rectification. The operation of thecurrent doubler rectifier with synchronous rectifica-tion is highlighted in Figure 5.

In accordance with the primary side, theswitching period is divided into four intervals.

State 1 (tO~tl)At to, VT becomes positive at the dotted end of

the secondary. During State 1 01 is off and 02 ison. Current flows in positive direction in both filterinductors. The sum of IL1 and IL2 supplies the loadcurrent. Because of the peak current mode controlused on the primary side, the peak values of IL1and IL2 must be equal, thus the load current isequally shared between L 1 and L2. The current IL1flows through 02 and the transformer secondary.The voltage across L 1 equals VT-VO. This positivevoltage causes IL1 to increase. At the same time,L2 freewheels through 02 and IL2 decreases bythe rate of VdL2. The current through the sec-ondary, IT equals IL1 and it accounts for half of thetotal load current.

State 2 (tl-')t2):In this state, VT is zero and 01 and 02 are both

on. The voltage across L 1 becomes -VO, produc-ing a negative slope in IL1, which now flowsthrough 01. The conditions for L2 do not changeand both inductors are in freewheeling mode.

DESIGN SPECIFICATIONSInput Voltage (VU: 32V to 72VOutput Voltage (Vo): 5VOutput Current (10): OA to 20AOutput Power: 100WEfficiency: >90% at full loadOutput Ripple: 100mV p-pZVT Range: 0% -100%Isolation: 1000VRMSSwitching frequency (fCLOCK): 400kHz (200kHzmagnetic

components)DESIGN OVERVIEW

A full bridge converter with current doublersynchronous rectifiers was implemented usingstandard, commercially available componentswherever it was possible. Power to this unit is

State 3 (t2~t3):During State 3, Vr is negative at the dotted end

of the secondary winding, 01 is on and 02 is off. Apositive voltage, Vr-Vo appears across L2 and IL2

0::!)--6C/DC Converter


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supplied from the nominal 48V bus of a distributedpower system. Control functions are provided by aUC3879 control IC. A galvanically isolated 5V out-put is capable of delivering 20A to the load. Thefeedback incorporates an opto-coupler to cross the500V isolation boundary between the primary andsecondary side of the power supply. Load-sharingcapability is added to accommodate higher currentloads by paralleling several modules.

Understanding the four major states givessufficient information about the square waveoperating principle of the circuit. Unfortunately, theultimate performance of the power supply dependsupon how well the circuit works during the switch-ing intervals. A resonant transition takes place inthe circuit every time the converter advances fromone state to the next one. The delay between turn-ing off one switch and turning on its comple-mentary pair in the same bridge leg provides theopportunity for the resonant operation of the para-sitic components. In an optimal design, theresonant action aligns all four switches under alloperating conditions to zero voltage before theswitch is turned on. Only in this case the circuit iscapable of delivering high efficiency and low EMIlevel. The conditions of the successful ZVT opera-tion depend on the power and parasitic componentvalues and the optimization of the delay times, asit will be shown later.POWER STAGE DESIGN

This section determines the major componentsand critical operating parameters of the power con-verter. Trying to use as much off-the-shelfcomponents as possible will require adifferent way of thinking. In several instances theactual design process is substituted by definingthe selection criteria of the components. However,understanding the underlining principles of thecomponent parameters and their effect on theoperation of the circuit is imperative to successfullyexecute the design.

SemiconductorsThe MOSFET transistors selected for the pri-mary side switches are MTP33N10E types. These100V, 58mQ devices have one of the lowestRoSON values in TO220 package. Several factorshad to be considered in the selection process ofthese components. These are the gate drive powerrequirements, transition times and their proportioncompared to the switching period (loss of effectiveduty ratio), potentially higher primary circulatingcurrent which parameters are functions of the par-asitic parameters of the chosen MOSFET device.Valid considerations were given [5] for high inputvoltage applications, where the lowest RoSONdevices do not guarantee the optimum efficiency.Nevertheless, in this low input voltage applicationwhich also maintains lossless turn-on of thedevices at all operating conditions, conduction lossis the dominant one. It can be minimized by usingthe lowest possible ROSON devices.

In addition to the extended soft-switching oper-ation of the circuit due to synchronous rectification,the output rectifier circuit employs twoMTP75N50HD type 50V, gmQ (max. value)devices for more efficient power conversion. Theselection criteria for these devices is the lowestpossible RoSON value that technology and costconsiderations allow.Transformer DesignConventional transformer design starts withdetermining the acceptable temperature rise, thecorresponding minimum area product and themaximum flux swing allowed to stay within the cal-culated core loss limits of the transformer. Theseparameters will define the number of turns requiredon the primary side. The secondary number oturns calculated from the turns ratio, is based onthe minimum value of the input voltage, the maximum steady state duty ratio and the DC transferfunction of the converter.

When off-the-shelf parts are considered, thefirst step is to calculate the DC transfer functionand the required turns ratio. For the phase shiftedfull bridge converter with current doubler outpu

DC/DC Converter-7


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PULSE part number:Power rating:

Solving the equation for N, the required turnsratio can be calculated as:

N= ~='). Yo

PE-68499100W convectioncooled, 200W200kHz-500kHzEE (custom)0.6W26C/W27C10 (2x5 in series)186I.JH14m.Q.16m.Q.42.5m.Q.2.8m.Q.0.26I.JH186pF1000Vrms1.16"x1.07"xO.032"14.5 grams

",- Np-- VI,MINDMAX (2)Two important conclusions can be drawn from

this result. The current doubler output stage needstwice the number of turns on the secondary sidethen its full wave counterpart, but only one windingis needed. Otherwise, the transfer function is iden-tical to any traditional full bridge circuit using fullwave diode rectifiers. As a result, existing designswith full wave rectification can be easily modifiedfor a current doubler configuration with the presenttransformer if the center tap termination is notused. Note also that the number of turns on the pri-mary and the secondary side are closer to eachother for this design. Consequently, the trans-former turns ratiQ can be adjusted in finer steps,lower leakage inductance can be achieved and themaximum duty ratio can be better optimized in acurrent doubler configuration.

In this design:Vo = 5VVI MIN = 32VOMAX = 0.8

therefore:

Operating frequency range:Core type:Est. core loss:Thermal Impedance:Est. temperature rise:Primary number of turns:L-magnetizing:R-dc primary:R-ac primary:Secondary number of turns:R-dc secondary:R-ac secondary:L-Ieakage:Cp (transformed to primary):Hipot:Dimensions WxLxH:Weight:Table 1. Transformer Data

For users planning to design their own trans-former, the design procedure is given in severalreferences. A conventional transformer designexample can be found [12] while detailed consid-eration for planar transformer structures are alsodiscussed [5]. In general, the phase shifted fullbridge converter is very forgiving of the parasiticvalues of the transformer because these compo-nents are utilized beneficially in the operation of thecircuit.Switching TransitionsOne goal of this design is to maintain zero volt-age switching for the entire load range from zero to20A output current. To guarantee the soft switchingof all four primary semiconductors by design, theconditions of the ZVT operation have to be ana-lyzed [6]. The first observation to make is to realizethat the two legs of the bridge converter operate

After reviewing the available transformersaccording to the required size, power rating, oper-ating frequency range, temperature rise, mountingconsiderations and turns ratio, the selected part isa PE68499 type. It is a low profile surface mount

[1=:0-C/DC Converter 2-8


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under different conditions. Switches OA and OBare driven by the clock signal of the controller.Every time a clock signal is generated one of theseswitches turns off and, after the delay specified inthe controller, the other switch turns on. Whenevera switching action takes place in the leg formed byOA and OB, the converter terminates the free-wheeling (or passive) state and starts a new activeinterval, delivering energy from the primary to thesecondary side of the power supply. Thus the legcomprised of OA and OB is called the Passive- To-Active (P~A) leg. On the contrary, the other side ofthe bridge circuit composed of OC and OO is calledthe Active- To-Passive (A~P) leg. Switching actionin the A~P leg is initiated by the PWM comparatorwhen the measured current signal or the rampequals the actual value of the error signal. At thatinstant, the power flow from the primary to the sec-ondary side is interrupted and the circuit goes to apassive (freewheeling) state.

A-+P leg resonant transitionA typical full bridge converter with all the para-

sitic components and initial conditions is shown inFigure 6(a). Switching transition starts with turningoff QD. The schematic diagrams featured in Figure6(b) and 6(c) represent the equivalent circuits ofthe phase shifted full bridge converter during theresonant transition. There are two componentswhich propel the resonant action in this transition.One of them is the contribution of the magnetizingcurrent. The value of the magnetizing current atturn-off of QD (or QC) is constant. It is independentof the input voltage and the load current while reg-ulation is maintained on the output of the converter.This is because the converter operates in continu-ous inductor current mode from zero to full loadand the applied volt-second product is constant. Itsvalue equals:

1 VI 1IM = 2 .LM .D. fCi:OCK (3)

Figure 6. A-tP Transition Equivalent Circuits

0=:0- 2-9 DC/DC Converter


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COSS = 600pF drain source capacitance of theMOSFET transistors,

Cp = 180pF equivalent parasitic capaci-tance transformed to theprimary side,

CSN = 2.2nF external snubber capacitanceto control dv/dt at the A~P leg,

N = 0.4 transformer turns ratio,LM = 186J.1H magnetizing inductance,LLK = 0.26J.1H transformer leakage inductance,LEXT = 2J.1H commutating inductance,L 1 = L2 = 3J.1H output filter inductances,VI = 32V, 48V input voltage (worst case is72V VI,MAX),Vo = 5V output voltage,10 = OA ...20A dc output current of theconverter,

These results were verified by using the morecomplicated equivalent circuit and PSpice circuitsimulation yielding similar values for the transitiontime.

The other current component driving the tran-sition is the contribution of the load current. Itsinstantaneous value at the beginning of the reso-nant action varies with the load current andcalculated as:

IL1,PK = IL2,PK =

(4)

It is important to note that both currents willactually increase during the transition because ofthe polarity of their respective voltages.Consequently, this soft transition will take placeevery time, if enough time is allowed for the reso-nant action to be accomplished.

The capacitive and inductive energies of thecircuit at the beginning of the A-+P transition aredefined as:

1 2EC,A~P = 2.(2 .CoSS+Cp+CSN).VI (5)1 1 Ll

EL,A~P= 2 .~.~2+ 2 .W.(N.ILl,P~2

"t(12V)

"t(48V)"t(32V)

12.(LLK+LEXT).(IM+N.ILl.P~2 (6)

Figure 7. Required Time to Complete SoftTransition in the A-tP Leg.

When EL,A~PEC,A~P, the currents will notchange significantly during the resonant transitionand the equivalent circuit of Figure 6(b) can be fur-ther simplified as shown in Figure 6(d). Theinductive circuit components can be replaced by acurrent source, therefore, the time required for theswitching transition can be calculated by the fol-lowing simplified formula:

'"t'OELAY,C-O = (2 .CoSS + Cp + CSN) .VI

The conclusion of this exercise is to demon-strate that the transitions of the A--tP leg in thephase shifted full bridge converter are inherentlysoft under any load conditions, if the delay time('tOELAY,C-O) between the turn-off and turn-on ofthe transistors OC and 00 is set properly. In thesection describing controller design issues, a sim-ple circuit will be introduced to be able to optimizethe delay time of the A--tP leg based on the

(7)M + N .ILl.PK

Figure 7 shows the solution of (7) using the fol-lowing circuit parameters:

~--10C/DC Converter


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actual current value propelling the resonanttransitions. (9)( Vo 1IL2,V = 2 0 10- L2 0 (2-D)ofCWCK

P-."A leg resonant transitionInitial conditions and equivalent circuits for the

P-."A leg transitions are shown in Figure 8. Theoperation of the circuit during this switching intervalis rather complicated and has several modesdepending on the actual output current value.Modeling the resonant transitions of the P-."A legrequires understanding the fine details of the wholepower stage.The switching transition starts with turning offQA. At that instant the magnetizing current and thereflected load current flow through QA, the primarywinding of the transformer and QC. The instanta-neous value of IL 1 and IL2 at the beginning of theresonant transition can be calculated as:

The capacitances loading the common point ofthe transistors OA and OB are the COSS capaci-tances of the two MOSFETs and the equivalentparasitic capacitance of the transformer.Depending on the values of the parasitic compo-nents and the load condition, there are twofundamentally different modes of the resonanttransition in the P~A leg. In the first mode, the volt-age across the "theoretical" primary winding stayszero during the resonant action, while in the othermode, the voltage across the transformer will startchanging.It is very important to point out here that at thebeginning of the P~A leg resonant transition thevoltage is applied first across the leakage and anyexternal inductances added in series to the theo-retical primary winding of the transformer. The8)

[1:=0- DC/DC Converter-11

I ( Vo I )Ll = 2. 10 + LT .D. fCLOCK


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EL,P~A,case2 =~. (LLK + LEXT) .(IM + N .ILJ2 +voltage across the real primary and consequentlyacross the secondary must stay zero until the cur-rent in the leakage and external inductors changesdirection and reaches the value of the reflectedload current.

If the resonant transition can be completed bythe energy stored in the leakage and commutatinginductances, switching action will be completedbefore the voltage starts changing across the pri-mary winding of the transformer. For this case, thecapacitive and inductive energies of the resonantcircuit are given as: or

EC,P~A,casel = ~ .2 .COSS .V( EL,P-..A,case3 = ~ .(LLK + LEXT) .(10)L2

N2.LM-IEL,P-+A,casel = ~ .(LLK + LEXT) . [


13/26

increases the reflected output current value on theprimary side and the voltage stress of the sec-ondary side rectifier devices, both leading towardlower overall efficiency of the circuit. Another wayto extend the soft-switching range of the converteris to reduce the value of the output filter inductorsand/or the magnetizing inductance. This way, itinsures that the reflected output current alwaysstays below the actual magnetizing current value.It is usually not possible to sufficiently reduce thevalue of the filter inductor in a regular full wave out-put rectifier structure, because of the increasingstress of the filter capacitors and the higher outputnoise. However, in the current doubler configura-tion, the ripple currents of the two output inductorscancel each other at the output capacitor, thereforethis solution can also be considered.

For example, Figure 9, 10' 11 and 12 show theP~A leg resonant transitions with different combi-nations of output and commutating inductor values.

These waveforms show that the best result isachieved with 3IJH output inductors and by addingan external 2IJH commutating inductor in serieswith the primary winding of the transformer. Thevalue shall be determined for worst case

conditions at the maximum input voltage usingthe equivalent circuit of Figure 8(b) and circuit sim-ulation tools, or by solving the equations given in(10)-(16). Figure 13 displays the common solutionof (10)-(16) obtained by MathCAD. When theavailable energy curve, EL,P-tA is above therequired energy line, Ec,P-tA lossless switching ofthe P-7A leg is feasible.Because of the complex nature and numerousconditions involved, deriving closed form equationsfor the transition time of the P-7A leg would berather difficult. Figure 14 shows the required timeto complete the transitions as a function of the out-put current. The optimum value of the commutatinginductor value was obtained by varying the LEXTparameter in the MathCAD calculations used togenerate Figure 13. The final numbers in Figure 14were calculated by PSpice simulation, using theequivalent circuits in Figure 8(b).Output Inductors

Although the current doubler offers significantbenefits for the power transformer ([1 ]-[3]), itrequires one additional output inductor. While intraditional full wave output stages the entire outputcurrent flows through the filter inductor which

~- 2-13 DC/DC Convel1er


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Figure 10. Resonant Transition in the P~A Leg Lo=3JlH; Lm=186JlH; Lext=OJlH.

TimeFigure 11. Resonant Transition in the P-tA Leg Lo=6f.JH; Lm=186f.JH; Lext=2f.JH.

r!::!]-C/DC Converter 2-14


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TimeFigure 12. Resonant Transition in the P--,;A Leg Lo=3JlH; Lm=186JlH; Lext=2JlH.

operates at double the frequency of the isolationtransformer, these inductors carry only one half ofthe load current and they work at half the frequen-cy of their full wave counterparts (same as theoperating frequency of the power transformer). Thecurrent waveforms are 180 degrees out of phaseand the ripple components partially cancel eachother in the common output capacitor. For thesame equivalent output ripple current that would begenerated by a full wave rectifier circuit, the induc-tance of each output choke has to be doubled.

Considering that the physical size of the inductorsare proportional to their energy storage capabilities(IL2 .L), the total core volume of the two outputinductors is the same as the single fi lter chokeused in the full wave rectifier circuit.

The two output inductors of the circuit wereselected from the same PGF product line offeredby Pulse Engineering. Their value is based on thesimulation results of the P-tA leg resonanttransitions and their characteristics are reviewed inTable 2.

25ILJ I

"t(72V)

~EL.P-A /~~!.v!..-:-~3-"-~~--100", / ~EC.P-+-A l- ~./-'"--- ~-:t- l---o Io 25 5 75 --'--"--"""-1175 200 125 15

'o!AJ15 200

lo[A]Figure 14. Optimal Timing of the P~A Leg.Figure 13. Available and Required Energiesof the P~A leg.

~- 2-15 DC/DC Converter


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PGF Surface Mount Power Inductor-PULSE part number:Current rating:Inductance:Operating frequency rangeCore type:

PE-5401110Adc2.75~H @ 10A200kHz- 500kHzEFD 15 gappedferrite80mW2.7mQ0. 7"xO. 7"xO.032"1 0 grams

Est. core loss:R-dc:Dimensions WxLxH:Weight:

25% of the conduction losses of the MOSFET tran-sistors. When Schottky diodes were used, theswitching losses were estimated as 5% of the con-duction loss of the diode.

Synchronous MOSFET switches are used inthis design to achieve higher efficiency and zerovoltage transitions from zero to full load. To avoidbody diode conduction during the freewheelingperiod of the converter, the synchronous switchesare driven from the primary side.

This technique is called control driven synchro-nous rectification ([1],[3]) and it offers the capabilityto reverse the current direction in the output induc-tors. Similarly to other topologies utilizing controldriven synchronous rectification, the turn-off of theappropriate rectifier switch has to precede theswitching action on the primary side. The propertiming of the MOSFET rectifiers have an importantrole in determining the ultimate efficiency of the cir-cuit. Early termination of the conduction interval willforce the current into the body diode of the transis-tors leading to reverse recovery problems andswitching losses in the device. Conversely, anydelay at the turn-off of the synchronous switcheswill result in a shoot through situation on the sec-ondary side of the isolation transformer loweringthe potential efficiency of the circuit.

Table 2. Output Inductor DataFor designing your own output inductors, the

procedure is given in [13]. There are no additionalcircumstances which would require special atten-tion. In general, since the inductors of the currentdoubler circuit work with higher ripple current, fer-rite or another low loss material is the preferredchoice. Balancing the core and copper losses arealso easier with this topology.Synchronous Rectification

Advancement in high density, low ROSONMOSFET development makes synchronous rectifi-cation a feasible and competitive rectificationtechnique for low voltage, high current DC/DC con-verters. Analysis of the readily available hightemperature, low forward voltage drop Schottkyrectifiers and high density, low RoSON MOSFETtransistors shows that synchronous rectifiers arebeneficial below 25A output current. Figure 15shows the power dissipation of a MTP75NO5HDMOSFET transistor and a 32CTQO30 Schottkyrectifier as a function of the output current in a lowoutput voltage application.This comparison is based on identical operat-ing conditions, assuming no conduction of theMOSFET body diodes during the freewheelingperiod. However, switching losses were added tothe conduction losses since body diode conductioncan not be completely avoided during the switchingintervals. This switching loss was estimated as Figure 15. Power Dissipation of Schottky andMOSFET Rectifier Devices

0::!)--16C/DC Converter


17/26

Secondary Gate DriveBecause the timing of the synchronous switch-

es is critical for proper operation, the high currentgate drive circuits of 01 and 02 are located on thesecondary side. Power for these drivers is provid-ed directly from the secondary winding of the maintransformer by peak rectification. This way, the dri-vers are operational even with a shorted outputand during start up, when the output pulses areshort. The drive signals are transmitted to the sec-ondary side via a signal transformer, a techniquewhich eliminates the delay usually associated withthe leakage inductance of the gate drive trans-formers. Figure 16 shows the logic and the timingrelationships between the primary and secondarygate drive pulses.Adding Parallel Diodes to the SynchronousMOSFETs

This technique is well known, but is not a uni-versal solution to avoid the reverse recoveryproblem of the body diode in the synchronousMOSFET transistor. The source of the problem isI "0" !

.x -O.56V = 28A-2 olOnH ~sec

--".( I ~ ! j ! ! ! j !-+-: : ~: :: ~:OUTA1J j-:---1 : : : : tI I I I I I I I I IOUTB 1 : .: : : I :-~--L-:-

i i i I --~+1-+-++-1 I I I II I I I I I I IOUTC --rTUTDtJ I: : : : I --tJ-: ) ~ .I I I I I IVT J J~)~l j-: Ij

(i (j

t

OUT II ' i N-Y' .I I I I I I I I I II I I I I I I I I II I I I I I I IOUT1 I I I I I I I I I I1 I I I I I I I I II I I I I I I I I IOUT24-: I: : : : : ~VDRV

GATEQ1 =1 : 1-t=--r1 j-t=--LJ.-I I I I I I I I I I'-~~ ~-:---I: I-:---~~-1 I I I I I I I 1 II I I I I I I I I I: I. ~ t3 t4-tO

~i'i'~19'

~6RV~ H7 ~ 7~( G GATE 02tO

(a)Figure 16. Circuit and Timing Diagram of the Secondary Gate Drive.

[1 2-17 DC/DC Converter

the packaging inductances inherently present insemiconductor packages. Since the body diode isa parasitic component of the silicon structure of theMOSFET device, it is connected in parallel with thechannel without any inductance. The current canflow either in the channel or the diode section ofthe part without overcoming the effect of the bondwire inductance. When the current of the deviceestablishes in the body diode, there is only a verylow voltage available to steer the current from theMOSFET diode to any externally paralleled diode.To demonstrate this, assume a very favorable10nH parasitic inductance for a TO220 semicon-ductor package. The voltage drop across the bodydiode is approximately 0.76V at 10A in aMTP75N05HD transistor. On the other hand, a32CTQ030 type Schottky has a voltage drop of0.2V at 1A. The maximum rate of change in thecurrent between the two device is:

dldl MA

IIII

~


18/26

To ensure fast switching speed and fullyenhanced operation of the primary side MOSFETtransistors, the desired undervoltage lockout is15.5V for this example. It is accomplished by leav-ing the UVSEL pin of the UC3879 floating.

Clock frequency of the controller is pro-grammed to 400kHz. In order to maximize theoperating duty-cycle of the converter, the timingcapacitance is kept at its minimum value, 220pF.Once the CT value is given, AT is defined as:

0.47+0.07 .~ 47.17- 5 .1()4.cr. fCLOCKRT= CT. fCLOCK(16)

The time between turning off one switch andturning on the other in the same leg of the fullbridge circuit has a profound effect on the circuitperformance. One unique feature of the UC3879 isthe ability to separately program the delays of theA~P and the P~A bridge legs.

The delay time of the A~P leg is set at theDELAYSET C-D pin of the controller. Figure 7shows the required time to complete the soft tran-sition in the A~P leg as a function of the loadcurrent. According to the graph, the optimum delayvaries from 20ns to 165ns depending mainly on theoutput current and slightly on the input voltage val-ues. Although, using the maximum number willensure zero voltage switching under all operatingconditions, it will reduce the maximum obtainableduty ratio for the converter. For this reason, adjust-ing the delay time seems desirable. Figure 17shows a simple solution to adjust the delay timeaccording to the actual load current based on thecurrent information available on the primary side.

The situation is more difficult at the P~A leg.As Figure 14 shows, the longest transition timeusually does not coincide with the lowest currentlevel (zero load) in the converter, thus the simplecircuit of Figure 17 can not provide the optimaldelay under all operating conditions. Nevertheless,it can correct for most of the variations in the tran-sition time above the load current level whichcorresponds the longest delay time. Below the crit-ical current, the delay time will be somewhat longerthan optimum.

That means a minimum of 400ns time intervalfor the current to be transferred from the bodydiode to the external Schottky at full load (1 OA). Athigher output currents the situation becomes evenworse and the time required to direct the current toan external device very quickly approaches thetotal duration of the freewheeling period.

Best efficiency results were obtained by slow-ing down the switching speed of the synchronousswitches by placing a 15.0. series resistor in thegate drive path. At turn on, the body diode con-ducts for a short period of time, but it does notcause significant losses because it will befollowed by the conduction of the channel. Atthe turn off process, the MOSFET operates inlinear mode during the switching period preventinga significant portion of the current to flow in thebody diode. As a result, body diode conduction andthe associated reverse recovery problem is greatlyreduced while conduction losses are only slightlyincreased in the device.CONTROLLER DESIGNController Setup Using the UC3879

The new UC3879 phase-shift PWM controlleris an improved version of the UC3875 family.Below is a list of the improvements and the newfeatures of the IC. Further details on the UC3879phase shift PWM controller can be found in refer-ence [14]:

.Selectable undervoltage lockout options

.Lower power consumption

.Improved oscillator circuit

.Cycle-by-cycle current limiting

.Flexible delay time circuit with zero delayoption.Low current TTUCMOS compatible outputsto enhance noise immunity.

In isolated power supplies, where the erroramplifier is located on the secondary side of theconverter, the controller setup is limited to selectingthe appropriate undervoltage lockout option, defin-ing the timing components of the oscillator,determining the proper delay times for the twobridge legs, interfacing the current sense circuit tothe controller and calculating the slope compensa-tion if required.

[1JJ--18C/DC Converter


19/26


20/26

needed for thisresistor at full loamaximum signalAccordingly,

R7 = 50. 2VIp,MAX (20)

Primary Gate DriveThere are two different methods to drive the

four switches of the full bridge converter in con-junction with the UC3879 controller. One requireshigh current drivers and two gate drive transform-ers, each with two secondary windings to drive twoMOSFETs in the same bridge leg. The other solu-tion employs integrated high and low side drivers.This design features two IR2110 half bridge MOS-FET gate drive integrated circuits from InternationalRectifier.Using the integrated half bridge driversreduced cost, board area and eliminated two addi-tional magnetic components in this application.Isolated Feedback

This design was intended for modular powerarchitectures where high current loads are often sup-plied by several, parallel connected power supplieswith lower individual current rating. For these appli-cations, the UC3907 load share controller offers aflexible and low cost secondary side solution. Thisintegrated circuit incorporates the precision voltagereference, error amplifier, current sense and loadshare functions in one 16 pin IC, [15].

Although loop stability is not in the focus of thisdesign review, the following considerations can beuseful in closing the feedback loops of the system.From loop stability point of view this circuit oper-ates at 400kHz. It is determined by the controllersampling rate and the output ripple frequencywhich equal the clock frequency. There are threeloops interacting in this power supply. The first loopis the current loop, residing on the primary side.Slope compensation is not required when thecurrent doubler output stage is employed becauseboth filter inductors are working below 50% dutyratio. The gain of the current loop is embedded in

the control-to-output transfer function as a con-stant, below the crossover frequency of the voltageloop. The second loop is the voltage control loopwith a crossover frequency of 10kHz in this exam-ple. When a third loop, such as the load sharecircuit, is added to the system, there will be twoloops controlling the output voltage. To preventinteraction between the two loops, the designerhas to ensure that the crossover frequency of theload share loop is at least one order of magnitudelower than the one of the voltage feedback loop,which is usually adequate in preventing thermaland reliability issues at paralleling modules.EXPERIMENTAL RESULTS

The final schematic of the power stage andcontroller section are presented in Figure 18 and19 respectively.

The example converter was built and testedover all operating conditions. Figure 20 and 21illustrate the characteristic waveforms of the con-troller. Figure 20 shows the signal across the timingcapacitor (trace 1 ), the SYNC output of theUC3879 controller (trace 2), the primary currentwaveform on the secondary of the current sensetransformer (trace 3) and the voltage on the COMPpin of the UC3879. As shown, the converter is run-ning closed loop at 400kHz. The four outputs of thecontroller are displayed in Figure 21. The operatingduty ratio is approximately 75%, based on thephase relation between the signals.

The primary side operation of the circuit at 15Aand OA output current is demonstrated in Figure 22and 23 respectively. The traces in both pictures areA-7P leg and P-7A leg middle points, transformercurrent and transformer voltage waveforms. Soft-switching of all four primary switches at no load hasbeen achieved and shown in Figure 23.

Figure 24 and 25 verify the operating principleof the current doubler output stage with respect tothe primary waveforms. Shown are the middlepoints of the A-7P and P-7A legs along with IL 1and IL2 at 15A and OA loads.

l1:=O--20C/DC Converter

topology, the sid shall be set toon the CIS+ pin

gnal across the2V, which is theof the UC3879.


21/26

-Figure 18. Phase Shifted Full Bridge Power Stage with Current Doubler Synchronous Rectifiers.

Figure 19. Controller Schematic Drawing.L!:::!J- 2-21 DC/DC Converter


22/26

put current before the output filter capacitor and thetwo individual inductor current at 15A and at OAload respectively.

Figure 31 completes the tour of the operatingwaveforms, illustrating the gate drive waveforms ofthe synchronous switches in respect to the trans-former secondary voltage and the unfiltered outputcurrent at 15A load.The efficiency of the circuit measured at nOmi-nal input voltage, is shown in Figure 32. Thehighest efficiency achieved was 92.5% at half load.The circuit operated above 90% efficiency in therange from 4A to 20A load current.

The next three pictures are dedicated to theresonant transitions of the P~A leg. In Figure 26the converter is running without load and the reso-nant transition is completed in a relatively longtime, 200ns. The same transition, shown at 10Aload in Figure 27, takes only 60ns. Figure 28 wasalso taken at 10A output current, but the modula-tion of the delay time was disabled. Thecomparison of Figure 27 and 28 shows clearly thebenefit of the adaptive delay times.

Typical waveforms of the current doubler syn-chronous rectifier are shown in Figure 29 throughFigure 31. The waveforms in Figure 29 and 30 arethe voltage of the transformer secondary, the out-

/1 ~ .,/\ .,;"1/ ...~// vn

2

~ ~ ~ \..4

Figure 20. Controller Waveforms; CT (pin 14),CLKSYNC (pin 17), RAMP (pin 19) and COMP

(pin 2).

0:=0--22C/DC Converter


23/26

h '-.ll 1 ..1--\..; ,. .;", .;,.2

: m- ~.1

f. ...! ! ! ..! ! , ~mFigure 25. Operating Waveforms at OA load;P~A leg, A~P leg, IL 1, 'L2, (both 5A1div).CONCLUSIONThe current doubler topology with synchronousrectification had been presented. This altemativerectification technique simplifies the power trans-former and adds one more filter inductor to theoutput rectifier circuit in push-pull, half-bridge andbridge converters. Superior performance of the cir-cuit had been shown in a 100W, 400kHz, DC-DCconverter. The example power supply combines theexcellent characteristics of the current doubler recti-fier with the superior properties of the phase shiftedfull bridge converter on the primary side. This com-bination has proved its effectiveness achievingefficiency above 92% in an isolated 5V output powersupply, operating from a 48V distribution bus.

/\V.

I i",,! 1111'

: : ...t ~ ....r

Tigure 28. Transition time without the

adaptive delay time control.

m

O::D- 2-23 DC/DC Converter


24/26

Figure 32. Efficiency VS. Load @ 48V input.[2] K. O'Meara, "A New Output Rectifier

Configuration Optimized For High FrequencyOperation", HFPC '91 Proceedings, pp. 219-225

REFERENCES[1] L. Balogh, "The Performance Of The Current

Doubler Rectifier With SynchronousRectification", HFPC '95 Proceedings, pp.216-225

[3] I. Do Jitaru, "High Efficiency DC-DCConverter", HFPC '94 Proceedings, pp. 120-127

[4] Lo Balogh, "The Current doubler Rectifier: AnAlternative Rectification Technique For Push-Pull and Bridge Converters", Design Note-63,Unitrode Integrated Circuit Corporation, DG-300, ppo 12-14

[5] W. M. Andreycak, "Design Review: 500W,40W/in3 Phase Shifted ZVT PowerConverter", Topic 4, SEM-900 Power SupplyDesign Seminar Manual, Unitrode IntegratedCircuit Corporation

0::!]-O/DO Oonvel1er 2-24


25/26

[14] Lo Balogh, "The New UC3879 Phase ShiftedPWM Controller Simplifies The Design OfZero Voltage Transition Full BridgeConverters", Application Note U-154,Unitrode Integrated Circuit Corporation

[15] "UC3907 Load Share Controller", Data Sheet,Unitrode Integrated Circuit corporation,Product & Applications Handbook 1995-96,ppo 6-419 -6-424

[6] L. Balogh, R. Redl, D. W. Edwards, "OptimumZVS Full Bridge DC/DC Converter With PWMPhase-Shift Control: Analysis, DesignConsiderations, And Experimental Results",APEC '94 Proceedings, pp. 159-165

[7] R. Redl, L. Balogh, N. 0. Sokal, "A Novel Soft-Switching Full Bridge DC/DC Converter:Analysis, Design Considerations, AndExperimental Results At 1.5 kW, 100 kHz",PESC '90 Proceedings, pp. 162-172

[8] W. M. Andreycak, "Designing A Phase ShiftedZero Voltage Transition (ZVT) PowerConverter", Topic 3, SEM-900 Power SupplyDesign Seminar Manual, Unitrode IntegratedCircuit Corporation

[9] 0. D. Patterson, D. M. Divan, "Pseudo-reso-nant Full Bridge DC/DC Converter", PESC '87Proceedings, pp. 424-430

[10] G. Moschopoulos, et al, "A Fixed FrequencyZVS High Power SMR Converter With ZeroTo Rated Load Variation Capability", INT -ELEC '92 Proceedings, pp. 351-358

[11] "UC3879 Phase-Shift Resonant Controller",Data Sheet, Unitrode Integrated CircuitCorporation, Product & ApplicationsHandbook 1995-96, pp. 6-357 -6-361

[12] L. H. Dixon, "Power Transformer Design ForSwitching Power Supplies", SEM-100 PowerSupply Design Seminar Manual, UnitrodeIntegrated Circuit Corporation (reprinted insubsequent Seminar Manuals)

[13] L. H. Dixon, "Design Of FlybackTransformersAnd Filter Inductors", SEM-400 Power SupplyDesign Seminar Manual, Unitrode IntegratedCircuit Corporation (reprinted in subsequentSeminar Manuals)

[1!]- 2-25 DC/DC Converter


26/26

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