IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006 2077

A 120-MHz–1.8-GHz CMOS DLL-Based ClockGenerator for Dynamic Frequency Scaling

Jin-Han Kim, Student Member, IEEE, Young-Ho Kwak, Student Member, IEEE,Mooyoung Kim, Student Member, IEEE, Soo-Won Kim, and Chulwoo Kim, Senior Member, IEEE

Abstract—A delay-locked loop (DLL)-based clock generatorfor dynamic frequency scaling has been developed in a 0.35- mCMOS technology. The proposed clock generator can generateclock signals ranging from 120 MHz to 1.8 GHz and change thefrequency dynamically in a short time. If the clock generator scalesits output frequency dynamically by programming with the samelast bit, it takes only one clock cycle to lock. In addition, the clockgenerator inherits advantages of a DLL. The proposed DLL-basedclock generator occupies 0.07 mm2 and has a peak-to-peak jitterof 6.6 ps at 1.3 GHz.

Index Terms—Clock generator, delay-locked loop (DLL), DLL-based frequency multiplication, fast lock, low jitter.

I. INTRODUCTION

COMPARED to most phase-locked-loop (PLL)-based clockgenerators and local oscillators [1]–[9], delay-locked loop

(DLL)-based counterparts exhibit less jitter and phase noise be-cause of no jitter accumulation. This is true even under severesupply noise which is becoming common and critical in manySoCs. Furthermore, they show stable operation with process,voltage and temperature (PVT) variations, are easier to design,and occupy smaller area due to a simpler loop filter [10]–[13].Recently, several DLL-based clock generators and a local oscil-lator have been proposed to overcome the difficulty of frequencymultiplication with DLLs and utilize the several inherent ad-vantages of DLLs over PLLs [10]–[14]. The DLL-based localoscillator for PCS applications consumes large power and areaand the frequency multiplication factor cannot be changed oncethe LC-tank value is chosen [10]. The frequency synthesizer in[11] multiplies input clock frequency by a fixed multiplicationfactor, 9, and generates a 1-GHz off-chip clock signal with anexternal 50- pull-up resistor [11]. The multiplying DLL pro-posed in [12] uses multiplexers (MUXes) which cause jitter dueto a fixed supply voltage. In addition, the duty cycle of the fre-quency multiplied output clock is not 50% which is requiredin many high-performance applications. The DLL-based clockgenerator proposed in [13] provides a low-jitter on-chip clocksignal with a variable multiplication factor. Its frequency-mul-tiplied output clock has a 50% duty cycle even with a non-50%duty cycle input. It also overcomes the limited locking range

Manuscript received August 24, 2005; revised April 20, 2006. This workwas supported by Grant R08-2003-000-10899-0 from the Basic Research Pro-gram of the Korea Science and Engineering Foundation and IT-SOC PromotionGroup.

The authors are with the Department of Electronics Engineering, Korea Uni-versity, Seoul 136-713, Korea (e-mail:ckim@korea.ac.kr).

Digital Object Identifier 10.1109/JSSC.2006.880609

of DLLs. However, large internal node capacitances of the fre-quency multiplier limit the operating speed of the clock gen-erator. Finally, the multiplying DLL (MDLL) in [14] was pro-posed to be highly integrated in clock and data recovery unit,of which the high-frequency portion of jitter can be filtered outby injection locking using a slave oscillator. The multiplicationfactor of the MDLL can be changed from 1 to 10.

In this paper, a DLL-based clock generator is demonstratedin a 0.35- m CMOS technology. The proposed clock generatorcan multiply input frequency dynamically, which enables dy-namic voltage scaling and can increase the maximum operatingfrequency owing to the proposed frequency multiplier. The pro-posed frequency multiplier has small internal node capacitancesand is controlled by simple enabling logic circuits. As a result,the generator can operate from 120 MHz to 1.8 GHz with var-ious input signals and multiplication factors. Hence, the pro-posed clock generator can be used in clock and data recoveryapplications or in a dynamic frequency scaler in microproces-sors, which needs a fast lock during frequency change.

This paper is organized as follows. Section II brieflyoverviews the architecture of proposed frequency multiplier.Section III presents the circuit implementation of the frequencymultiplier concretely. The proposed frequency multiplierconsists of transition detector and edge-combiner. Section IVdescribes the operation of DLL-based clock generator using theproposed frequency multiplier for dynamic frequency scaling.Experimental results, die photo, and performance comparisonsto previous works are shown in Section V.

II. ARCHITECTURE OF PROPOSED FREQUENCY MULTIPLIER

To overcome the problems of conventional DLL-based clockgenerators, we have proposed a new one. The key idea ofthe proposed DLL-based clock generator is shown in Fig. 1.The architecture of the proposed DLL-based clock generatorfeatures a programmable multiplication factor controller anda high-frequency frequency multiplier. The buffered outputsof the voltage-controlled delay line (VCDL) are applied to theinputs of the frequency multiplier. The multiplication factorcontroller generates select signals for both the MUX and thetransition detector. Appropriate phases for DLL locking areselected by the MUX. Whenever each buffered VCDL outputrises, the transition detector generates a short period pulse,as shown in Fig. 2. The edge combiner puts the short pulsestogether and toggles the phase of output at every negativeedge of the short pulses. Thus, the multiplier output clocksignal toggles at every rising edge of signal . Fig. 2 showsan example of frequency multiplication by two. Even thoughthe duty cycle of signals is not 50%, the output clock signal

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2078 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006

Fig. 1. Block diagram of DLL-based clock generator.

Fig. 2. Waveforms of frequency multiplication by two.

does toggle at 50% duty cycle because each virtual pulse isgenerated at every rising edge of the signals. If the VCDLhas delay cells, then the output clock frequency can beexpressed as

(1)

where is the frequency of the reference signal and themultiplication factor can be chosen dynamically by themultiplication factor controller.

III. CIRCUIT IMPLEMENTATION OF FREQUENCY MULTIPLIER

To enhance the operating frequency of the frequencymultiplier while maintaining dynamic programmability, thefrequency multiplier is proposed as shown in Fig. 3. The circuitimplementation of each block is as follows. First, the transitiondetector consists of three inverters and a three-input NAND

gate as shown in Fig. 3. Enable signals ( ) for adjusting themultiplication factor are fed to the NAND gates. Each bufferedVCDL output ( ) is then fed to a NAND gate and three invertersat the same time. If signal rises, one input of a NAND gate

Fig. 3. Block diagram of proposed frequency multiplier (�4).

Fig. 4. Simulated waveform which shows the signal propagation failure at1.6 GHz without signal ordering in the edge-combiner.

will arrive faster than the other which comes after three-inverterdelay. As a result, at the rising edge of output of buffer, theNAND gate generates the negative narrow pulse correspondingto the three-inverter delay. Second, the edge-combiner consistsof symmetric NANDs, inverters, and a toggle pulsed latch (TPL).The negative pulses are transferred through three stages oftwo-input AND gates which is constructed by a symmetricNAND and an inverter. Node A results in an AND operation ofthe negative pulses. Therefore, whenever any buffered VCDLoutput feeds the transition detector, a short pulse is generatedat node A. Finally, the TPL toggles its output signal as longas the negative pulse is generated at node A. If a pulse signalpropagating through the edge combiner arrives at a certaininternal node during the transition time of a previous pulsesignal, a malfunction may occur, which limits the operationfrequency of the edge combiner. To prevent this problem,the number of fan-in of a symmetric NAND gate is limited totwo. In addition, outputs of the transition detector are pairedto guarantee maximum pulse separation as shown in Fig. 3,which reduces signal transition overlap and increases the op-erating frequency of the frequency multiplier by 15%. Fig. 4shows the failing case when the transition detector outputsare connected without signal ordering to the edge combiner.If two pairs of adjacent inputs, ( and ) and ( and ),feed to NAND gates and , respectively, overlap betweenadjacent signals reduces the voltage levels of nodes x and y.In the same manner, voltage reduction and overlap in nodes xand y results in voltage level degradation of node i. As a result,

KIM et al.: A 120-MHZ–1.8-GHZ CMOS DLL-BASED CLOCK GENERATOR FOR DYNAMIC FREQUENCY SCALING 2079

Fig. 5. Edge-combiner circuits. (a) Symmetric NAND. (b) TPL.

Fig. 6. Detailed block diagram of DLL-based clock generator.

pulses at node A are not generated properly. Fig. 5 shows thecircuit implementation of edge-combiner. Each component wascontrolled by the regulated supply for supply noise suppression.A pull-down path of a symmetric NAND gate is divided intotwo paths and input connections are switched for symmetricshort propagation. The operation of TPL is as follows. Duringthe short pulse width, the nMOS pass transistor turns on andtransmits input data ( ) to output. Furthermore, the output isinverted and fed back to input data until next pulse is triggered.Consequently, TPL can be considered a toggle-edge-triggeredflip-flop. The pMOS transistor (M1) of TPL prevents internalnode X from voltage drop of . Also, it provides a negativesetup time when input data changes from logic “Low” to logic“High”. The increased size of the nMOS pass transistor canhave a better drive strength at node X than the equivalent sizeof transmission gate. Thus, the total propagation time throughTPL determines the maximum frequency of the frequency mul-tiplier. Because data transfers through only an nMOS transistorand three inverters, the frequency multiplier maintains dynamicfrequency programmability and operates at high frequencycompared to the frequency multiplier in [4], which suffers fromlarge internal node capacitance.

IV. DLL-BASED CLOCK GENERATOR

Fig. 6 shows the overall block diagram of the frequencymultiplier for dynamic frequency scaling. The proposed

Fig. 7. Schematics of (a) charge-pump circuit, (b) charge-pump bias circuit,and (c) voltage regulator.

DLL-based clock generator was implemented in a 0.35- msingle-poly four-metal CMOS process with a 3.3-V supply.The phase detector (PD) with reset circuitry has increased thelocking range by initial condition as proposed in [12]. Thelock range for the DLL is from 240 to 500 MHz. A chargepump with replica bias controls the charge pump current foradaptive bandwidth. Schematics of a charge pump and its biascircuit are shown in Fig. 7. The charge pump is similar to thatintroduced in [15] and can make the voltages of nodesand n1 equal. Then the offset is canceled. The bias current iscontrolled by the last bit, which was compared through PDas shown in Fig. 7(b). The bandwidth is determined by theVCDL gain ( ) and charge pump current. The VCDL gainis inversely proportional to charge pump current. Therefore,as the position of the last bit decreases, the VCDL gain willbe reduced, and the charge pump current should be reduced tomaintain the bandwidth. Delay of VCDL is controlled by theregulated supply voltage. The regulator consists of a two-stagecurrent mirror as shown in Fig. 7(c) [16]. The bandwidth of theregulator was controlled by the bias voltage of . Thus, theregulated voltage swing results in the adaptive bandwidth ac-cording to input frequency and independent of the supply noise.Finally, there are the MUX and the frequency multiplier. TheMUX selects the last bit which connects to the PD accordingto the control signal. Hence, the selected number of delaycell outputs determines the maximum frequency of multipliedoutput by (1). For example, if the multiplication factor is 3 in

2080 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006

Fig. 8. Dynamic frequency multiplication example, where D represents“disable”.

Fig. 8, the MUX selects the output of the sixth tap as the last bitand the number of delay cell is six. The maximum frequencyof multiplied output is input frequency . In addition, ifthe multiplication factor controller enables the first, third, andfifth transition detectors, the frequency of the multiplied outputwill be halved: input frequency . Therefore, when thefrequency multiplier scales its output frequency dynamically byprogramming with the same last bit, it takes only one cycle timefor locking, which is critical for dynamic power managementfor system-level power reduction. Other combinations markedin gray in Fig. 8 can be chosen, but in those cases, some cycletime is wasted before the multiplied output clock is generated.For example, if the multiplication factor is changed from 1 to2 with the last bit of 8 and the multiplication factor controllerenables the second transition detector instead of the third, thefirst multiplied pulsewidth is narrower than desired and shouldbe discarded.

To reduce static phase offset and mismatch of delay path, thereplica bias charge pump and dummy delay cells in the VCDLare used. Furthermore, a symmetric NAND gate is used in thephase detector and layout of the proposed clock generator wascarefully done to reduce mismatch.

V. EXPERIMENTAL RESULT

Input and output waveforms of the frequency multiplierare shown in Fig. 9. The measured waveforms of Fig. 9 showa 1.3-GHz frequency multiplier output from an input refer-ence frequency of 325 MHz, giving a multiplication factor offour. The measured sinusoidal input signal is the output ofa signal generator which feeds the device under test (DUT).

Fig. 9. Input and multiplied output.

Fig. 10. Jitter histogram of the output.

Fig. 11. Dynamic frequency scaling example (from 1.6 GHz to 400 MHz andthen to 800 MHz).

Inside the chip, the sinusoidal input signal becomes a squarewave after passing through several buffers and then feeds theDLL-based clock multiplier. The measured output waveformlooks triangular due to the weak driving capability of the outputdriver. The measurement result with a quiet supply shows

KIM et al.: A 120-MHZ–1.8-GHZ CMOS DLL-BASED CLOCK GENERATOR FOR DYNAMIC FREQUENCY SCALING 2081

Fig. 12. Performance comparison of the DLL-based frequency multipliers.

Fig. 13. Die photo.

peak-to-peak jitter of 6.6 ps and rms jitter of 1.8 ps in Fig. 10.Fig. 11 shows that the frequency multiplier output changesfrom 1.6 GHz to 400 MHz and then to 800 MHz with one cyclelock time. The minimum and maximum multiplied output fre-quencies are 120 MHz and 1.8 GHz with input frequencies of240 MHz and 450 MHz, respectively. The triangles in Fig. 12are simulated maximum operating frequency of the proposedmultiplier featuring programmability for dynamic frequencyscaling. The proposed clock multiplier increases the operatingfrequency significantly in a given technology as shown inFig. 12. The clock generator die photo is shown in Fig. 13.The clock generator occupies 0.07 mm in a 0.35- m CMOSprocess. The performance of the implemented clock generatoris summarized in Table I.

TABLE IPERFORMANCE SUMMARY

VI. CONCLUSION

In this paper, a DLL-based clock generator for dynamic fre-quency scaling was proposed. This clock generator has beendesigned in a 0.35- m CMOS process and could increase themaximum operating frequency owing to the proposed frequencymultiplier. The proposed frequency multiplier has small internalnode capacitances and was controlled by simple enabling logiccircuits. As a result, the generator can operate from 120 MHzto 1.8 GHz with various input signal and multiplication factors.Since the multiplied output was made from each rising inputsignal, output signal maintain 50% duty cycle ratio independentof duty cycle ratio of the input signal. In addition, with plain dig-ital logic for frequency adjustment, the multiplication factor canbe changed dynamically with fast lock time. In case of the samelast bit, it takes only one-cycle to lock during frequency scaling.Since the DLL includes the voltage regulator and replica bias,the generator can suppress the supply noise and have adap-tive bandwidth. The implemented DLL-based clock generatorshows that for a reference signal of 325 MHz and a multipli-cation factor of four, the measured peak-to-peak cycle-to-cyclejitter is 6.6 ps at 1.3 GHz. The proposed clock generator canbe used in clock and data recovery applications or in dynamic

2082 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006

frequency scalers for low-power microprocessors which need afast lock during frequency change.

REFERENCES

[1] I. W. Young, J. K. Greason, and K. L. Wong, “A PLL clock generatorwith 5 to 110 MHz of lock range for microprocessors,” IEEE J. Solid-State Circuits, vol. 34, no. 11, pp. 1599–1607, Nov. 1992.

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Jin-Han Kim (S’04) received the B.S. and M.S. de-grees in electronics engineering from Korea Univer-sity, Seoul, Korea, in 2002 and 2005, respectively,where he is currently working toward the Ph.D. de-gree in electronics and computer engineering.

His research interests are in PLL/DLL design forhigh-speed communications and panel display driverIC design.

Mr. Kim was the recipient of the IEEE Seoul Sec-tion Student Paper Contest Award in 2004.

Young-Ho Kwak (S’04) received the B.S. degreein electronics engineering from Korea University,Seoul, Korea, in 2004, where he is currently workingtoward the Ph.D. degree in electronics and computerengineering.

His research interests are in clock and data re-covery for high-speed communications, high-speedserial link, and PLL design.

Mr. Kwak was the recipient of the IEEE Seoul Sec-tion Student Paper Contest Award in 2005.

Mooyoung Kim (S’04) received the B.S. degreein electrical computer engineering from KoreaUniversity, Seoul, Korea, in 2004, where he iscurrently working toward the Ph.D degree in the areaof integrated circuits and systems.

His research interests include mixed-mode circuitand system design.

Soo-Won Kim received the B.S. degree in electronicsengineering from Korea University, Seoul, Korea, in1974, and the M.S. and Ph.D. degrees in electrical en-gineering from Texas A&M University, College Sta-tion, in 1983 and 1987, respectively.

He joined the Department of Electronics Engi-neering at Korea University as an Assistant Professorin 1987. Since 1989, he has been a Professor inDepartment of Electronics Engineering at KoreaUniversity, Korea. His research area is in designof mixed mode IC, RF PLL, and high-speed and

low-power digital systems.

Chulwoo Kim (S’98-M’02-SM’06) received theB.S. and M.S. degrees in electronics engineeringfrom Korea University, Seoul, Korea, in 1994 and1996, respectively, and the Ph.D. degree in electricaland computer engineering from the University ofIllinois at Urbana-Champaign in 2001.

While at the University of Illinois, during1997–2000, he was a research assistant with theCoordinated Science Laboratory. In 1999, he alsoworked as a summer intern at the Design Technologyat Intel Corporation, Santa Clara, CA. In May

2001, he joined IBM Microelectronics Division, Austin, TX, where he wasinvolved in Cell processor design. Prior to joining IBM, he was a ResearchStaff Member with the University of California, Santa Cruz, CA, in 2001.Since September 2002, he has been with the Department of Electronics andComputer Engineering, Korea University, where he is currently an AssistantProfessor. His current research interests are in the areas of wireline transceiver,high-speed I/O, PLL/DLL, dynamic power management, and network on chip.

Dr. Kim received the HumanTech Thesis Contest Bronze Award from Sam-sung Electronics Corporation (1996), the International Low-Power Design Con-test Award at the IEEE International Symposium on Low-Power Electronics andDesign (2001), the Design Automation Conference (DAC) Student Design Con-test Award (2002), and Semiconductor Research Corporation (SRC) InventorRecognition Award (2002).