division of circuits and systems - ntu eeeisfet sensory system dedicated to precision ph sensing...

SYSTEMS

Division of CIRCUITS AND

29DIVISION OFCIRCUITS AND

SYSTEMS

[ Nanyang Technological University • School of Electrical & Electronic Engineering ]

INTRODUCTIONINTRODUCTION

he continuous growth in integrated circuit (IC) and electronic design activities in Singapore has resulted in excellent student enrolments in the Division’s fi nal year electronics option as well as the IC Design Specialist Manpower Programme (SMP) and NTU-TUM MSc Course in IC Design. Besides playing a leading role in IC design manpower training for the nation’s expanding electronics and IC design industries, the division has also performed extremely well in research.

On 12th January, the division signed an agreement with Advanced RFIC (aRfi c) Pte Ltd to set up the $9 million new research laboratory, Advanced RFIC@NTU. The collaboration aims to advance research and development in RFIC technology. The new research laboratory contains state-of-the-art equipment, including a world-class 300 mm probe system that makes modelling, measurement and characterization of nano-RF devices as well as integrated circuits and systems possible. Thirty postgraduate scholarships have also been set aside to expand the research activities in RFIC design.

On 4th September, NTU established the Institute for Sustainable Nanoelectronics (ISNE), a new initiative led by the division. The ISNE aims at designing and developing the next generation of embedded IC chips which consume signifi cantly less energy with low production costs. The ISNE has received a seed funding of $4 million to kick off its research activities. The ISNE strategy will be led by Professor Krishna Palem of Rice University, who is also the Canon Visiting Professor at NTU. To offi cially launch the ISNE, an inaugural workshop was held on 29th October with many internationally renowned nano-electronics researchers

T sharing their latest research with NTU researchers. NTU aims to build the ISNE into an international centre of excellence in fi ve years and our colleagues have, to date, participated actively in 6 projects to be funded by the ISNE.

On 7th September, another new research laboratory led by the division, the $10 million Electromagnetic Effects Research Laboratory (EMERL) set up jointly with DSO National Laboratories, was officially opened by the Defence Minister, Mr Teo Chee Hean. The Semi-Anechoic Chamber and the Reverberation Chamber in the EMERL allow advanced Electromagnetic Compatibility (EMC) measurement for any electronic system up to 40 GHz. With the worldwide trend of imposing EMC regulations on practically all electronic devices, the setting up of the EMERL is timely for the division to play a key role to spearhead advanced EMC research that seeks to ensure that electronic devices and systems are well designed with low electromagnetic emission, as well as high electromagnetic immunity.

Our colleagues have also done very well in securing research funding from both public and private sectors, such as Panasonic Semiconductor, Chartered Semiconductor, SINO-American Silicon Products, ST Microelectronics, A*STAR, DSTA and DSO National Laboratoreis. The total funding secured is close to $4 million, covering research areas in VLSI, RFIC, Reliability and EMC, which are in line with our division’s long-term research capability in System-on-Chip (SoC). A CRP research proposal from our colleagues has also been shortlisted by NRF despite keen

competition at the international-level.

MOU signing for the setting up of Advanced RFIC@NTU

Defence Minister, Mr Teo Chee Hean (4th from the left) unveiling the commemorative plaque at the EMERL opening ceremony


30 DIVISION OFCIRCUITS ANDSYSTEMS

620μm

400μm

GND VDD GND

GND OUT GND Vcont

Highlights of Research Activities

With all these newly added research facilities, research

initiatives and a strong research team, the division is well

positioned to build up System-on-Chip (SoC) capability

for the realization of many SoC systems. Amongst these

are Software Defi ned Radio (SDR) systems that can be

easily confi gured to operate at many existing and future

worldwide air-interface standards, and ultimately to become

the universal mobile communication system.

In this report, the division would like to highlight some of its

research achievements.

One main component in microwave receivers is the

Voltage-Controlled Oscillator (VCO). The unity frequency

ft, the frequency where the transistor current gain becomes

unity for 0.18μm, is about 40 GHz for optimum biasing. In

a circuit with large biasing swing like a VCO, ft can be as

low as 15 GHz. This proves to be a major problem for VCO

design as the VCO needs to work at 24 GHz. In addition,

other parameters such as tuning range and phase noise

could be greatly affected by the low unity frequency. The

division has developed a VCO with an oscillation frequency

of 23 GHz using a CMOS transistor with ft of 15.8 GHz.

Based on the 0.18μm CMOS process, our colleagues

demonstrated that using novel push-pull buffer, a VCO can

operate up to almost double the unity frequency.

IC Reliability is another important aspect of IC design,

especially with the continuous reduction in line width

and the increase in the number of metallization layers.

Our colleagues have developed a physical model of the electromigration that allows accurate prediction the failure sites for interconnects with different line widths and structures under various stress conditions. With the model, different

categories of failure mechanisms can be predicted for

failure analysis.

High-speed Digital Signal Processing (DSP) is a dedicated

module that has to cope with the complexity and diverse

processing requirements and specifi cations of different

SoC systems. Traditional techniques for multiplierless

fi ltering involve optimizing the digital fi lter coeffi cients in

signed power-of-two (SPT) coeffi cient space, and thus the

coeffi cient multiplications are replaced by additions and

shifts. However, the design of digital fi lters with discrete

coeffi cient values may not always be possible in some

applications such as in adaptive fi ltering. The division has

developed a new technique where signals are converted

into a sum of a limited number of SPT terms. Since hardware

circuitry for the real time conversion is available, the fi lter

is also multiplierless even though the coeffi cient values are

not SPT. The new technique can handle very complex signal

processing needs with low power consumption.

Microphotograph of the 23-GHz VCO


SYSTEMS


Near-fi eld electromagnetic scanning results indicating hot-spot areas that are causing SI/EMC problems

a b

4.54x1027

e-flow

3.75x1029 7.46x1029

1.90x1029 5.61x1029 9.32x1029

MaxVoidM2dummy line

(a) FIB-SEM image of failed sample, (b) total AFD distribution at M1 test condition.

Comparison of quantization error of the new technique (solid lines) and the measured results (histogram plots)

With high-speed electronic systems operating at sub-nano

second edge rates, board-level integration becomes a

very challenging task. The interconnects begin to behave

as transmission lines. In addition, parasitic effects due to

inter-layer vias, interconnect bends and gaps in ground

plane, start to show their impacts on circuit performance

at these edge rates. Hence, Signal Integrity (SI) and EMC

are becoming major issues for high-speed board design.

The SI and EMC issues, if not properly resolved, will lead to

unstable and intermittent operation problems. The research

group in EMERL has done extensive research work and

developed a systematic design methodology in SI/EMC

compliant high-speed designs.



CENTRE FOR INTEGRATED CIRCUITS AND SYSTEMS

20-GHz High-FrequencyCMOS T/R Switch IC Design

Its novel design supports a wide range of wireless

applications that require broadband and high frequency.

The layout technique for switch transistor overcomes

drawbacks due to drain-source interconnections. The

series-only topology saves chip area and reduces design

complexity. The double-well body-floating technique

overcomes drawbacks of excessive chip area in LC-

tuned techniques. The switched body-floating technique

overcomes the negative effects of body-floating

techniques. The differential topology improves power

handling capability and offers better signal quality.

OBJECTIVE

A novel IC design method and topology for CMOS Transmit/Receive switch design towards wideband and 20-GHz high frequency applications have been invented.

he Centre for Integrated Circuits & Systems (CICS) has 18 active full-time academic staff, 4 Research Fellows, 10 Research Associates, 3 Project Offi cers and 14 Technical Staff. Its research activities are focussed in three areas, namely RF Integrated Circuits and Systems, Analog/Mixed-Signal IC, and VLSI Design and Embedded Systems, with academic staff strengths of 5, 7, and 5 respectively. Most projects concern the design and analysis of devices, circuits and sub-systems of the fi nal SoC (System on Chip) products, with or without the embedded software. The RF Integrated Circuits and Systems group has 5 academic staff, 6 research staff and 23 research students. Its research focuses on RF IC design for wireless & mobile communications, RF modelling and characterization for deep sub-micrometer semiconductor devices, on-wafer interconnects and coupling, RFIC testing, ultra high speed clock-data-recovery, RF System-on-Chip, RF System-in-Package, Integrated Circuit Package Antenna, and EMC/EMI in RF integrated circuits and systems. At present there

T are 6 on-going research projects with an aggregate funding of some $2 million, the major part of the funding comes from external sources. The major research strengths of the group are Ultra Low Power RFIC designs for wireless, mobile and biochips applications. The research activities of the Analog/Mixed-Signal IC group are focussed on data converters, low-voltage low-power mixed signal circuits, and high-performance asynchronous digital signal processors. This group currently has a total research funding of some $2 million. In VLSI Design and Embedded Systems, the research activities cover a diversity of topics pertaining to the development of novel algorithms, effi cient hardware architectures and design methodologies towards VLSI and embedded application solutions. The group has 2 major projects with a funding of $700,000.

Some of the major projects and signifi cant achievements are described below.

A 20-GHZ CMOS T/R Switch


SYSTEMS


Intelligent ISFET Sensory Systemfor Water Quality Monitoring

Low Power Low Voltage8 Bit 200 MS/s Pipelined ADC

Using semiconductor theory and innovative circuit design

technique, a novel readout IC has demonstrated that

temperature compensation can be accomplished without

temperature sensor. Further incorporating generic time-

The achievement of high speed and ultra low power operation (200 MS/s @ 22 mW) sets a new benchmark in ADC design. The design uses a novel mixed-mode sampling and holding technique which reduces signal swings in the pipelined ADC while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the op amp gain, slew rate, bandwidth and capacitor matching requirements in pipelined ADCs. Thus, single stage op amps and small capacitor sizes can be used in this pipelined ADC, leading

OBJECTIVE

This project is to research a new intelligent ISFET sensory system dedicated to precision pH sensing function, along with long-term monitoring capability for water quality monitoring in environmental applications whilst not jeopardizing the accuracy by any temperature and time fl uctuations.

OBJECTIVE

The ADC was designed for applications in broadband wireless communications and optimized for IEEE 802.11 standards.

to a high speed and low power consumption. The linearity of the ADC is also improved due to the reduced signal swing. The performance of the ADC is summarized in Table 1. Table 1. Performance Summary

variant compensation algorithm together with hardware and

software co-design, the sensing performance of the readout

IC is signifi cantly enhanced even using standard ISFET

sensing device.

Technology 0.18 μm 2P6M CMOSResolution 8 bitsSampling Rate 200 MS/sSupply Voltage 1.8VInput Range 0.8Vpp

DNL/INL 0.30 LSB / 0.34 LSBSNDR (ƒin = 40MHz) 45.2 dBSNDR (ƒin = 99MHz) 44.2 dBSFDR (ƒin = 40MHz) 60.4 dBSFDR (ƒin = 99MHz) 53.4 dBActive Area 0.8 mm x 0.4 mmPower Consumption 22 mW

A Low Power Low Voltage 8 bit 200 MS/s Pipelined ADC

An Intelligent ISFET Water Quality Sensory System



1st Row (From left to right) Head of DivisionYeo Kiat SengAssociate Professor

Deputy Head of DivisionSee Kye YakAssociate Professor

Assistant Head of DivisionGoh Wang LingAssociate Professor

ProfessorDo Manh Anh

2nd Row (From left to right)Associate ProfessorsChan Pak KwongChang Chip Hong

Chang, Joseph SylvesterAssociate Dean, College of Engineering(1 April 2006 - 31 March 2007)

Gwee Bah Hwee

3rd Row (From left to right)Associate ProfessorsHo Duan Juat Jong Ching ChuenKoh Liang Mong

4th Row (From left to right)Associate ProfessorsLam Ying Hung, Yvonne

Lau Kim TeenProgram Director,MSc (Consumer Electronics) MSc (IC Design)

Lim Meng Hiot

StaffMembers


SYSTEMS


1st Row (From right to left) Associate Professors

Ng Lian SoonOng Keng Sian, Vincent

Siek LiterTan Cher Ming

2nd Row (From right to left)Associate Professor

Zhang Yue Ping

Assistant ProfessorsBoon Chirn Chye

Tiew Kei TeeTan Meng Tong

3rd Row (From right to left)Assistant Professor

Yu Yajun

Teaching FellowsAlper CabukKong Zhi Hui

4th Row (From right to left)Associate Professorial Fellows

Chua Hong Chuck@Chua Hong Chuek

Ooi Tian Hock@Wei Ten Fook

Wong Mong Chung, EddieTang Hung Kei

StaffMembers



ResearchInterest

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

Boon Chirn Chye

Chan Pak Kwong

Chang Chip Hong

Chang, Joseph Sylvester

Chua Hong Chuck

Do Manh Anh

Goh Wang Ling

Gwee Bah Hwee

Ho Duan Juat

Jong Ching Chuen

Koh Liang Mong

Lam Ying Hung, Yvonne

Lau Kim Teen

Lim Meng Hiot

Ng Lian Soon

Ong Keng Sian, Vincent

Ooi Tian Hock

See Kye Yak

Siek Liter @ Hsueh Liter

Tan Cher Ming

Tan Meng Tong

Tang Hung Kei

Assistant Professor

Associate Professor

Associate Professor

Associate Professor

Associate Professorial Fellow

Professor

Associate Professor

Associate Professor

Associate Professor

Associate Professor

Associate Professor

Associate Professor

Associate Professor

Associate Professor

Associate Professor

Associate Professor


Associate Professor

Associate Professor

Associate Professor

Assistant Professor


RFIC Devices, Circuits and Systems Design, PLL Frequency Synthesizer Design, Biomedical Consumer Electronic.

Biomedical Circuits and Systems, Sensor Interfaces, Mixed-Signal Circuits and Systems.

Computer Arithmetic, VLSI Design, Design automation, Digital Signal Processing.

Acoustics, Audiology, Electronics, IC Design, Analogue and Digital Signal Processing, Biomedical Engineering, Pyschophysics.

High Density Multilayer PCB Design, System Integration (Noise & signal integrity), Embedded Systems for Security.

Biomedical Electronics, Digital Communications, R.F. Circuits and Systems, Acoustics.

Device Processing, Device Characterization, and IC Design.

Asynchronous & Digital Class-D Amplifier IC Designs, Acoustic Noise Reduction.

Video Coding, System Level Digital Design, ASIC Design.

High-Level Synthesis, Parallel Computation and Reconfigurable Systems.

Machine Vision, Energy Saving Electronic Converters.

Mixed-signal IC Design, Analogue Design Automation.

Low power IC Design, Self-timed CMOS Circuits, Subthreshold CMOS Circuits.

Computational Intelligence, Embedded Systems, AI in Finance, Fuzzy/neural Hardware, Combinatorial Optimization.

Analogue CMOS circuits, DAC/ADC, Micropower Circuits, Analogue Bipolar Circuits.

Materials and Device Characterization, Analysis and Modelling, Electron Beam Techniques, EBIC Metrology.

RF Circuits and Systems, ASIC, DSP in Consumer Electronics Applications, Factory Automation, Quality and Reliabilty, EMC/EMI/EMS.

Computational Electromagnetics, Electromagnetic Compatibility and Signal Integrity.

Low-power Low-voltage Analog/Mixed Signal CMOS/Bipolar IC Design.

Nanoelectronics, ULSI Interconnect Reliability, Wafer Bonding, Reliability and Maintenance Engineering.

VLSI Design, Class D Amplifiers, Analog and Digital Signal Processing, Biomedical Engineering.

Technopreneurship, Management of Innovation and Technology.

CIRCUITS AND SYSTEMS


SYSTEMS


ResearchInterest

PhD & MEngDegrees Awarded in 2007

23

24

25

26

27

Tiew Kei Tee

Wong Moon Chung, Eddie

Yeo Kiat Seng

Yu Yajun

Zhang Yue Ping

Assistant Professor


Associate Professor

Assistant Professor

Associate Professor

Analog and Mixed-signal IC Design, Delta-sigma Modulators, Bio-instrumentation.

Biomedical Instrumentation, Image Processing, Robotics And Automation, Digital Test Generation and DFT.

Device Modeling, RFIC Design, Low-voltage Low-power IC Design.

VLSI Digital Signal Processing, VLSI Circuits and Systems Design.

Wireless Chip Area Network, Single-chip Radio, and Radio Bioelectronics.

CIRCUITS AND SYSTEMS

1

2

3

4

5

6

7

8

9

10

11

12

13

Design and implementation of a reconfigurable fuzzy inference processor

Flicker noise fluctuations in deep submicron MOSFETs

Design and implementation of a low energy fast fourier transform/inverse fast fourier transform (FFT/IFFT) processor based on asynchoronous-logic

Performance analysis and integrated circuit design for ultra-wideband transceiver

Novel methodologies for miniaturized filter designs and realization

Dual band low-noise amplifier designs for bluetooth and hiperlan applications

Characterization and modeling of on-wafer interconnects for RFICs

Study of chip scale wireless interconnect systems and their antennas

Algorithms for synthesis and optimization of multiplierless FIR filters

New self-organizing algorithms for topological mapsi

Meta-heuristic algorithm development for combinatorial optimization within an integrated problem solving environment

Digital image enhancement algorithm for 2-D ultrasound imaging system

Speckle removal in medical ultrasound images by compounding and filtering

PhD - CIRCUITS AND SYSTEMS

Lim Meng Hiot

Yeo Kiat Seng

Gwee Bah HweeChang, Joseph Sylvester

Zhang Yue Ping

Yeo Kiat SengMiao Jianmin

Yeo Kiat Seng

Yeo Kiat SengLi Erping

Zhang Yue PingGuo Lihui

Jong Ching Chuen

Chang Chip Hong

Lim Meng Hiot

Koh Liang Mong

Wong Moon Chung, Eddie

Cao Qi

Chew Kok Wai, Johnny

Chong Kwen Siong

Li Qiang

Ma Kaixue

Mou Shouxian

Shi Xiaomeng

Sun Mei

Xu Fei

Xu Pengfei

Xu Yiliang

Zhang Fan

Zhang Lichen

PROJECT TITLE STUDENT SUPERVISOR/CO-SUPERVISORS/NO.

1

2

Fast finite field multipliers for public key cryptosystems

An integrated platform for design & verification of digital FIR filters

MEng - CIRCUITS AND SYSTEMS

Chang Chip Hong

Jong Ching Chuen

Satzoda Ravi Kumar

Sharma Udit

PROJECT TITLE STUDENT SUPERVISOR/CO-SUPERVISORS/NO.



SelectedPublications in 2007

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Aaron V. Do, C. C. Boon, M. A. Do, K. S. Yeo and A. Cabuk, "A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band", accepted, IEEE Trans. on Microwave Theory and Techniques, 2007.

K. M. Lim, C. Y. Ng, K. S. Yeo, M. A. Do and C. C. Boon, "A 2.4GHz Ultra Low Power Subthreshold CMOS Low-Noise Amplifier", Microwave and Optical Technology Letters, vol. 49, pp. 743 - 744, February 2007.

P. K. Chan and D. Y. Chen, "A CMOS ISFET Interface Circuit with Dynamic Current Temperature Compensation Technique", Special Issue on Smart Sensors, IEEE Trans. on Circuits and Systems, Part I, vol. 54, no. 1, pp. 119 - 129, January 2007.

J. Peng and P. K. Chan, "Analysis of Nonideal Effects on a Tomography-Based Switched-Capacitor Transducer", IEEE Sensors Journal, vol. 7, no. 3, pp. 381 - 391, March 2007.

J. K. Yin and P. K. Chan, "A Low-Jitter Polyphase Filter Based Frequency Multiplier with Phase Error Calibration", accepted, IEEE Trans. on Circuits and Systems, Part II, 2007.

F. Xu, C. H. Chang and C. C. Jong, "Design of Low-Complexity FIR Filters Based on Signed-Powers-of-two Coefficients with Reusable Common Subexpressions", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 1898 - 1907, October 2007.

Y. Shao and C. H. Chang, "A Generalized Time-Frequency Subtraction Method for Robust Speech Enhancement Based on Wavelet Filter Bank Modeling of Human Auditory System", IEEE Trans. on Systems, Man and Cybernetics, Part B: Cybernetics, vol. 37, no. 4, pp. 877- 889, August 2007.

B. Cao, C. H. Chang and T. Srikanthan, "A Residue-to-Binary Converter for a New 5-moduli set", IEEE Trans. on Circuits and Systems, Part I, vol. 54, no. 5, pp. 1041 - 1049, May 2007.

Z. H. Lu, K. S. Yeo, J. G. Ma, M. A. Do, W. M. Lim, and X. Y. Chen, "Broadband Design Techniques for Trans-impedance Amplifiers", IEEE Trans. on Circuits and Systems I, vol. 54, no. 3, pp. 590 - 600, March 2007.

X. P. Yu, M. A. Do, J. G. Ma, W. M. Lim, K. S. Yeo and X.L. Yan, "Sub-1V Low Power Wide Range Injection-Locked Frequency Divider", IEEE Microwave and Wireless Components Letters, vol. 17, no. 7, pp. 528 - 530, July 2007.

D. D. Chen, K. S. Yeo, M. A. Do and C. C. Boon,"A Fully Integrated CMOS Limiting Amplifier with Novel Offset Compensation Network", IET Electronics Letters, vol. 43, no. 20, pp. 1084 - 1085, September 2007.

H. Q. Liu, W. L. Goh, L. Siek, Y. P. Zhang and W.M. Lim, "A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator with Coarse and Fine Frequency Tuning", accepted, IEEE Trans. on Very Large Scale Integration Systems, 2007.

K. S. Chong, B. H. Gwee and J. S. Chang, "Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors", IEEE Journal of Solid State Circuits, vol. 42, no. 9, pp. 2034 - 2045, September 2007.

C. F. Chong, B. H. Gwee and J. S. Chang, "Asynchronous Control Network Optimization Using Fast Minimum Cycle Time Analysis", accepted, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2007.

K. S. Chong, B. H. Gwee, and J. S. Chang, "Design of Several Asynchronous-Logic Macrocells for a Low-Voltage Micropower Cell Library", IET Proc. Circuits, Devices and Systems, vol. 1, no. 2, pp. 161 - 169, April 2007.

A. Agarwal, M. H. Lim, M. J. Er and T. N. Nguyen, "Rectilinear Workspace Partitioning for Parallel Coverage using Multiple UAVs", Advanced Robotics, vol. 21, no. 1, January 2007.

Z. Z. Zhao, Y. S. Ong, M. H. Lim and B. S. Lee, "Memetic Algorithm using Multi-Surrogates for Computationally Expensive Optimization Problems", Soft Computing, 11(10), pp. 957 - 971, 2007.

J. Tang, M. H. Lim and Y. S. Ong, "Diversity-Adaptive Parallel Memetic Algorithm for Solving Large Scale Combinatorial Optimization Problems", Soft Computing, 11(9), pp. 873 - 888, 2007.

List of Selected Publications - CIRCUITS AND SYSTEMS


SYSTEMS


SelectedPublications in 2007

J. Deng and K. Y. See, "In-circuit Characterization of Common-mode Chokes", IEEE Trans. on Electromagnetic Compatibility, vol. 49, no. 2, pp. 451 - 454, May 2007.

K. Y. See, P. L. So and A. Kamarul, "Feasibility Study of Adding a Common-mode Choke in PLC modem for EMI Suppression", IEEE Trans. on Power Delivery, vol. 22, no. 4, pp. 2136 - 2139, October 2007.

C. M. Tan and A. Roy, "Electromigration in ULSI Interconnects", Materials Science and Engineering R, 58, 1 - 75, 2007.

C. M. Tan and Y. Hou, "Lifetime Modeling for Stress-induced Voiding in Integrated Circuit Interconnections", Appl. Phys. Lett., 91(6), 061904, 2007.

C. M. Tan and N. Raghavan, "A Framework to Practical Predictive Maintenance Modeling for Multi-State Systems", in press, Reliability Engineering and System Safety, 2007.

K. Ma, K.S. Yeo, J.G. Ma and M.A. Do, "An Ultra-compact Hairpin Band Pass Filter with Additional Zero Points," accepted, IEEE Microwave and Wireless Components Letters, 2007.

X. M. Shi, K. S. Yeo, J.G. Ma, M. A. Do and E. P. Li, "Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs," accepted, IEEE Trans. on Very Large Scale Integration Systems, August 2007.

K. Ma, K. S. Yeo, J. G. Ma, and M. A. Do, "An Ultra-Compact Planar Bandpass Filter with Open-ground Spiral for wireless Application," accepted, IEEE Trans. on Advanced Packaging, August 2007.

Q. Li and Y. P. Zhang, "A 1.5-V 2-9.6-GHz Inductorless Low-noise Amplifier in 0.13-μm CMOS," accepted, IEEE Trans. on Microwave Theory and Techniques, vol. 55, no. 10, pp. 2015 - 2023, October 2007.

A. Poh and Y. P. Zhang, "Design and Analysis of Transmit/Receive Switch in Triple-well CMOS for MIMO Wireless Systems", IEEE Trans. on Microwave Theory and Techniques, vol. 55, no. 3, pp. 458 - 466, March 2007.

Q. Li and Y. P. Zhang, "CMOS T/R Switch Design: Towards Ultrawide-band and Higher Frequency", IEEE Journal of Solid-State Circuits, vol. 42, no. 3, pp. 563 - 570, March 2007.

G. Moldovan, P. Kazemian, P. Edwards, V.K.S. Ong, O. Kurniawan and C.J. Humphreys, "Low-Voltage Cross-Sectional EBIC for Characterisation of GaN-Based Light Emitting Devices", Ultramicroscopy, vol. 107, no. 45, pp. 382 - 389, 2007.

O. Kurniawan and V.K.S. Ong, "Investigation of Range-Energy Relationships for Low Energy Electron Beams in Silicon and Gallium Nitride", accepted, Scanning, 2007.

Y. J. Yu and Y. C. Lim, "Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming", IEEE Trans. on Circuits and Systems, Part I, vol 54, no. 10, pp. 2330 - 2338, October 2007.

Y. C. Lim, Y. J. Yu, T. Saramäki and K. L. Teo, "FRM Based FIR Filters with Optimum Finite Word Length Performance", IEEE Trans. on Signal Processing, vol. 55, pp. 2914 - 2924, June 2007.

Y. J. Yu and Y. C. Lim, "Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms", IEEE Trans. on Signal Processing, vol. 55, pp. 2122 - 2135, May 2007.

List of Selected Publications - CIRCUITS AND SYSTEMS

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

division of circuits and systems - ntu eeeisfet sensory system dedicated to precision ph sensing...

Documents