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Page 1: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 1

Discrete Event Simulation

Page 2: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 2

• Scheme Language

• Simulation Overview

• DEVS formalism

• Basic model

• Experimental Frame

• Abstract Simulators

• Coupled model

Contents

Page 3: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 3

Simulation Overview

Page 4: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 4

Computer Simulation Components

MODEL

SIMULATOR

REAL or

PROPOSED

SYSTEM

source

of data

modeling simulation

set of instructions

program

execution of model

generates behavior

decision making

Page 5: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 5

Application Domains

Generally, complicated system that cannot be

expressed numerically (most of the artificial system).

Ex) Network, war, traffic, airport, manufacturing,

space station, . . .etc.

• Existing system : analysis, modification, extension,

testing alternative strategies

• Future system : design (including dynamics)

• Intelligent : control, planning, monitoring,..

Page 6: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 6

Simulation System Classification(1)

- Continuous (time) simulation

t0t

outputModel,

System

State

space

Time space

abstraction

t0t

input

Page 7: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 7

- Discrete (time) simulation

Model,

system

input output

s0

s1

s2

s3

s4

dtt0t

dt

t0t

dt

Simulation System Classification(2)

Page 8: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 8

- Discrete event simulation

Input event Output event

t0t t0

t

s0

s1

s2

s3

Model,

system

Simulation System Classification(3)

Page 9: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 9

Terminology

• State variables : the variables that represent

model’s situation (status)

• Model state : - models current status

- represented by the collection

of state variables

• Event : internal event (change of model state)

external input event,

external output event

Page 10: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 10

TerminologyExample: A single tank

State variables: number-of-crew, speed,

damage-status, bullet-remaining

cannon-diameter, total-weight, . . .

Model state: number-of-crew = 3, speed = 54km/h,

damage-status = none, bullet-remaining = 30 …

Event: hit by enemy, firing, breaking, . . .

Page 11: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 11

Bank system

System I

• purpose : observation of changes in customer-number

• event (external) input event : arrival of customer

internal event : change of customer number

(external) output event : departure of customer

Page 12: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 12

Bank system

• state variable : customer-number

t0 tf t0 tf

bank

Page 13: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 13

Bank system

System II

• purpose : observation of changes of customer-number

and changes of customer-in-queue

• event (external) input event : arrival of customer

internal event change of total-customer-number

transition from queue to teller

(external) output event : departure of customer

Page 14: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 14

Bank system

• state variable : total-customer-number

customer-in-queue

Input event Output event

bank

… ::

teller

:

queue

Page 15: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 15

performance evaluation

Standard measure: throughput,

turnaround time

• throughput :

total customer number

processed during a certain observation time

• (average) turnaround time :

(average) processing time per a person

Bank system

Page 16: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 16

ModelingModeling is Objective Driven

Based on the objective of the current simulation

a modeler decides the events.

Based on the events other modeling components

(including state variables) are designed and

programmed.

Page 17: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 17

DEVS formalism

Page 18: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 18

Representation of System

(Mathematical structure)

• arithmetic structure

< Ζ, + >

1, 2 ∈ Z 1+2=3

- numerical arithmetics

set of integer

Page 19: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 19

• finite-state machine

< X, S, Y, , λ >

▫ X : finite set of input symbols

▫ S : finite set of states

▫ Y : finite set of output symbols

▫ : next state function, state transition function

: S X → S

Representation of System

(Mathematical structure)

Page 20: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 20

▫ : output function

: S → Y

- sequential machine

Representation of System

(Mathematical structure)

Page 21: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 21

DEVS Formalism

• Discrete EVent system Specification

Basic Models

M = < X, S, Y, int , ext , , ta >

▫ X : Set of external input event types

▫ S : Sequential state set

▫ Y : Set of external event types generated as

output

Page 22: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 22

DEVS Formalism

▫ int : internal transition function

int : S → S

▫ ext : external transition function

ext : Q X → S

total state Q={(s, e) | s ∈ S, 0 ≤ e ≤ ta(s)}

Page 23: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 23

DEVS Formalism

▫ : output function

: S → Y

▫ ta : time advance function

ta : S → R0+

Page 24: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 24

State transition functionM is a small commercial vehicle (max capacity is 2)

X = {x1, x2 , x3}, S = {s0, s1, s2, s3}

x1, x2 , x3 : passenger id

s0: none, s1: 1 passenger, s2: 2 passenger, s3: moving

ext : (Q X) → S where, Q={(s,e) | s ∈ S, 0 ≤ e ≤ ta(s)}

s1 = ext ((s0,1),x1)

s3 = ext((s0,7),x1) ; waited too long in s0 , if any one

onboard then start moving.

int : S → S

s3 = int(s2) ; move after 1 minute of setup time at s2

(setup time needed only at s2)

Page 25: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 25

Basic ModelBasic Model contains the following information

• the set of input ports through which external events

are received

• the set of output ports through which external events

are sent out

• the set of state variables including

phase and sigma (default s.v.)

summary of a model state

next event schedule time

Page 26: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 26

Basic Model

• the time advance function that controls the timing

of internal transitions.

• output of the time advance function is determined

by the state variable “sigma”

Modeler => sigma => ta => int

• the internal state transition function that

determines the next state of the model

Page 27: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 27

Basic Model

• the external transition function which specifies how

the system changes state when an input is received

• the output function which generates an external

output just before an internal transition function is

executed

Page 28: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 28

ext : (define (ext s e x)

. . .

) ; s should be returned

int : (define (int s)

. . .

) ; s should be returned

Page 29: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 29

Basic Model

: (define (out s)

. . .

) ; y, output event should be returned

Page 30: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 30

P Model(1)

• model diagram

simple processor

Processing time T

Pinput output

Page 31: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 31

P Model (2)

• timing diagram

t

t

t

t

X

S

E

Y

s0s0 s0

s1 s1 s1

Xa Xb Xc

Ya Yb

ext ext extintint

T

45˚

T T

Yc

T

Page 32: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 32

P Model(3-1)

• model diagram

∞ passive ’( ) 5

P

in out

sigma phase job-id processing-time

default

Page 33: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 33

Phase: Summarizes the model state

Ex) Weather (How is the weather?)

phase = rainy, snowy, sunny, or cloudy

other possible state variables: humidity

pressure

wind-direction

wind-speed

precipitation

cloud-ratio

visuability

. . .

Page 34: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 34

P Model(3-2)

• timing diagram

t

t

t

X

S

Y g1

g1

passive busy passive

intext

in

out

(phase)

Page 35: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 35

P Model(3-3)

t

t

t

X

S

Y

g1

in

5 busy

3 2

2 = 5-3 = sigma-e

ext

continue sigma = sigma – e

phase = unchanged

(phase)

g1out

Page 36: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 36

P Model(4)

• state transition diagram

passive

busy

intext

in out

Page 37: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 37

P Model(5-1)• pseudo code

ext : external transition function

when receive x on port in

if passive then

begin

set job being processed := x

go to START

end

else

continue

START : hold-in (busy, processing-time)

Page 38: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 38

P Model(5-2)

int : internal transition function.

passivate : schedule the next internal event to t+∞

phase = passive

sigma = ∞

: output function

if busy then send job x to port out.

Page 39: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 39

Event Scheduling

start : Hold in (busy, p.t.)

t

event scheduling : Assigns values to sigma and phase.

As a result, the state trajectory until

the next event time is created.

p.t

ext

phase: passive => busy

sigma: inf => p.t.busy

passive

Page 40: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 40

P Model(6-1)

• model definition (code)

(make-pair atomic-models ’p)

(send p def-state

’(job-id

processing-time)

)

Page 41: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 41

Object Oriented View

(send obj2 function x1 )

Data

+

Function(x)

Data

+

Function(x)

obj1 obj2

Atomic-models: obj1, obj2

Page 42: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 42

(send p set-s

(make-state

’sigma ’inf

’phase ’passive

’job-id ’()

’processing-time 5

)

)

event

scheduling

P Model(6-2)

Page 43: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 43

P Model(6-2)

state : structure type

sigma phase job-id processing-time

s

sigma ’inf

phase ’passive

job-id ’()

processing-time 5

Page 44: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 44

P Model(6-3)(define (ext-p s e x)

(case (content-port x)

(’in (case (state-phase s)

(’passive

(set! (state-job-id s) (content-value x))

(hold-in ‘busy (state-processing-time s))

)

(’busy (continue) )

)

);in

);case

)

event scheduling

Page 45: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 45

P Model(6-3)

content : structure type

port value

x port ’in

value ’g1

Page 46: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab.

continue sigma = sigma-e

phase remains same as before

(define (int-p s)

(case (state-phase s)

(’busy (passivate))

)

)passivate sigma = inf

phase = passive

46

P Model(6-4)

Event scheduling

Page 47: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 47

P Model(6-5)(define (out-p s)

(case (state-phase s)

(’busy

(make-content ’port ’out ’value (state-job-id s)

)

(else (make-content))

);case

)

(send p set-ext-transfn ext-p)

(send p set-int-transfn int-p)

(send p set-outputfn out-p)

Never happen

Page 48: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab.

p Model timing diagram(7-1)

48

t0

t0

t0

2

g1

in

g1

out

λ

passive5

busyext

passive

int

𝑋

𝑆(𝑝ℎ𝑎𝑠𝑒)

𝑌

Page 49: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab.

p Model timing diagram(7-1)

t0

t0

t0

① (send p inject ’in ’g1 2) =>

arrival of input

execution of ext

state s = (5 busy g1 5)② (send p output?) =>

g1

out

λ

output y = out g1

state s = (∞ passive g1 5)

③ (send p int-transition) =>

passive

2

g1

in

5

busyext

passive

int

49

𝑋

𝑆(𝑝ℎ𝑎𝑠𝑒)

𝑌

initial state s = (∞ passive ( ) 5)

Page 50: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 50

P Model testing I (verification)initial state

sigma phase job-id pt

: ∞ passive ’() 5

e

① (send p inject ’in ’g1 2) => state s = (5 busy g1 5)

arrival of input

execution of ext

② (send p output?) => output y = out g1

③ (send p int-transition) => state s = (∞ passive g1 5)

Page 51: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab.

5busy

P Model timing diagram(7-2)

t0

2

g1in

t0

passive

ext

t0

g1out

λ

passive

int

3

g2in

2

ext

51

𝑋

𝑆(𝑝ℎ𝑎𝑠𝑒)

𝑌

Page 52: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab.

state s = (5 busy g1 5)state s = (2 busy g1 5)

P Model timing diagram(7-2)

t0

t0

2

g1

in

passive

t0

5

busyext

① (send p inject ’in ’g1 2) =>

arrival of input

execution of ext

② (send p inject ’in ’g2 3) =>

ext

3

g2

in2

y= out g1③ (send p output?) =>

g1

out

λ

④ (send p int-transition) =>

passive

int

52

𝑋

𝑆(𝑝ℎ𝑎𝑠𝑒)

𝑌

state s = (∞ passive g1 5)initial state s = (∞ passive ( ) 5)

Page 53: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 53

P Model testing II (verification)

initial state

sigma phase job-id pt

: ∞ passive ’() 5

① (send p inject ’in ’g1 2) => ’(5 busy g1 5)

arrival of input

execution of ext

② (send p inject ’in ’g2 3) => ’(2 busy g1 5)

③ (send p output?) => y= out g1

④ (send p int-transition) => ’(∞ passive g1 5)

Page 54: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 54

Devs-scheme

• directory structure

c:\ > scheme \ devs \ *.*

\ simparc \ mbase \ p.m

\ enbase \

c:\ > scheme \ devs \ airport \ mbase \ runway.m

\ contr-tower.m

\ enbase

Devs files

ᆞᆞᆞ

ᆞᆞᆞ

ᆞᆞᆞ

ᆞᆞᆞ

Page 55: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 55

Devs-schemec: \ > scheme \ devs \ simparc \ pcs

. . . wish help? (y/n) n . . .

[1](load “mbase \ p.m”)

o.k.

[2](send p inject ’in ’g1 3)

(5 busy g1 5)

[3] . . .

Dos commands: dir, cd <directory>, cd ..

Page 56: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 56

pq Model(1)

• model diagram

pq

in out

sigma phase job-id p.tqueue

default

∞ passive ’( ) ’( ) 10

Page 57: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab.

Busy 10Busy 10 Busy 10

passive passive

pq Model timing diagram

t0

6

g1in

t0

ext

t0

g1out

4 4

g2in

g3in

2

ext ext int int

g2out

g3out

int

57

𝑋

𝑆(𝑝ℎ𝑎𝑠𝑒)

𝑌

Page 58: Discrete Event Simulation - SKKU

Sungkyunkwan University

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Copyright (c) 2015 Intelligence Modeling Lab. 58

pq Model(2)

• state transition diagram

passive

busy

intext

in out

pq

int

Page 59: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 59

pq Model(3-1)• model definition (code)

(make-pair atomic-models ’pq)

(send pq def-state ’( job-id

queue

processing-time)

)

(send pq set-s

(make-state ’sigma ’inf

’phase ’passive

’job-id ’( )

’queue ’( )

’processing-time 10)

)

Page 60: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 60

pq Model(3-2)(define (ext-pq s e x)

(case (content-port x)

(’in (case (state-phase s)

(’passive (set! (state-job-id s) (content-value x))

(hold-in ’busy (state-processing-time s))

)

(’busy (set! (state-queue s)

(append (state-queue s)

(list (content-value x))

) )

(continue)

)

);case

);’in

) )

Page 61: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 61

pq Model(3-3)(define (int-pq s)

(case (state-phase s)

(’busy

(if (null? (state-queue s))

(passivate)

(begin

(set! (state-job-id s) (car (state-queue s)))

(set! (state-queue s) (cdr (state-queue s)))

(hold-in ’busy (state-processing-time s))

)

);if

)))

Page 62: Discrete Event Simulation - SKKU

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Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 62

pq Model(3-4)(define (out-pq s)

(case (state-phase s)

(’busy

(make-content ’port ’out ’value (state-job-id s))

)

(else (make-content))

)

)

(send pq set-ext-transfn ext-pq)

(send pq set-int-transfn int-pq)

(send pq set-outputfn out-pq)

Page 63: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab.

Busy 10Busy 10 Busy 10

passive passive

pq Model timing diagram(4)

t0

6

g1in

t0

ext

t0

g1out

4 4

g2in

g3in

2

ext ext int int

g2out

g3out

int

62

𝑋

𝑆(𝑝ℎ𝑎𝑠𝑒)

𝑌

Page 64: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab.

state s = (2 busy g1 (g2, g3) 10)state s = (10 busy g3 ( ) 10)y = out g3state s = (10 busy g2 (g3) 10)state s = (∞ passive g3 ( ) 10)

initial state s = (∞ passive ( ) ( ) 10)

passive

pq Model timing diagram(4)

t0

t0

6

g1in

t0

(send pq inject ’in ’g1 6) =>

state s = (10 busy g1 ( ) 10)

4

g2in

(send pq inject ’in ’g2 4) =>

state s = (6 busy g1 (g2) 10)

(send pq inject ’in ’g3 4) =>

4

g3in

ext ext

(send pq output?) =>

g1out

y = out g1

(send pq int-transition) =>(send pq output?) =>

y = out g2

g2out

(send pq int-transition) =>

Busy 10

int

2

int

Busy 10

(send pq output?) =>

g3out

(send pq int-transition) =>

Busy 10ext

passive

int

63

𝑋

𝑆(𝑝ℎ𝑎𝑠𝑒)

𝑌

Page 65: Discrete Event Simulation - SKKU

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Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab. 65

pq Model(5)• model test

(send pq inject ’in ’g1 6) => (10 busy g1 () 10)

(send pq inject ’in ’g2 4) => (6 busy g1 (g2) 10)

(send pq inject ’in ’g3 4) => (2 busy g1 (g2, g3) 10)

(send pq output?) => y= out g1

(send pq int-transition) => (10 busy g2 (g3) 10)

(send pq output?) => y= out g2

(send pq int-transition) => (10 busy g3 () 10)

(send pq output?) => y= out g3

(send pq int-transition) => (∞ passive g3 () 10)

passivate

Page 66: Discrete Event Simulation - SKKU

Sungkyunkwan University

Computer Engineering

Copyright (c) 2015 Intelligence Modeling Lab.

message

66

ip Model(1)

• model diagram

ip in

out

sigma phase

interrupt-handling-

time

temp

time-remaining p.t.

job-id

∞ passive ’( ) ’( )

0 5 0.1

Page 67: Discrete Event Simulation - SKKU

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passive, inf

67

ip Model(2)

• timing diagram

t

t

t

X

S

Y

g1

intext

in

message

g2

g2 g1

intext

out

passive busy busyinterrupted

0

0

0

0.1

3in

2

(phase)

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ip Model(3)

• transition diagram

passive

busy

interrupted

ext int

intext

in

out

message

ip

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ip Model(4-1)• model definition (code)(make-pair atomic-models ’ip)(send ip def-state ’(job-id

temptime-remainingprocessing-timeinterrupt-handling-time)

)(send ip set-s

(make-state ’sigma ’inf’phase ’passive’job-id ’()’temp ’()’time-remaining 0’processing-time 5’interrupt-handling-time 0.1)

)

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ip Model(4-2)(define (ext-ip s e x)(case (content-port x)

(’in(case (state-phase s)

(’passive (set! (state-job-id s) (content-value x))(set! (state-time-remaining s)

(state-processing-time s))(hold-in ’busy (state-processing-time s))

)(’busy (set! (state-time-remaining s)

(- (state-time-remaining s) e))(set! (state-temp s) (content-value x))

(hold-in ’interrupted (state-interrupt-handling-time s)))

(’interrupted (continue))) )

(else (bkpt “error: invalid input port” (content-port x))) )

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ip Model(4-3)(define (int-ip s)

(case (state-phase s)

(’busy (passivate))

(’interrupted (hold-in ’busy (state-time-remaining s)))

(else (bkpt “error: should not be executed” (state-phase s)))

) )

(define (out-ip s)

(case (state-phase s)

(’busy (make-content ’port ’out ’value (state-job-id s)))

(’interrupted (make-content ’port ’message

’value (list ’interrupted ’by (state-temp s)))

)

(else (make-content))

) )

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ip Model(4-4)

(send ip set-int-transfn int-ip)

(send ip set-ext-transfn ext-ip)

(send ip set-outputfn out-ip)

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ip Model timing diagram(5)

t0

3

g1in

t0

passive

int

t0

Message

(interrupted by g2)

busyinterrupted

busypassive

g2in

2

0.1

g1out

extext int

72

𝑋

𝑆(𝑝ℎ𝑎𝑠𝑒)

𝑌

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satae s = (2 busy g1 g2 2 5 0.1)

state s = (∞ passive g1 g2 2 5 0.1)

ip Model timing diagram(5)

t0

t0

t0

(send ip inject ’in ’g1 4) => state s = (5 busy g1 ( ) 5 5 0.1)

g1in

passivebusy

ext

(send ip inject ’in ’g2 3) =>

state s = (0.1 interrupted g1 g2 2 5 0.1)

3

g2in

interrupted0.1

ext

(send ip output?) => y = message g2

Message

(interrupted by g2)

(send ip int-transition) =>

int

busy

2

(send ip output?) => y = out g1

g1out

(send ip int-transition) =>

passive

int

73

𝑋

𝑆(𝑝ℎ𝑎𝑠𝑒)

𝑌

initial state s = (∞ passive ( ) ( ) 5 5 0.1)

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ip Model testing (verification)

• model test

(send ip inject ’in ’g1 4) => s=(5 busy g1 () 5 5 0.1)

(send ip inject ’in ’g2 3) => s=(0.1 interrupted g1 g2 2 5 0.1)

(send ip output?) => y= message g2

(send ip int-transition) => s=(2 busy g1 g2 2 5 0.1)

(send ip output?) => y= out g1

(send ip int-transition) => s=(∞ passive g1 g2 2 5 0.1)

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Experimental Frame

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Experimental Frame

An experimental frame module is a coupled-

model composed of atomic-models which

are used to generate inputs, observe

outputs, and provide control in accordance

with the desired experimental conditions.

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Model/Experimental Frame

Model/Experimental Frame

Model Structure

Experimental FrameAcceptor

Generator

Transducer

Input

Segment

Control

Segment

Output

Segment

Results

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EF

TRANS

GENR

outreport solved

outstop

ariv

P

out

in out

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Generator(1)

• Generates the input events for the model

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Generator(2)

• model diagram

GENR

sigma phase Inter-arrival-time

stop out

0 active 10

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Generator(3)

• timing diagram

X

Y

Spassive

outg1

outg2

outg3

outgn

active

stop

int int intint

any-value

ext

(phase)

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Generator(4)• pseudo code

state variables : sigma = 0

phase = active

parameters : inter-arrival-time = 10

external transition function : case input-port

stop: passive

else: error

internal transition function : case phase

active: hold-in active

inter-arrival-time

passive: (does not arise)

output function : case phase

active: send random-job-name to port out

passive: (does not arise)

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Generator(5-1)

• model definition (code)

(make-pair atomic-models ’genr)

(send genr def-state ’(inter-arrival-time))

(send genr set-s (make-state ’sigma 0

’phase ’active

’inter-arrival-time 10))

(define (ext-genr s e x)

(case (content-port x)

(’stop (passivate))

(else (continue))

))

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Generator(5-2)(define (int-genr s)

(case (state-phase s)

(‘active

;(set! (state-sigma s) (state-inter-arrival-time s))

(hold-in’ active (state-inter-arrival-time s))

)

) )

(define (out-genr s)

(case (state-phase s)

(’active

(make-content ’port ’out ’value (gensym))

)

(else (make-content))

) )

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Generator(5-3)

(send genr set-int-transfn int-genr)

(send genr set-ext-transfn ext-genr)

(send genr set-outputfn out-genr)

(gensym) => ‘g1

(gensym job-) => job-23

(gensym job-) => job-24...

arbitrary number

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GENR Model testing (verification)

• model test

(send genr output?) => y = out g1

(send genr int-transition) => s = (10 active 10)

(send genr output?) => y = out g2

(send genr int-transition) => s = (10 active 10)

(send genr inject ‘stop ‘(5 0.8) 2)=> s = (inf passive 10)

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Transducer(1)

• The transducer is designed to measure two

performance indexes of interest for computer processor :

the throughput and average turnaround time of jobs in a

simulation run.

- throughput is the average rate of job departures

from the architecture.

- a job-turnaround time is the length of time

between its arrival to the processor and its

departure from it as a completed job.

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Transducer(2)

• model diagram

TRANSD

sigma phase

arrived-listariv

out

clock total-ta

solved-list

solved

active 0 0

observation-interval

’() ’()

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Transducer(3)

• timing diagram

X

Y

Spassive

out

active

ariv

g1

solved

g1

ariv

g2

’(5, 0.8)

extext ext intext

y

t

t

t

(phase)

solved

g2

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Transducer(4-1)

• pseudo code

global variable: observation-interval

state variable: sigma = observation-interval

phase = active

arrived-list = ’()

solved-list = ’()

clock = 0

total-ta = 0

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Transducer(4-2)external transition function:

advance local clock to agree with global clock

case input-port

ariv: append job to arrived-list

solved: find job arrival-time

ta = clock – arrival time

put the job to solved-list

internal transition function:

case phase

active: passive

;; end of observation interval

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Transducer(4-3)

output function:

case phase

active: average-turnaround-time =

total-ta / solved-job-number

thruput = solved-job-number / clock

else: no output

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Transducer(5-1)• model definition (code)(define observation-interval 100)

(make-pair atomic-models ’transd)

(send transd def-state ’( arrived-list

solved-list

clock

total-ta))

(send transd set-s (make-state

’sigma observation-interval

’phase ’active

’arrived-list ’()

’solved-list ’()

clock 0

total-ta 0))

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Transducer(5-2)(define (ext-t s e x)

(let ((problem-id (content-value x)))

(set! (state-clock s) (+ (state-clock s) e))(case (content-port x)

(’ariv (set! (state-arrived-list s)(cons (list problem-id (state-clock s))

(state-arrived-list s))))(’solved (let* (

(pair (assoc problem-id (state-arrived-list s)))(prob-arrival-time (cadr pair))(turn-around-time

(- (state-clock s) prob-arrival-time)))

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Transducer(5-3)(when (not (null? prob-arrival-time))

(set! (state-total-ta s)

(+ (state-total-ta s) turn-around-time))

(set! (state-solved-list s)

(cons problem-id (state-solved-list s)))

)))

(else

(bkpt “error : invalid input port name ->”( content-port x)))

)

);;end case

(continue)

)

);;end let

(define (int-t s)

(case (state-phase s)

(’active (passivate))))

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Transducer(5-4)(define (out-t s)

(case (state-phase s)

(’active

(let (

(log-file (open-output-file “log”))

(avg-ta-time

(if (NULL? (state-solved-list s))

’()

(/ (state-total-ta s) (length (state-solved-list s)))

);end if

);avg-ta-time

(thruput

(if (= (state-clock s) 0)

’()

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Transducer(5-5)(/ (length (state-solved-list s)) (state-clock s))

)));local-variables

(newline log-file)

(display “The arrived list : ”log-file)

(display (state-arrived-list s) log-file)

(newline log-file)

(display “The solved list : ” log-file)

(display (state-solved-list s) log-file)

(newline log-file)

(display “Avg. turnaround time: ” log-file)

(display avg-ta-time log-file)

(newline log-file)

(display “ThruPut: ” log-file)

(display thruput log-file)

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Transducer(5-6)(newline log-file)

(close-output-port log-file)

(make-content ’port ’out ’value (list avg-ta-time thruput))

));’active

(else (make-content))

))

(send transd set-ext-transfn ext-t)

(send transd set-int-transfn int-t)

(send transd set-outputfn out-t)

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EF model(1)

• Experimental frame digraph-model

EF

Transducer

Generator

solved

ariv

in out result

out stop

out

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Coupled models

• Coupled model specification

N = <X, Y, D, {Md | d∈D}, EIC, EOC, IC, Select>

※ X, Y, {Md | d∈D}; defined by basic models

where

X, Y : identical to X, Y of basic models,

D : set of component names for each d in D,

Md : component basic model,

EIC : set of external input coupling,

EOC : set of external output coupling,

IC : set of internal coupling,

Select : function, the tie-breaking selector.

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ENTITIES

ATOMIC-MODELS COUPLED-MODELSSIMULATORS

CO-ORDINATORS

ROOT

CO-ORDINATORSFORWARD-

MODELS

BROADCAST

MODELS

HYPERCUBE-

MODELS

CONTROLLED

MODELS

CELLULAR-MODELS

TABLE-MODELS

MODELS PROCESSORS

KERNEL-MODELSDIGRAPH-

MODELS

~lst

~name

~processor

~parent

~inport

~outport

~cell-position

~parent

~devs-component

~time-cf-last-event

~time-of-next-event

~*-child

~wait-list

~clock

~ext-coup

~infl-origin

~structure

~ext-coup

~num-infl

~controller

~composition-tree

~influence-digraph

~ind-vars

~int-transfn

~ext-transfn

~outputfn

~time-advancefn

• Uppercase Letters: Class

• Lowercase Letters: Class/Instance Variables

~children

~receivers

~influencees

~init-call

~out-in-coup

~class

Class hierarchy of DEVS-Scheme

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EF model(1)

• Digraph-Model : EF

EF

GENR TRANSD

(out out)(out result)

(in solved)

GENR TRANSD

(out ariv)

(out stop)

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EF model(2)• pseudo code

DIGRAPH MODEL : EF

COMPOSITION TREE : root: EF

leaves: GENR, TRANSD

EXTERNAL INPUT COUPLING : EXTERNAL OUTPUT COUPLING :

EF.in->TRANS.solved GENR.out->EF.out

TRANSD.out->EF.result

INFLUENCE DIGRAPH: INTERNAL COUPLING :

GENR->TRANSD GENR.out->TRANSD.ariv

TRANSD->GENR TRANSD.out->GENR.stop

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EF model(3-1)• model definition (code 1)

;;load components of experimental frame, generator and

;;transducer

(load “/scheme/devs/simparc/mbase/genr.m”)

(load “/scheme/devs/simparc/mbase/transd.m”)

;;couple them in a digraph-model

(make-pair diagraph-models ’ef)

;;specify the root and leaves of the composition-tree

(send ef build-composition-tree ef (list genr transd))

;;add the external input port pairs to the arcs of the

;;composition-tree

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EF model(3-2)(send ef set-ext-lnp-coup transd (list (cons ’in ’solved)))

;;add the external output port pairs to the arcs of the

;;composition-tree

(send ef set-ext-out-coup genr (list (cons ’out ’out)))

(send ef set-ext-out-coup transd (list (cons ’out ’result)))

;;specify the influencees of each component

(send ef set-inf-dig (list (list genr transd) (list transd genr)))

;;add the internal port-pairs to the arcs of the

;;influence-digraph

(send ef set-int-coup transd genr (list (cons ’out ’stop)))

(send ef set-int-coup genr transd (list (cons ’out ’ariv)))

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EF model(3-3)• model definition (code 2)

;;load components of experimental frame, generator and

;;transducer

(load “/scheme/devs/simparc/mbase/genr.m”)

(load “/scheme/devs/simparc/mbase/transd.m”)

;;couple them in a digraph-model

(make-pair diagraph-models ’ef)

;;method specify-children calls build-composition-tree and

;;set-inf-dig

(send ef specify-children (list genr transd))

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EF model(3-4);;method add-couple figures out where to place the

;;specified

;;port pairs from the source and destination given in each

;;case

(send ef add-couple ef transd ‘in ‘solved)

(send ef add-couple genr ef ‘out ‘out)

(send ef add-couple transd ef ‘out ‘result)

(send ef add-couple transd genr ‘out ‘stop)

(send ef add-couple genr transd ‘out ‘ariv)

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EF-P model(1)

EF-P

P

EF

G T

EF-P

P EF

G T

M M

N

N

M M

M = < X, S, Y, int, ext, , ta >

N = <X, Y, D, {Md}, EIC, EOC, IC, Select>

M

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EF-P model(2)

• Digraph-Model : EF-P

EF-P

P EF

result outout in

in out

- Model Diagram

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EF-P model(3)• pseudo code

DIGRAPH MODEL : EF-P

COMPOSITION TREE : root: EF-P

leaves: EF, P

EXTERNAL INPUT COUPLING : EXTERNAL OUTPUT COUPLING :

None EF.result ->EF-P.out

INFLUENCE DIGRAPH: INTERNAL COUPLING :

P->EF P.out->EF.in

EF->P EF.out->P.in

PRIORITY LIST: (P EF)

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EF-P model(4-1)• model definition (code)

;;load the components

(load “/scheme/devs/simparc/mbase/p.m”)

(load “/scheme/devs/simparc/coupbase/ef.m”)

;;couple the experimental frame with the processor by p-ef

(make-pair diagraph-models ’ef-p)

;;build the composition tree and influence digraph

(send ef-p specify-children (list p ef))

;;internal coupling

(send ef-p add-couple p ef ’out ’in)

(send ef-p add-couple ef p ’out ’in)

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EF-P model(4-2);;external coupling

(send ef-p add-couple ef ef-p ’result ’out)

(send ef-p set-priority (list p ef))

;;the final touch, attach a root co-ordinator

(mk-ent root-co-ordinators r)

;;initialize it with the co-ordinator for ef-p

(initialize r c:ef-p)

;;start a simulation run

(restart r)

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EF-P model(5)

S : GENR S : TRANSD TRANSDGENR

EFS : PP

C : EF-P• C : Co-ordinator

• S : Simulator

• DEVS abstract processor hierarchy for simulation of EF-P

EF-P

C : EF

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EF model(6)

• Processors

(abstract simulators)

an abstract simulator is an algorithmic

description of how to carry out the instructions

implicit in DEVS models to generate their

behavior

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message format

source time content

port value

message : *, x, y, done

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simulator

parentdevs-comp

time-of-last-eventtime-of-next-event

*

X

y

done

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co-ordinator

parentchildren

time-of-last-eventtime-of-next-event

wait-list

devs-comp

*

X

done

Y

*

X

done

Y

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root-co-ordinator

devs-component

clock

done *

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*-message : indicates next internal event is to be carried out

X-message : represents the arrival of an external event to

a processor’s devs-component

Y-message : generated by output function when a processor

processes *-message by computing the int of

devs-comp

done-message : indicates that the state transition has been

carried out and provides the new time-of-next

-event

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root-co-ordinator

S: GENR

root-co-ordinator R

GENR

(mk-ent root-co-ordinators r) ; creation of R

(initialize r S:GENR) ; connection

(restart r)

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S:TRANSDS:GENR

C:EF

C:EF-P

S:P

R

TRANSDGENR

P

① *time 0

① *

① *② Y

② Y③ X

④ done(5)

③ X④ done(100)④ done(10)

④ done(10)

④ done(5) ⑤ *time 5

active0

phaseб

passiveinf

phaseб

active100

phaseб

5 busy

10

root-co-ordinator• C ; Co-ordinator

• S ; Simulator

λ

δext

δextδint

EF

EF-P

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root-co-ordinator

S : GENR TRANSDS : TRANSDGENR

C : EF EFS : PP

C : EF-P

• C ; Co-ordinator

• S ; Simulator

EF-P

R

① *time 0

① *

① *

② Y

② Y

③ X

③ X

④ done(5)

④ done(5)

④ done(10)

④ done(100)

④ done(10)

⑤ *time 5

б=5

б=0

б=100б=10

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Devs-scheme

<EF-P model>

C> …\simparc\pcs

[1](load “mbase/ef-p.m”)

[2](mk-ent root-co-ordinators r)

[3](initialize r c:ef-p)

[4](restart r)

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• Directions for Use

[1] (start-log “file-name”)

[2] (stop-log)

• Example

[1] (start-log “ef-p-test.log”)

[2] (load “mbase/ef-p.m”)

[3] (mk-ent root-co-ordinators r)

[4] (initialize r c:ef-p)

[5] (restart r)

[6] (stop-log)

current directory system files: method.s, pcs.bat, scheme.ini

……

start-log

123

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Multiserver architecture

• structure of model

MUL-C

P1in out

x1 y1

P2in out

x2 y2

P3in out

x3 y3

in out

MUL-ARCH

in out

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• model diagram

MUL-C in out

sigma phase

p3-state

out-port

p1-state p2-state

job-id

Multiserver Coordinator

x1 y1 x2 y2 x3 y3

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Assume that

process time of p model

is 5 time unit.

Mul-c

in

g1

in

g2

in

g3

y1

g1

y2

g2

y3

g3

3 1 1 3 1

x1

g1

x2

g2

x3

g3

out

g1

out

g2

out

g3

δext δint

X

S

Y

• timing diagram

phase

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• pseudo-code (1)

Multiserver Coordinator

ATOMIC-MODEL : MUL-C

State variables : sigma = inf

phase = passive

p1-state = passive

p2-state = passive

p3-state = passive

out-port = ‘()

job-id = ‘()

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• pseudo-code (2)Multiserver Coordinator

External transition function :

Store job-id

Case input-port

in : sequentially select an idle subordinate and set the

out-port (destination) to the corresponding value. i.e.

If p1-s passive then set out-port = x1 and p1-s = busy

If p2-s passive then set out-port = x2 and p2-s = busy

If p3-s passive then set out-port = x3 and p3-s = busy

When receive solution from a subordinate send to out :

y1: reset p1-s to passive and set out-port = out

y2: reset p2-s to passive and set out-port = out

y3: reset p3-s to passive and set out-port = out

Hold-in busy 0

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• pseudo-code (3)

Multiserver Coordinator

internal transition function :

Case phase

busy : passivate

passive : (does not arise)

output function :

Case phase

busy : case out-port

x1,x2,x3,out : output job-id to out-port

else make a null output

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• model definition (code)

Multiserver Coordinator

;;;;make a pair for the co-ordinator in multi-server module

(make-pair atomic-models ’mul-c)

(send mul-c def-state ’(

p1-s ;;phase of p1

p2-s ;;phase of p2

p3-s ;;phase of p3

out-port ;;holds next destination port

job-id ;;holds job id

)

)

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Multiserver Coordinator ;;initialize the state

(send mul-c set-s ( make-state ’sigma ’inf

’phase ’passive

’p1-s ’passive

’p2-s ’passive

’p3-s ’passive

’out-port ’()

’job-id ’()

)

)

;;external transition function

(define (ext-mc s e x)

(set! (state-out-port s) ’()) ;default, no port to be sent to

(set! (state-job-id s) (content-value x))

(case (content-port x)

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Multiserver Coordinator ;case 1. input from outside of the world

(’in

;find a processor not busy and send the job to it

(cond

((equal? (state-p1-s s) ’passive)

(set! (state-out-port s) ’x1)

(set! (state-p1-s s) ’busy))

((equal? (state-p2-s s) ’passive)

(set! (state-out-port s) ’x2)

(set! (state-p2-s s) ’busy))

((equal? (state-p3-s s) ’passive)

(set! (state-out-port s) ’x3)

(set! (state-p3-s s) ’busy))

))

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Multiserver Coordinator ;case 2. input for the subordinate processors

(’y1 (set! (state-p1-s s) ’passive)

(set! (state-out-port s) ’out)

)

(’y2 (set! (state-p2-s s) ’passive)

(set! (state-out-port s) ’out)

)

(’y3 (set! (state-p3-s s) ’passive)

(set! (state-out-port s) ’out)

)

) ;end of case

(hold-in ’busy 0)

)

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Multiserver Coordinator

;;;;internal transition function

(define (int-mc s)

(case (state-phase s)

(’busy

(passivate)

)))

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Multiserver Coordinator ;;;;output function

;;;;output the value to corresponding port

(define (out-mc s)

(case (state-phase s)

(’busy

(case (state-out-port s)

((x1 x2 x3 out)

(make-content ’port (state-out-port s)

’value (state-job-id s))

)

(else (make-content)) ;;mull output needed

))))

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Multiserver Coordinator

;;;;assignment to the model

(send mul-c set-ext-transfn ext-mc)

(send mul-c set-int-transfn int-mc)

(send mul-c set-outputfn out-mc)

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Multiserver architecture

• pseudo-code (1)DIGRAPH-MODEL : MUL-ARCH

COMPOSITION TREE :

Root : MUL-ARCH

Leaves : MUL-C, P1, P2, P3

EXTERNAL-INPUT COUPLING :

MUL-ARCH.in MUL-C.in

EXTERNAL-OUTPUT COUPLING :

MUL-C.out MUL-ARCH.out

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Multiserver architecture

• pseudo-code (2)

INFLUENCE DIGRAPH :

MUL-C P1, P2, P3

P1 MUL-C

P2 MUL-C

P3 MUL-C

INTERNAL COUPLING :

MUL-C.x1 P1.in P1.out MUL-C.y1

MUL-C.x2 P2.in P2.out MUL-C.y2

MUL-C.x3 P3.in P3.out MUL-C.y3

PRIORITY LIST : P1 P2 P3 MUL-C

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• timing diagram

Multiserver

(J1, in) (J2, in) (J3, in) (J4, in)

X

S(P1)

S(P2)

S(P3)

Y

Busy(J1)

processing

Busy(J4)

Busy(J2)

Busy(J3)

(J1, out) (J2, out) (J3, out)

ti tf

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Isomorphic copy

Isomorphism• Same structure h : on-to and one-to-one

1 -> a A1 -> E2

2 -> c A2 -> E1

3 -> b

4 -> d

Property Preservation

h(δ(arc)) = δ`(h(arc)))

operate-map = map-operate

Mapping h is isomorphism,

If it satisfies

operate-map = map-operate

1

3 2

4

A1 A2

E1

d

b

a

c

E2 δ : arc-to-endpoint function

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Isomorphic copy

Isomorphism• Same structure => Same behavior

s0 s1 s2

s0` s1` s2`

h

δ δ

δ` δ`

h h

h : on-to and one-to-one

s0 -> s0`

s1 -> s1`

s2 -> s2`

Property Preservation

h(δ(s)) = δ`(h(s)))s`

operate-map = map-operate

δ : state transition function

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• source code (1)

Multiserver

(load-from model-base_directory p.m)

(load-from model-base_directory mul-c.m)

;;make three copies from original p processor and copy its

;;initial state

(send p make-new ’p1)

(send p make-new ’p2)

(send p make-new ’p3)

;;now couple them to the multi-server

(make-pair digraph-models ’mul-arch)

;;build composition tree and influence digraph

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• source code (2)

Multiserver

(send mul-arch specify-children (list mul-c p1 p2 p3))

;;external-input coupling

(send mul-arch add-couple mul-arch mul-c ’in ’in)

;;external-output coupling

(send mul-arch add-couple mul-c mul-arch ’out ’out)

;;internal-coupling between processors and co-ordinator

(send mul-arch add-couple mul-c p1 ’x1 ’in)

(send mul-arch add-couple p1 mul-c ’out ’y1)

(send mul-arch add-couple mul-c p2 ’x2 ’in)

(send mul-arch add-couple p2 mul-c ’out ’y2)

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• source code (3)

Multiserver

(send mul-arch add-couple mul-c p3 ’x3 ’in)

(send mul-arch add-couple p3 mul-c ’out ’y3)

;;define the select function to avoid job loss when it

;;is sent from co-ordinator to a processor just as the

;;process is finishing its current job: processors first,

;;then co-ordinator

(send mul-arch set-priority (list p1 p2 p3 mul-c))

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Pipeline architecture

• structure of model

PIP-C

P1in out

x1 y1

P2in out

x2 y2

P3in out

x3 y3

in out

PIP-ARCH

in out

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• structure

PIP-C in out

sigma phase out-portjob-id

Pipeline Coordinator

x1 y1 x2 y2 x3 y3

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• pseudo-code (1)Pipeline Coordinator

ATOMIC-MODEL : PIP-C

State variables : sigma = inf

phase = passive

out-port = ‘()

job-id = ‘()

External transition function :

Store job-id

Case input-port

in : set out-port to x1

y1 : set out-port to x2

y2 : set out-port to x3

y3 : set out-port to out

hold-in busy 0

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• pseudo-code (2)

Pipeline Coordinator

internal transition function :

Case phase

busy : passivate

output function :

Case phase

busy : case out-port

x1,x2,x3,out : output job-id to out-port

else make a null output

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• timing diagram

Pipeline Architecture

(J1, in) (J2, in) (J3, in) (J4, in)

X

P1

P2

P3

Y

Busy(J1) Busy(J4)

(J1, out) (J2, out) (J3, out)

Busy(J2) Busy(J3)

Busy(J1) Busy(J2) Busy(J3)

Busy(J1) Busy(J2) Busy(J3)

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Divide&Conquer architecture

• structure of model

DC-C

P1in out P2in out P3in out

x1 y1 x2 y2 x3 y3

in out

DC-ARCH

in out

P&

DIV

P&

CMPL

incx

outcy

in px

outpy

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• structure

DC-C in out

sigma phase out-port

p-cnt

job-id

Divide&Conquer Coordinator

x1 y1 x2 y2 x3 y3 cx cypx py

To partitioner To processors To compiler

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• pseudo-code (1)

Divide&Conquer Coordinator

ATOMIC-MODEL : DC-C

State variables : sigma = inf

phase = passive

out-port = ‘()

job-id = ‘()

p-cnt = 3

(count of free processors)

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• pseudo-code (2)Divide&Conquer Coordinator

External transition function :

Store job-id

Case input-port

in : always send to problem partitioner by setting out-port to ‘px

py : if three sub-processors are free then set out-port to ‘xin

indicating to output function that a job is available in job-id

(problem is not partitioned in this simple model).

Otherwise job is lost.

y1,y2,y3 : partial result returned by one of the processors

increment p-cnt by one.

if p-cnt = 3 then send job-id to the port cx

set out-port to cx

clear p-cnt

Hold-in busy 0

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• pseudo-code (3)

Divide&Conquer Coordinator

internal transition function :

Case phase

busy : passivate

output function :

Case phase

busy : case out-port

xin : send job-id to each processor

px,cx,out : output to given port

else make a null output

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• timing diagram

Divide&Conquer

(J1, in) (J2, in)

(J1, out) (J2, out)

X

P&DIV

P1

P2

P3

P&CMPL

Y

Max{pi}

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Divide&Conquer architecture

• pseudo-code (1)DIGRAPH-MODEL : DC-ARCH

COMPOSITION TREE :

Root : DC-ARCH

Leaves : DC-C, P&DIV, P1, P2, P3, P&CMPL

EXTERNAL-INPUT COUPLING :

DC-ARCH.in DC-C.in

EXTERNAL-OUTPUT COUPLING :

DC-C.out DC-ARCH.out

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Divide&Conquer architecture

• pseudo-code (2)INFLUENCE DIGRAPH :

DC-C P1, P2, P3, P&DIV, P&CMPL

P1 DC-C P2 DC-C P3 DC-C

P&DIV DC-C P&CMPL DC-C

INTERNAL COUPLING :

DC-C.px P&DIV.in P&DIV.out DC-C.py

DC-C.x1 P1.in P1.out DC-C.y1

DC-C.x2 P2.in P2.out DC-C.y2

DC-C.x3 P3.in P3.out DC-C.y3

DC-C.cx P&CMPL.in P&CMPL.out DC-C.cy

PRIORITY LIST : P&CMPL P1 P2 P3 P&DIV DC-C

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Performance of Simple Architectures

ARCHITECTURE PARAMETERSTURNAROUND

TIME

MAXIMUM

THROUGHPUT

simple processor processing-time, p P 1/p

multiserver

processing-times,

1) p1,p2,p3

2) p1=p2=p3=p

3/throughput

p

1/p1+1/p2+1/p3

3/p

pipeline

processing-times,

1) p1,p2,p3

2) p1=p2=p3=p/3

p1+p2+p3

p

1/max{pi}

3/p

divide & conquer

processing-times,

1) p1, p2, p3, cp,cm

2) p1=p2=p3=p/3

cp+cm+max{pi}

cp+cm+p/3

1/max{pi,cp,cm}

1/max{p/3,cp,cm}