dirk stroobandt ghent university electronics and information systems department

Dirk Stroobandt

Ghent UniversityElectronics and Information Systems Department

A Priori System-LevelInterconnect Prediction

The Road to Future Computer Systems

Presentation at Northwestern UniversityMay 11th, 2000

May 11th, 2000 Talk at NWU, Dirk Stroobandt 2

• Why do we need a priori interconnect prediction?• Basic models• Rent’s rule with extensions and applications• A priori wirelength prediction• New evolutions:

• 3D and anisotropic systems• System-level predictions

• Applications• Conclusions

Outline





Outline


• Importance of wires increases (they do not scale as components).

• For future designs, very little is known. Roadmapping uses a priori estimation techniques.

• To improve CAD tools for design layout generation.• CAD tools have to take into account: timing constraints,

area constraints, performance, power dissipation…• All these constraints: wires should be as short as possible.• Estimation at early stage aids the CAD tools in finding a

better solution through fewer design cycle iterations.

Why do we needa priori interconnect prediction?


Why do we needa priori interconnect prediction?

To evaluate new computer architectures• To adhere to the increasing performance demands, new

computer architectures are needed.• Each of them must be evaluated thoroughly.• A priori estimates immediately provide a ground for drawing

preliminary conclusions.• Different architectures can be compared to each other.• Applications for evaluating three-dimensional (opto-

electronic) architectures, FPGA’s, MCM’s,...


Components of thephysical design step

layout

Layout generation

circuit architecture


Net

External net

Internal net

Logic block

Multi-terminal nets havea net degree > 2

Circuit model

Terminal / pin


8 nets cut

4 nets cut

Model for partitioning

Optimal partitioning:minimal number of nets cut


Model for partitioning

Module

New net

New terminal


The three basic models

Circuit model

Placement and routing model

Model for the architecture

Pad

Channel

Manhattan gridusing Manhattan metric

Cell

|||| 2121 yyxxd


The three basic models

Optimal routing = routing through shortest path• requires channels with sufficiently high density• for multi-terminal nets: Steiner treesThis defines the net length for known endpoints

Placement and routing model

Optimal placement = placement with minimal total wire length over all possible placements.





Outline


T = t B p

11

100010

10

100

100

T

B

Rent’s rule

averageRent’s rule

(simple) 0 p 1 (complex)

Normal values: 0.5 p 0.75

Measure for the complexityof the interconnection topology

p = Rent exponent

Rent’s rule was first described by [Landman and Russo, 1971]For average number of terminals and blocks per module:

t = average # term./block


BT B

B

TT

If B cells are added, what is the increase T?In the absence of any other information we guess

Overestimate: many of T terminals connect to T terminals and so do not contribute to the total.

We introduce a factor p (p <1) which indicates how self connected the netlist is

BB

TpT

ptBTB

dBp

T

dT

Or, if B & T are small compared to B and T

Statistically homogenous system

T

B

Rent’s rule


11

100010

10

100

100

T

B

Rent’s rule


Rent’s rule is experimentallyvalidated for a lot of real circuitsand for different partitioningmethodologies.

T = t B p

Distinguish between:• p* : intrinsic Rent exponent• p : Rent exponent for a given placement• p’ : Rent exponent for a given partitioningDeviation for high B and T:

Rent’s region II (cfr. later).


Rent’s rule

Rent’s rule is a result of the self-similarity within circuits

Assumption: interconnection complexity is equal at all levels.


Extension: the local Rent exponent

Variations in Rent’s rule:• global variations (e.g., lower complexity after Technology

mapping of the circuit, duplication);• local variations.

Two kinds of local variations in Rent’s rule:• hierarchical locality: some hierarchical levels are more

complex than others;• spatial locality: some circuit parts are more complex than

others.

Both are deviations from Rent’s rule that can be modelled well.


Hierarchical locality: Rent’s region II

Causes of region II:

- pin limitation problem;

- parallel to serial (complexity is moved from space to time, number of pins is lowered);

- coding (input and output stream compact).

11

100010

10

100

100

T

B



Hierarchical locality: region III

For some circuits: also deviation at low end.

Mismatch between the available (library) and the desired (design) complexity of interconnect topology.

Only for circuits with logic blocks that have many inputs.

T


Hierarchical locality: modelling

Use incremental Rent exponent (proportional to the slope of Rent’s curve in a single point).

)(BptBT

)log(

)log()(

B

TBp

B

T p1

p2

p3


Spatial locality in Rent’s rule

Inhomogeneous circuits: different parts have different interconnection complexity.

For separate parts:

ipii tBT

35.0

80.0

2

1

p

p

Only one Rent exponent (heterogeneous) might not be realistic.

Clustering: simple parts will be absorbed by complex parts.


Local Rent exponent

Higher partitioning levels: Rent exponents will merge.

Spreading of the values with steep slope (decreasing) for complex part and gentle slope (increasing) for simple part.

Local Rent exponent

tangent slope of the line that combines all partitions containing the local block(s).

T

B

11

11

11

2 22

2

2

2


Heterogeneous Rent’s rule

Suggested by (Zarkesh-Ha, Davis, Loh, and Meindl,’98)

Weighted arithmetic average of the logarithm of T:

Heterogeneous Rent’s rule (for 2 parts):

21

2211 logloglog

BB

TBTBTeq

eqpeqeq BtT

21

2211

1

212121 )(

BB

BpBpp

ttt

eq

BBBBeq


Use of Rent’s rule in CAD

Rent’s rule is very powerful as a measure of interconnection complexity

Can aid in the partitioning process

Benchmark generators are based on Rent’s rule

Is basis for a priori estimates in CAD


Rent’s rule in partitioning

Actual goal: minimize the number of pins per module.

We should use a pin count criterion.

External multi-terminal

nets lead to only one

new pin instead of two

when cut.

Preferring external nets

to be cut will better keep

clusters together.



Solution: use a new ratio value (in ratiocut partitioning) based on terminal count:

Better partitions are obtained because the total number of pins for each module is taken into account by the cost function.

|'||| AA

TR n

p



Better (ratio cut) heuristic by using terminal count prediction (Stroobandt, ISCAS‘99).

• Clustering property of the ratio cut: use Rent’s rule instead of uniformly distributed random graph.

• New ratio:

Instead of old ratio:

pppn

p BBBB

TR

)( 2121

21BB

TR n

old



Important (especially in pin-limited designs): terminal balancing (Stroobandt, Swiss CAD/CAM‘99).

• Minimizing the terminal count alone is not enough.

2

'

'

pA

ApA

Ab B

T

B

TR

Additional cost functionfor terminal balancing:

Terminal


Rent’s rule in benchmark generation

Generating benchmarks in a hierarchical way• Rent’s rule is used for estimating the number of connections• Other parameters have to be controlled as well:

– Classical parameters:* total number of gates* total number of nets* total number of pins

– Gate terminal distribution

– Net degree distribution

• Other issues: gate functionality, redundancy, timing constraints, ...





Outline


1. Partition the circuit into 4 modules of equal size such that Rent’s rule applies (minimal number of pins).

2. Partition the Manhattan grid in 4 subgrids of equal size in a symmetrical way.

Donath’s hierarchical placement model


3. Each subcircuit (module) is mapped to a subgrid.

4. Repeat recursively until all logic blocks are assigned to exactly one grid cell in the Manhattan grid.

Donath’s hierarchical placement model

mapping


Donath’s length estimation model

At each level: Rent’s rule gives number of connections• number of terminals per module directly from Rent’s rule

(partitioning based Rent exponent p’);• every net not cut before (internal net): 2 new terminals;• every net previously cut (external net): 1 new terminal;• assumption: ratio f = (#internal nets)/(#nets cut) is constant

over all levels k (Stroobandt and Kurdahi, GLSVLSI’98);

• number of nets cut at level k (Nk) equals

where =1/(1+f); depends on the total number of nets in the circuit and is bounded by 0.5 and 1.

kk TN


Donath’s length estimation model

Length of the connections at level k ?

Donath assumes: all connection source and destination cells are uniformly distributed over the grid.

Adjacent (A-) combination

Diagonal (D-) combination


Number of connections at level k:

Average length A-combination:

Average length D-combination:

Average length level k:

Total average length: with

and 2K = G = total number of gates

Average interconnection length

92

914

,

31

34

,

,2

,

k

dk

ak

l

l

l

)2,,(9)3,,(2)1,,(14

rKHrKHrKH

L

1212

),,( 2

)2(

xr

xrK

xrKH

)1(1 4)41( pkpk tGN


Results Donath

Scaling of the average length L as a function of the number of logic blocks G :

L

G

0

5

10

15

20

25

30

1 10 100 103 106105104 107

p = 0.7

p = 0.5

p = 0.3

Similar to measurements on placed designs.

)5.0()(

)5.0()log(

)5.0(5.0

ppf

pG

pG

L

p


Results Donath

Theoretical average wire length too high by a factor 2

10000

L

G

1

23

4

6

5

7

10 100 1000

8

experimenttheory

0


Enumeration: site density function (only architecture dependent). Occupying probability favours short interconnections (for an optimal placement) (darker)

• Keep wire length scaling by hierarchical placement.• Improve on uniform probability for all connections at one

level (not a good model for an optimal placement).

Including optimal placement model


Including optimal placement modelWirelength distributions contain two parts:

site density function and probability distribution

all possibilities

requires enumeration

(use generating polynomials)

probability of occurrence

shorter wires more probable

)()()( lqlDKlN


Wire length distribution

From this we can deduct that

For short lengths:

Local distributions at each level have similar shapes (self-similarity) peak values scale.

Integral of local distributions equals number of connections.

Global distribution follows peaks.

42

)(

)()( pl

LD

lNlq

32)( pllNllD )(


Occupying probability: results

8Occupying prob.

10000

L

G

1

23

4

6

5

7

10 100 10000

Donathexperiment

Use probability on each hierarchical level (local distributions).



Effect of the occupying probability: boosting the local wire length distributions (per level) for short wire lengths

Occupying prob.100

Wire length

percent of wires

10

1

0,1

0,01

10-3

10-4

100001 10 100 1000

per leveltotal

global trend

Donath

1

Wire length

10 100 1000

per leveltotal

global trend

10000


Effect of the occupying probability on the total distribution: more short wires = less long wires

average wire length is shorter


100

10

1

10-1

10-2

10-3

10-4

10-5

1 10 100 1000 10000Wire length

percent wires

Occupying prob.Donath



10

20

30

40

50

60

1 10Wire length

Percent wires


2 3 4 5 6 7 8 9

global trend-23%

-8%

+10%

+6%



0,1

1

10

100

1000

1 100Wire length

Number of wires


measurement

10


Davis’ probability function

Introduced by Davis, De, and Meindl (IEEE T El. Dev., ‘98).

Number of interconnections at distance l is calculated for every gate separately, using Rent’s rule.

Three regions: gate under investigation (A), target gates (C), and gates in between (B).

Number of connections between A and C is calculated.

This approach alleviates the discrete effects at the boundaries of the hierarchical levels while maintaining the scaling behaviour.



B

B

BB

B B

B

A B B

BB

B

C

C

C

C

C

C

C

C

C

C

C

C

C

BA

C

BA

C

BA

C

BA

C

BA= + - -

TAC TAB TBC TB TABC= + - -

Assumption: net cannot connect A,B, and C

pBAB BtT 1 pCBBC BBtT

pBB tBT pCBABC BBtT 1

pCBpB

pCB

pBCACA BBBBBBtTN 11



B

B

BB

B B

B

A B B

BB

B

C

C

C

C

C

C

C

C

C

C

C

C

For cells placed in infinite 2D plane

lBC 4

)1(2'41

1'

lllBl

lB

ppppCA lllllllllltN 4)1(21)1(24)1(2)1(21

42

4)( pCA l

l

Nlq


Planar wirelength model AL

L

Finite system, Btot=L2, no edges, approximate form for q(l)

)()()( lqlDNlN atot

ptottottot BBtN

22)( lLlDa

28

42)( pllq


Planar wirelength model B (Davis)L

L

else0

2for 312212

1for 361

)(

2

LlLlLlLlL

LllLLll

lDb

Finite system, Btot=L2, includes edge effects,use q(l)

29

)()()( lqlDNlN btot

ptottottot BBtN


Planar wirelength model comparison

100

101

102

100

101

102

103

104

Length

Num

ber

of n

ets

Model A

Model B

Btot = 1024p = 0.66

Model A: Lav = 4.53Model B: Lav = 2.27

30


Relationship between models from Davis (planar model B) and Stroobandt

(hierarchical model C)

0 10 20 30 40 50 60 700

0.5

1

1.5

2x 10

4

Length

Num

ber

H

hc

hHb hlDlD

1

),(4)(

Dc(l,h)

Db(l)

same q’(l)essentially identical!


Hierarchical wirelength model comparison

100

101

102

100

101

102

103

104

Length

Num

ber

Model D

Model C

Ctot = 1024p = 0.66

Model C (Stroobandt):Lav = 2.05Model D (Donath):Lav = 5.14

Model C: q(l) and hierarchyModel D: only hierarchy (q(l)=1)


Planar and hierarchical model comparison

100

101

102

100

101

102

103

104

Length

Num

ber

Model D

Model C

100

101

102

100

101

102

103

104

Length

Num

ber

of n

ets

Model A

Model B

Models B (planar) and C (hierarchical ) are equivalent if the Rent exponentused for the probability function (depends on placement) and the one usedfor the number of nets per hierarchical level (based on partitioning) are the same





Outline


Extension to three-dimensional grids


Three-dimensional grids: basic results

Average length converges (for G) up to r = 2/3 1/2

Average wire length is lower than for 2D (no long wires)


Anisotropic systems


Anisotropic systems

Basic method: Donath’s method in 3D

Not all dimensions are equal (e.g., optical links in 3rd D)• possibly larger latency of the optical link (compared to intra-

chip connection);• influence of the spacing of the optical links across the area

(detours may have to be made);• limitation of number of

optical layers

Introducing an optical cost


Anisotropic systems

If limited number of layers: use third dimension for topmost hierarchical levels (fewest interconnections).

For lower levels: 2D method.

2D and 1D partitioning are sometimes used to get closer to the (optimal in isotropic grids) cubic form.

Depending on the optical cost, it is advantageous either to strive for getting to the electrical plains as soon as possible (high optical cost, use at high levels only) or to partition the electrical planes first (low optical cost).


External nets

Importance of good wire length estimates for external nets during the placement process:

For highly pin-limited designs: placement will be in a ring-shaped fashion (along the border of the chip).


Wire lengths at system level

At system level: many long wires (peak in distribution).

How to model these?Davis and Meindl ‘98:estimation based onRent’s rule with thefloorplanning blocksas logic blocks.IMPORTANT!


Improving CAD tools for design layout

Digital design is complex

Computer-aideddesign (CAD)

More efficient layout generation requires good wire length estimates.• Layer assignment in routing• effects of vias, blockages• congestion, ...A priori estimates are rough but can already provide us with a lot of information.


Evaluating new computer architectures

Estimation for evaluating and comparing different architectures

Circuit characterization

We need parameters to classify circuits in classes and to optimize them.

Benchmark generation based on Rent’s rule.


Conclusion

• Wire length estimates are becoming more and more important.

• A priori estimates can provide a lot of information at virtually no cost.

• Methods are based on Rent’s rule.• Important for future research: how can we build a

priori estimates into CAD layout tools?

More information at http://www.elis.rug.ac.be/~dstr/dstr.html

dirk stroobandt ghent university electronics and information systems department

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