digital vlsi- assignment mentor graphics
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Assigtnmenet on the use of Mentor GraphicsTRANSCRIPT
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EE-404: Digital VLSI, Spring15
Assignment on the use of Mentor Graphics
Submitted by:
Akshit Jain (0985962)
Department of Electrical and Computer Engineering
University of Bridgeport
Bridgeport, CT-06604
USA
02/22/2015
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Question: - Design, Simulate and Create Layouts for NAND, NOR, EXOR and EXNOR CMOS gates using Mentor Graphics tools as under:
(1) Design Architect - Schematic design
(2) Accusim - Functional Verification.
(3) ICStation - Layout/ Physical Design.
1) NAND Gate:-
Figure 1: Schematic of NAND Gate in Design Architect
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Figure 2: Schematic report of NAND Gate in Design Architect
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Figure 3: Functional Verification of NAND Gate in Accusim
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Figure 4: Transient mode analysis and waveform for NAND Gate
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Figure 5: DC Mode analysis and waveform of NAND Gate
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Figure 6: Layout of NAND Gate in IC Station
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Figure 7: Layout Vs Schematic report of NAND Gate in the IC Station
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2) NOR GATE:-
Figure 8: Schematic of NOR Gate in Design Architect
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Figure 9: Schematic report of NOR Gate in Design Architect
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Figure 10: NOR Gate Symbol
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Figure 11: Functional Verification of NOR Gate in Accusim
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Figure 12: Transient mode analysis and waveform for NOR Gate
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Figure 13: DC Mode analysis and waveform of NOR Gate
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Figure 14: Layout and Design Rule Check of NOR Gate in IC Station
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Figure 15: Layout Vs Schematic report of NOR Gate in the IC Station
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3) XOR GATE:-
Figure 16: Schematic of XOR Gate in Design Architect
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Figure 17: Schematic report of XOR Gate in Design Architect
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Figure 18: Functional Verification and Transient mode analysis and waveform for XOR Gate
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Figure 19: DC Mode analysis and waveform of XOR Gate
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Figure 20: Layout and Design Rule Check of XOR Gate in IC Station
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Figure 21: Layout Vs Schematic report of XOR Gate in the IC Station
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4) XNOR GATE:-
Figure 21: Schematic of XNOR Gate in Design Architect
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Figure 22: Schematic report of XNOR Gate in Design Architect
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Figure 23: XNOR GATE Symbol
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Figure 24: Functional Verification and Transient mode analysis and waveform for XNOR Gate
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Figure 25: DC Mode analysis and waveform of XNOR Gate
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Figure 26: Layout and Design Rule Check of XNOR Gate in IC Station
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Figure 27: Layout Vs Schematic report of XNOR Gate in the IC Station