digital to analog converters...

DAC’s

C.Sauriol Rev. 11/8/2002 DAC’s Page I1

DIGITAL TO ANALOG CONVERTERS (DAC's)

A linear DAC converts a digital input into an analog voltage that is directly proportional to the binary input, that is VAN (out ) = KCON × BINin where KCON is the conversion gain or constant given by the slope of the DAC transfer function. The binary input can be signed (+ve or -ve) or unsigned as well as the analog reference, depending on the actual converter being used. This means that converters can operate in quadrant I alone, or in quadrant II alone, or quadrants I and II alone, or in quadrants I, II, III and IV, etc. Most DAC's use a fixed precision DC reference voltage in order to generate an accurate analog output, that is: VAN (out ) = ACON × BINin × VREF (DC ) Multiplying DAC's, as the name implies, multiply too input signals, one being digital and the other analog, to produce the analog output, that is: VAN (out ) = ACON × BINin × Vin (AC ) . The analog input is usually injected into the reference voltage input of the DAC and may need to be superimposed on top of a DC component if the DAC reference input cannot handle both +ve and -ve signals. 0

00

001

010

011

100

101

110

111

DIGITAL

BINARY

INPUT

ANALOG

REFERENCE

INPUT

+VE

+VE-VE

-VE

QUADRANT IQUADRANT II

QUADRANT III QUADRANT IV

011 010 001 000 100 101 110 111

DAC’s


DIFFERENT TYPES OF DAC TRANSFER FUNCTIONS

ANALOG

O/P

BINARY I/P

POSITIVE

000

001

010

011

100

101

110

111

QUADRANT I ANALOG

O/P

BINARY I/P

NEGATIVE

000

001

010

011

100

101

110

111

QUADRANT IV

ANALOG

O/P

BIPOLAR

SYMETRIC

BINARY I/P

NON

000

001

010

011

100

101

110

111

QUADRANT IV

QUADRANT I

BINARY I/P

ANALOG

O/P

BIPOLAR

SYMETRIC

000

001

010

011

100

101

110

111

QUADRANT I

QUADRANT IV

SIGNED BINARY I/P

ANALOG

O/P

BIPOLAR

SYMETRIC

NON

000

001

010

011

100

101

110

111

SIGNED BINARY I/P

ANALOG

O/P

BIPOLAR

SYMETRIC

000

001

010

011

100

101

110

111

DAC’s


DAC and ADC TERMINOLOGY Conversion Time: The time required for a complete measurement by an analog-to-digital converter. DC Common-Mode Error. This specification applies to ADCs with differential inputs. It is the change in the output code that occurs when the analog voltages on the two inputs are changed by an equal amount. It is expressed in LSBs. Differential Nonlinearity: Ideally, any two adjacent digital codes correspond to measured analog voltages that are exactly one LSB apart. Ditferential non-linearity is a measure of the worst case deviation from the ideal 1 LSB step. For example, a DAC with a 1.5 LSB output change for a 1 LSB digital code change exhibits 1/2 LSB differential non-linearity. Differential non-linearity may be expressed in fractional bits or as a percentage of full scale. A differential non-linearity greater than 1 LSB will lead to a non-monotonic transfer function in a DAC and missing codes in an ADC. Gain Error (Full Scale Error): For an ADC, the difference (usually expressed in LSBs) between the input voltage that should ideally produce a full scale output code and the actual input voltage that produces that code. For DACS, it is the difference between the output voltage (or current) with full scale input code and the ideal voltage (or current) that should exist with a full scale input code. Gain Temperature Coefficient (Full Scale Temperature Coefficient). Change in gain error divided by change in temperature. Usually expressed in parts per million per degree Celsius (PPM/°C). Integral Nonlinearity (Linearity Error). Worst case deviation from the line between the endpoints (zero and full scale). Can be expressed as a percentage of full scale or in fractions of an LSB. LSB (Least-Significant Bit). In a binary coded system this is the bit that carries the smallest value or weight. Its value is the full scale voltage (or current) divided by 2n, where n is the resolution of the converter. Monotonicity: A monotonic function has a slope whose sign does not change. A monotonic DAC has an output that changes in the same direction (or remains constant) for each increase in the input code. The converse is true for decreasing codes. MSB (Most Significant Bit): In a binary coded system this is the bit that has the largest value or weight. Its value is one half of full scale. Multiplying DAC. In a sense, every DAC is a multiplying DAC since the output voltage (or current) is equal to the reference voltage times a constant determined by the digital input code divided by 2n (n is the number of bits of resolution). In a two-quadrant multiplying DAC the reference voltage or the digital input code can change the output voltage polarity. If both the reference voltage and the digital code change the output voltage polarity, four-quadrant multiplication exists. Offset Error (Zero Error). In a DAC, this is the output voltage that exists when the input digital code is set to give an ideal output of zero volt. In the case of an ADC, this is the difference between the ideal input voltage (l/2 LSB) and the actual input voltage that is needed to make the transition from zero to 1 LSB. All the digital codes in the transfer curve are offset by the same value. Many converters allow nulling of offset with an external potentiometer. Offset error is usually expressed in LSBs. Power Supply Rejection (Power Supply Sensitivity). The sensitivity of a converter to changes in the dc power supply voltages. Quantizing Error: The error inherent in all A/D conversions. Since even an "ideal" converter has finite resolution, any analog voltage that falls between two adjacent output codes will result in an output code that is inaccurate by up to 1/2 LSB.

DAC’s


Ratiometric Operation: Many A/D applications require a stable and accurate reference voltage against which the input voltage is compared. This approach results in an absolute conversion. Some applications, however, use transducers or other signal sources whose output voltages are proportional to some external reference. In these ratiometric applications, the reference for the signal source should be connected to the reference input of the converter. Thus, any variations in the source reference voltage will also change the converter reference voltage and produce an accurate conversion Resolution: The smallest analog increment corresponding to a 1 LSB converter code change. For converters, resolution is normally expressed in bits, where the number of analog levels is equal to 2n. As an example, a 12-bit converter divides the analog signal into 212 = 4096 discrete voltage (or current) levels. Settling Time: The time from a change in input code until a DAC's output signal remains within ± 1/2 LSB (or some other specified tolerance) of the final value.

RELATIONS BETWEEN DIFFERENT BIPOLAR BINARY CODES

Commonly Used Bipolar Codes

Modified and Complementary Bipolar Codes

DAC’s


Ideal D/A conversion for 4 bit (3 bits plus sign) offset binary, 2’s complement, sign-magnitude and 1’s complement codes.

Ideal A/D conversion for 4 bit (3 bits plus sign) offset binary, 2’s complement, sign-magnitude and 1’s complement codes.

DAC’s


BINARY WEIGHTED RESISTOR DAC (CMOS)

B7

B6

B5

B0

BINARY

INPUT VOUT

ANALOGOUTPUT

VREF

I 7

I 6

I 5

I 0

2 0 R

2 1 R

2 2 R

2 7 R

RF

+ -PRECISIONREFERENCE

CMOS SWITCHES

IK∑ IK∑

I7 = B7VREF20 R

I6 = B6VREF21R

I5 = B5VREF22R

• • • I0 = B0VREF27 R

Vo = 0 − IK∑[ ]RF = −RF × B7VREF20 R

+ B6VREF21R

+ B5VREF22 R

+ • • • + B0VREF27R

Vo = −RFR

× VREF ×B7

20 +B6

21 +B5

22 + • • • +B0

27

= −RFR

× VREF ×BIN2N−1

where N = 8 is the number of bits and BIN is the binary number

Binary weight The analog voltage change associated by a given bit is called binary weight. Let VREF =-10,24V and RF = R and let's calculate the binary weights.

W7 = −VREF × RFR

× B7

20 =10,24 × B7

20 =10,24V ⇒ MSB weight

W6 = −VREF ×RFR

×B6

20 =10,24 ×B6

21 = 5,12V • • •

W0 = −VREF ×RFR

×B0

27 = 10,24 ×B0

27 = 80 mV ⇒ LSB weight (RESOLUTION)

DAC’s


DAC transfer function

VO = 10,24 ×BIN2N −1

for VREF = -10,24V,

RF = R and N = 8 bits The resolution is equal to the output step size which is also equal to the weight of the LSB, that is

∆VO =10,24 × ∆BIN2N −1

∆VO =10,24 ×1

28−1

∆VO = 80mV

VFS =10,24 ×BIN(MAX)

2N−1

V out

ANALOG

OUTPUT

BINARY INPUT BIN

255

254

0 1 2 3 4 253

0,08

0,16

0,24

0,32

20,16

20,24

20,32

20,4

0,00

(VOLT)

FULL SCALE VOLTAGE

RE

SO

LUT

ION

The accuracy of the DAC is not necessarily equal to its resolution as it depends on the accuracy of the components which have inherent tolerances and non-zero temperature coefficients. This type of DAC gets less and less accurate as the number of bits increases because the resistors require more and more accuracy which cannot be afforded by the fabrication process. Another disadvantage of the weighted resistor DAC is the settling time of the output voltage that increases with the number of bits because the resistance seen by the MOS analog switches is not equal and therefore each switch has a different switching time thereby causing different delay times for each bit.

DAC’s


R-2R LADDER DAC - VOLTAGE OUTPUT (CMOS)

2R

RRR

2R2R2R2R2R2R2R 2R

RRR R

VREF

B7 B6 B5 B4 B3 B2 B1 B0

BINARY INPUT

I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 RF

+ -

Vout

2R R 2R R2R R

+ve DC or

-ve DCorAC

signal

A B C

VR

VR

2

VR

4

VR

8

MSBLSB

TERMINATION RESISTOR

IK∑

IK∑

IK∑

CMOS

SWITCHES CMOS SWITCHES

CMOS SWITCHES

CMOS

SWITCHES

RA BVR VB = VR/2

REQ = R

RB CVC= VR/4

REQ = R

VR/2

I7 = VREF21R

I6 = VREF22 R

I5 = VREF23 R

• • • I0 = VREF28 R

Vo = 0 − IK∑[ ]RF = −RF × B7VREF21R

+ B6VREF22 R

+ B5VREF23 R

+ • • • + B0VREF28R

Vo = −RFR

× VREF ×B7

21 +B6

22 +B5

23 + • • • +B0

28

= −RFR

× VREF ×BIN2N

If RF = R and VREF = -10,24V the TF is as shown beside.

DAC’s


DESIGN EXAMPLE-1 DAC-1020 (CMOS -VOLTAGE O/P) Audio volume control

+15V

-15V

+15V

V o

Vin

BINARY INPUT

REF

+Vdd G ND

LSBMSB

DAC1020

14

15

16

O2

O1

4 13

1

2

3RF

Input signal: 4 VP, 20 Hz to 20 kHz, small DC component < ±1V Output signal: 0 to 10 VP , 0 V (DC)

System bandwidth: 2 Hz to 100 kHz Calculate all required components and draw system transfer function.

DAC’s


DESIGN EXAMPLE-2 DAC-1020 (CMOS-VOLTAGE O/P) Four quadrant multiplying DAC

1NA1 05

2 5K 2 5K

25 K 2 5K

+15 V

BIN ARY INP U T+5 V HC M OS

2 TO 1ANAL OG MU X

+6 .2 5V

ADG4 19Ron < 45

POL ARITY CONTROL

+15 V

-1 5V

Vo ut

off set bal

Vr efMC14 04

1

2

3

4

5R EF

+Vd d GND

LSBMSB

D AC1020

14

15

16

O 2

O 1

4 13

1

2

3R F

Design a four quadrant multiplying DAC with symmetrical output ranging from -5,115V to +5,115V. The reference input has to be switchable from +6,25V DC and must be derived from a +6,25V precision reference IC. Draw the DAC transfer function and fully label. Also prove that the output is given by the following

expression: VOUT = −VREF −1 + BIN2N −1 + 1

2N

Hint: Use equation given in data sheets and convert Ak = -1 + 2 Bk where Bk = 0 or 1 and Ak = -1 or +1. N is # of bits and BIN is the binary input.

Vout

SIGNEDBINARY I/P

0x000

0x010

0x011

x1111

011x1

011x0

100x1

100x0

x1110

x1101

+5,12V-5 mV

-5,12V+5mV

+5 mV

-5mV

10 mVsteps

+ve V REF

-ve VREF

+ve V REF -ve VREF

DAC’s


R-2R LADDER CURRENT OUTPUT DAC'S

2k1k

1k

2k 2k 2k 2k 2k 2k 2k 2k

1k 1k 1k 1k 1k 1k

Ir ef

2

Ir ef Ir ef Ir ef Ir ef Ir ef Ir ef Ir ef Ir efIr ef

4 8 16 32 64 128 256 256

MSB LSBB7 B6 B5 B4 B3 B2 B1 B0

DAC- 08 EQUIVALENT CIRCUIT

IOUT = IREF

BIN

28

IOUT = IREF

BIN

28

R1

R1

R1

Ir ef

Vr ef ( - )

Vr ef (+)

Vr ef (+)

0A

Ir ef

0V

POSITIVEREFERENCEVOLTAGE

P1

Ir ef

Vr ef ( - )

Vr ef (+)

0A

Ir ef

Vr ef ( - )

Vr ef (+)

PRECISIONREFERENCE

P1

LOW TC

LOW TC

SMALLPOT

R1

R1

Ir ef

Vr ef ( - )

Vr ef (+)

0A

Ir ef

Vr ef ( - )

Vr ef ( - )NEGATIVEREFERENCEVOLTAGE

LOW TC

P1

SMALLPOT

-V EE

CCOM

-V EE

CCOM

-V EE

CCOM

VXVX VX VX VX VX VX

16 32 64 1282 4 8

termination resistorvx vx

Q3

Q1 Q2

Q4

Q5

VLC

VTH

BK

I K

I OUT

I OUT

I K

0v 5v

1,4 v 2,1 v

on off

on off

currentswitching

IOUT = IK∑ = B7IREF21 + B6

IREF22 + B5

IREF23 + • • • + B0

IREF28

= IREF ×BIN2N

Threshold voltage of current switch VTH = VLC +1,4V

Frequency compensation of reference op amp: If VREF is a fixed DC level, CCOM = 0,01 µF. If VREF is DC + AC signal for multiplying DAC applications, CCOM = 15 pF stabilises op amp with a maximum bandwidth of approximately 1 to 3 MHz. If CCOM increases, BW goes down.

DAC’s


DAC-08 ANALYSIS EXAMPLE-3 A) Determine the range of Vo and draw the transfer function of the DAC showing all relevant values including the steps' size. The bottom part of the 5k pot is set to 2023Ω as shown on the circuit diagram. B) If BIN= 113, determine the output voltage. C) Explain why this circuit is more stable with respect to temperature variations.

+ 15V -15 V

B IN INPU T

5K

2K

202 3

4.3K+5V

0.1 u F

Vo u t

297 7

REFVLC +Vcc -Vee com

MSB LSB

DAC0800

1 4

1 5

1

2

34

5 1 2

1 3 1 6

Iou t

Iou t

RE F

DAC’s


DAC-08 ANALYSIS EXAMPLE-4 P1=657Ω P2=2,00 kΩ

IO = IREFBIN256

where BIN=255-BIN

A) Determine the analog output range. B) Draw the DAC transfer characteristic showing all relevant values. C) What is the DAC resolution in mV? D) If BIN=133, determine the value of Vo. E) Explain what makes this circuit configuration not very stable with temperature variations.

+1 5V -15 V -1 5V

+6.2 V

P1

8.2K

P 2 1 8K 1 0K

2 0K0.0 1 uF

9.1k

V out

BAL

B IN INPUT

REFVLC + Vc c -Vee com

MSB LSB

DAC0800

14

15

1

2

34

5 12

13 16

Iout

Iout

REF

DAC’s


DAC-08 DESIGN EXAMPLE-5 Determine the "precision resistor" values necessary to obtain a conversion range of -10,24V to +10,24V-LSB for a corresponding BIN input of 0 to 255. Assume reasonnable current levels. Explain what P1 and P2 will trim in the transfer function of the DAC.

+1 5V -1 5V -1 5V

20 K0.01 uF

Vo ut

B AL

B IN INPUT

+ 5V

2 00

2 00

REFVLC +Vc c -V ee com

MSB LSB

DAC0800

14

15

1

2

34

5 12

13 16

I out

I out

REF

DAC’s


DAC-08 DESIGN EXAMPLE-6 : Digital amplitude control

ANALOG INPUT 4 VPP, 20 to 20 kHz

AC coupled

ANALOG OUTPUT

0 to 16 VPP, VDC = 0V, RL 100k

DIGITAL INPUT

HCMOS, 0 AND +5V

Make system bandwidth compatible with signal

bandwidth.

+ 15V - 15V

Vou t

B IN INPUT

2 00Vin

-1 5V

P1

REFVLC + Vc c -Vee com

M SB L SB

DA C08 00

1 4

1 5

1

2

34

5 12

13 16

Io ut

Io ut

REF

Let FLO = 2 Hz and FHI = 200 kHz such that the signal is not attenuated in the 20 to 20 kHz range. IREF (DC) + IREF (AC) > 0 at all time because IREF (+) must always sink into the +REF input. This means that we cannot operate the +REF input with an AC signal alone, it must be superimposed on a DC component. This entails that the op amp O/P will have both DC and AC components which means AC coupling to the load to remove the DC component.

VOPA = IOUT × RF + V + = IREF (DC)RF + IREF( AC )SIN ωt( )RF[ ]×BIN2N

+ V +

DAC’s


EXAMPLE 7 PROGRAMMABLE POWER SUPPLY ANALYSIS

A1

A4A3

A2

Q1

Q2

10V

R1 R3

R2

R1

R2

R3

R4

R5

R6

R7

R8

R9R10

C1

C8

C9

Rsen

BIN-1

BIN-2

4.7K

8.2K

910

0.4

10K

10K

91K

91K

10K10K

3.3K

1562.5

1.6K

3353.5

3.3K

0A

0A

1.6 mA

0.7455mA

0V

0V

0V

0V

0V

0V0A

0A

0A

0A

0A

3.3K2.35 mA 3.8 mA0 to 1.594 mA

0 to0.7426 mA

0 to 7.426V 0 to 7.426V

VOLTAGE CONTROL DAC

CURRENT LIMIT CONTROL DAC

20K

0V to 31.875V

0 to1.594 mA

+Vsg -

0A to2.04ALIMIT

- +

- +

0V to 31.875V

OFF -Vsat

ΩΩΩΩ

0V to 7.426V 0V

to0.816V

CURRENT LIMIT COMP

SENSEAMPLIFIER

10K

10K

OFF

POWERMOSFET0A

UNREG. INPUT

0.1 uF


MSB LSB

DAC0800

14

15

1

2

34

5 12

13 16

Iout

Iout

REF


MSB LSB

DAC0800

14

15

1

2

34

5 12

13 16

Iout

Iout

REF

2,5V 0,2%

NAT. SEMI. LM4040B

LOAD

+15V

-15V

-15V

-15V

+15V

-15V

-15V

+15V

+15V

DAC’s


SENSE AMPLIFIER: Amplifies sense voltage (ILRsen) by gain R3/R1 and produces Vo2 that provides indication of load current. R2 does not affect gain but attenuates the high input voltages within the input voltage renge of A2. Matching of R1, R2 and R3 resistor pairs is extremely critical to the accuracy of the current limit. Matching should be such that accuracy of Ilimit is within ½ LSB. POWER MOSFET: Provides heavy load current that op amps cannot supply. As load current increases, the small differential input of A1 increases – which means (V1

+- V1-) gfoes up – Vo1 increases, VE2 of Q2 increases, IE3~IC3 also increases, which ultimately increases VSG1=IC3R6 and tells the MOSFET

to increase its drain and source currents thereby supplying the load current. R4 – R5 : attenuates voltage VD1 = Vout+ILRsen to a low enough level such that Vo1 = VE2 + 0.7 does not saturate the output of A1 under worst case

conditions. ( )54254

512 RRI

RRR

VV EDE ++

= where IE2 = VSG1/R6 . VE2 will be maximum when VD1 is maximum and IE2 is also maximum. This will occur

at Vout max and IL max. VSG1 max can be obtained from the MOSFET characteristics (ID versus VGS). CURRENT LIMIT: Normally there is no current limiting if there is no overload . An overload condition can be detected by A3 which acts as a voltage comparator looking at V3

+= Vo2 = ILRsenAsen and V3- = Vo4 = VDAC2 . As long as V3

+ < V3- , Vo3 goes into –ve saturation and turns off the diode which keeps

the current limit loop open and ineffective. As soon as V3+

exceeds V3-, Vo3 goes +ve and turns the diode on which closes the current limit feedback loop

and will now force V3- to equal V3

+ and will therefore force Vo2 = ILRsenAsen to equal Vo4 = IDAC2*R10. Therefore IL will be limited because of –ve feedback through A3 forcing Vo2 to equal VDAC2=Vo4. STABILITY OF FEEDBACK LOOPS: C1, C8 and C9 are critical to the stability of the many feedback loops and will dictate the response time of the power supply to sudden changes in load current and voltage.

DAC’s


EXAMPLE-8 DESIGN OF PROGRAMMABLE POWER SUPPLY

MOSFET CHARACTERISTICS

GENERAL SPECIFICATIONS: Vo = 0 to 51V,BIN1 = 0 to 255, ∆Vo = 0,2V, ILIMIT = 0 to 2.55A, BIN2 = 0 to 255, ∆IL = 10 mA

LF347 DATA (VSUP =±15V) RFP10P12 DATA MIN TYP MAX MIN TYP MAX

Vout swing ±12V ±13,5V V(TH) at 1 mA -2V -4V Vin range ±11V +15V, -12V VGS (MAX) ±20V

Vio @ 25oC 5 mV 10 mV VDS (MAX) -120V LF411 DATA (VSUP =±15V) RON,VGS=-10V 0,5Ω

Vout swing ±12V ±13,5V Ciss,VDS=-25V 1,7 nF Vin range ±11V +14.5V,-11.5V

Vio @ 25oC 0.8 mV 2 mV

UNREG'D I/P

LF347

LF411

1

2 V o2

R1 R3

R2

R1

R2

R3

R4

R5

R6

R7

SENSERESISTOR

0V

0V

Q1RFP12P10

1

Io (DAC)

Io (DAC)

Vo

- Vo +

0Vto51V

LOW OFFSET OP AMP

0 to 2.55A

LOAD

+12V

+12V

-12V

-12V

-12V

-12V

DAC’s


DESIGN EXAMPLE-9 DIGITAL CONTROL OF AC AND DC COMPONENTS

47 pF

1

2

3Vin(AC)

2,5V 0,2%

NAT. SEMI.

LM4040B

REF

+Vdd GND

LSBMSB

DAC1020

14

15

16

O2

O1

4 13

1

2

3RF


MSB LSB

DAC0800

14

15

1

2

34

5 12

13 16

Iout

Iout

REF

+15V

+15V

+15V-15V

IDCIAC

Vo1(AC)

Vo2(DC)+Vo2(AC)RFROFF

RAC

IDAC2

IFIX

Iref

BIN-1

BIN-2

AC AMPLITUDE CONTROL DAC

DC OFFSET CONTROL DAC

(AD7533)

digital to analog converters...

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