digital radio front-end strategies provide game-changing ... · pdf filesince the output power...

Introduction

Explosive growth in cellular data usage is dictating communication infrastructure evolution,

pushing for increased capacity and reduction in cost and environmental impact. Heteroge-

neous networks – coexisting macro/pico/femto cells, along with advanced receivers and

transmitters to maximize spectral effi ciency can provide the required boost in capacity. At the

same time, improving power effi ciency will be a key consideration for next-generation radio

architectures.

As wireless service providers and base station manufacturers aggressively push towards

deployment of small cell base stations, they are faced with challenges to meet viable business

and network performance models: approximately a 10x reduction of power consumption,

size and cost compared to the traditional macro base station. A lot of focus has been given

to single-chip base station SoCs, along with optimized small cell software as a key strategy

for achieving these objectives, and rightfully so as the SoC architecture and software plays a

signifi cant factor in small cell cost, power, size and performance. The digital radio front ends

of macro base stations are typically on separate boards, sometimes even in separate enclo-

sures. Since the output power for small cells is signifi cantly lower than for traditional macro

base stations, one approach could be to scale down the macro design (perhaps also reducing

functionality) to achieve acceptable performance at reduced size and cost.

However, as we make the paradigm shift from a macro to a small cell base station, there

are additional opportunities for further integration of the digital radio front end technology

and the baseband processing executed by the SoC, as well as portions of the radio front end

with the analog RF circuitry. Newer interface standards offer more optimized board layout and

interconnect options, offering additional optimization. Finally, by leveraging the radio front end

power amplifi er linearization techniques, even further gains can be made in small cell solution

power reductions without compromising performance.

Abstract

It is no secret that small cell base stations

are expected to be a major lifesaver in the

wireless data deluge by helping to provide

significant capacity gains as part of 3G and

4G wireless heterogeneous networks. While

the industry standards and algorithms are

mostly in place for these heterogeneous net-

works to function, power, performance and

cost hurdles must be met before small cell

base station solutions manifest into practi-

cal reality. Base station manufacturers tend

to focus their attention on the performance

and attributes of the small cell baseband

System on Chips (SoCs). The baseband SoC

silicon and software does contribute to a sig-

nificant portion of the small cell solution per-

formance, however the digital radio front end

portion of the design can have a substantial

impact as well and is often overlooked. This

white paper focuses on the digital front end

portion of the small cell base station and

delves into design factors that play a sig-

nificant role in achieving the performance

and power targets demanded by small cells.

Digital Radio Front-End strategies provide game-changing benefi ts for small cell base stations

Hardik Gandhi,Radio IP Development Manager,

Debbie Greenstreet,Strategic Marketing Director,

Joe Quintal,Senior Applications Engineer,

Texas Instruments

W H I T E P A P E R

Digital Radio Front-End strategies provide game-changing benefi ts for small cell base stations May 2013

2 Texas Instruments

Traditional macro base station architectures can roughly be divided into three functional categories: control

processing, baseband (BB) processing and radio front end. While some level of integration of these func-

tions is happening today, the control, baseband and some of the radio front end functions of a macro base

station are typically on a single board, with the bulk of the radio front end often times on a separate board,

and maybe even in a separate enclosure, as depicted in Figure 1. Macro base-station radios often have

dozens of integrated circuits partitioned along functional boundaries, with baseband and control processing

in a leading-edge process node digital CMOS SoC, digital front end technologies in digital CMOS ASICs or

ASSPs, data-converters in CMOS/BiCMOS technologies with 1–8 converters per device, and RF up and down

conversion functions like I/Q modulators and mixers, buffers, attenuators, etc. in typically separate devices

with optimal noise and linearity performance.

When small cell base stations became an integral topic of heterogeneous network planning several years

ago, the success strategy hinged on the assumption that they would be much smaller and lower power and

hence, employ a single-board solution with much fewer numbers of discrete components compared to macro

cells. Since then, as operators and the 3GPP organization continue to hone the small cell requirements and

algorithms, the performance requirements and complexity has grown, providing further challenges in meeting

those form factor and power expectations.

While macro cells typically range in output power from anywhere between 10W to 60W or more, the

small cell umbrella covers a variety of applications with different output power ranges (transmit power at the

antenna):

• Indoor femto cells: <200mW Pout, often Power over Ethernet (PoE) requirements

• Enterprise femto cells: 125–250mW Pout, often PoE+ requirements

From macro cells

to small cells

Figure 1: Macro base-station radios often have dozens of integrated circuits partitioned along functional boundaries


3Texas Instruments

• Outdoor pico cells: 1–2W Pout

• Micro cells: 2–5W Pout and larger

To meet area and cost targets in small cells, the stringent performance requirements imposed on analog/

RF components are often relaxed, with the expectation that evolution of digital impairment correction

algorithms would help recover any loss in performance. For example, in order to lower size, the transceiver

front ends would use surface or bulk acoustic wave (SAW or BAW) duplexers, which are much smaller and

cheaper than the ceramic/cavity duplexers normally used in macro cells. But they add signifi cantly to post-PA

RF power loss. Due to this the RF PAs for small cells often need to operate at 2–3dB higher Pout than what

the antenna actually radiates, pushing them further into non-linear operating regions, in turn requiring linear-

ization algorithms to ensure compliance with spectral emissions and modulation accuracy limits.

The fact that a vast majority of, perhaps all, small cell base stations will be deployed with enclosures that

have no special provisions for air cooling makes reducing every watt of power consumption (and resulting

heat dissipation) ever so important. Along with the motivation to reduce power, cost and area, small cells

also need to support newer features like network listening modes for spectral sniffi ng and synchronization,

and be more frequency agile to be able to support different 3G/4G frequency bands and signal bandwidths

with as few variants of the design as possible. These requirements drive a rethink of traditional architectures,

potentially evolving into a confi guration as depicted in Figure 2.

Next-generation small cell architectures can achieve these goals by taking advantage of advances in many

areas:

• Aggressive power optimization solutions

•• PA linearization techniques like digital pre-distortion (DPD) in combination with crest factor reduc-

tion (CFR) techniques help lower overall system power consumption signifi cantly, enabling more

PA choices – cheaper PAs and less expensive board and enclosure designs, which help minimize

BOM cost

Figure 2: Small cell base station architectures strive for single-board solutions with minimal number of discrete components


4 Texas Instruments

•• PA Linearization techniques also provide margin for system performance – extending the reach

and performance of a small cell solution (bigger cell size, less interference) which maximizes

system effi ciency

• Flexible IF architectures and optimized interfaces

•• For traditional high-performance macro base stations, a costly heterodyne design has until now

remained the de facto radio topology. A direct-conversion, or homodyne architecture, where the RF

signal is directly down-converted to a BB signal or vice versa without any intermediate frequency

stages has many attractive features. It is also referred to as a zero IF architecture. A zero-IF (or

very-low-IF) approach enables dramatically reducing component count and thus footprint and cost

of radio transceivers. Reducing the number of parts also simplifi es the supply chain and manufac-

turing and improves yield. Zero-IF architectures provide a great deal of fl exibility in frequency plan-

ning and allow multi-mode and/or multiband operations with minimal changes to baseband digital

and analog circuitry. Zero IF is not a new concept: radio designers have used these architectures

for low-end handsets and some base-station designs. Historically, many of the benefi ts offered by

a zero-IF architecture have been offset by a series of problems – I/Q distortion, DC offset and LO

leakage being some of the most critical. Until recently, these technical barriers in receiver design

have prohibited its practical implementation for high-performance base stations. But with advances

in digital SoCs, novel, adaptive digital compensation techniques can be implemented cost-effectively

to mitigate these problems, and allow radio designers to fully exploit all the advantages this archi-

tecture choice brings to the table.

•• Newer interface standards, like JESD204B, help optimize board-level layout, reduce power

consumption and enable faster time to market compared to traditional parallel LVDS/LVCMOS

interfaces.

• Higher levels of integration

•• Aggressive integration of traditionally discrete digital-/analog-processing components into area,

cost and power-optimized System-on-Chips. As shown in Figure 2, all of the high throughput

digital processing could be combined in one optimized leading-edge digital process node BB SoC,

combining control, baseband and radio processing, including some or all elements of the digital

radio front end processing. All of the data conversion and RF up/down conversion processing

could be combined in another radio SoC in a process node suited for analog/RF performance, with

elements of the digital front end processing included to provide required analog/RF impairment

correction.

Every watt of power saved with the above techniques translates into a proportional reduction in operational

expenditure for the carrier (OPEX) as well as into proportional reduction in cooling (enclosure) costs, and may

provide a wider choice in component selection and resulting reduction in capital expenditure (CAPEX). With


5Texas Instruments

the sheer number of small cell deployments projected, even an 10W power saving per small cell base sta-

tion (typical savings with CFR/DPD for a 0.5W 2×2 small cell) using advanced technologies can translate to

signifi cant savings in lifetime operating expenses (~$1M/year for a single dense metro with 70k small cells

deployed), as well as reducing the environmental impact of vast scale deployment.

Digitally assisted RF transceiver architectures utilizing the techniques described in this paper take us a

step closer to an all-digital radio and help next-generation base-station transceivers meet some of the newer

challenges as they emerge. These novel technologies enable the small cell architecture to take on a single-

board solution as depicted in Figure 2, and are discussed in more detail in the rest of the paper.

The air interface for cellular base-station radios requires essential digital, analog and RF signal-processing

components to prepare the modulated samples for transmission, or extract modulated data from received

signals at the antenna, and is functionally partitioned as depicted in Figure 3.

Beyond providing an interface (LVDS/LVCMOS or JESD204A/B SerDes) to analog-to-digital and digital-

to-analog data converters, the digital front end blocks perform a variety of critical functions which can be

roughly classifi ed into two categories:

1. Channelization and re-sampling functions – these are mandatory signal-processing functions to

be performed for any type of base station [micro or macro, Time Division Duplex (TDD) or Frequency

Division Duplex (FDD), 3G or 4G]

• Carrier fi ltering to comply with spectral emission masks and spectral leakage requirements, includ-

ing root-raised-cosine fi ltering (RRC) and/or linear channel equalization.

• Tuning and channel aggregation/distribution – essential for multi-carrier and/or multi-standard

base stations.

• Gain, phase, delay adjustments and power-measurement functions

Figure 4 on the following page shows a fl exible digital up/down converter block (DUC/DDC) that performs

these manda tory channelization and resampling functions. Programmable fi nite impulse response (FIR) fi lters,

Figure 3: Functional partitioning of cellular base station processing components

AntennaAnalogDFELayer 1Layer 2Layer 3 Transport

Radio

Interface

Backhaul

Interface

RF CarriersSamplesFramesPackets

Digital Front End

technologies overview


farrow-based resampling fi lters, cascaded-integrator-comb (CIC) fi lters and numerically controlled oscillators

(NCOs) and mixers are the essential signal processing blocks that perform these functions.

2. Power amplifi er (PA) linearization and RF impairment correction functions – these are

optional in the true sense, but often mandated by system effi ciency and cost requirements. Every

Analog/RF component suffers from some impairment (group delay, non-linear distortion, gain/phase

imbalance) at its optimal operating point (best effi ciency, best dynamic range, best noise fi gure) that

can be corrected by digital pre- or post-processing. Some of the key algorithms for impairment cor-

rection include:

• Crest Factor Reduction – required to limit signal peak to average power ratios to reduce PA

peak power and linearity requirements and hence system cost

• Digital Pre-Distortion – required to improve system linearity to allow PAs to be operated more

effi ciently, reducing both system cost (CAPEX) and operating expenses (OPEX)

• I/Q distortion and DC offset/LO-leakage correction – essential to enable zero-IF system

architectures, which in turn help reduce system cost and improve fl exibility.

Fourth-generation multi-carrier communication systems based on orthogonal frequency division multiplex-

ing (OFDM) as well as third-generation code-division multiple-access (CDMA) based systems exhibit signals

with high peak-to-average ratios (PARs), also known as crest factors. The non-constant envelope-modulation

techniques employed in such systems have stringent Error Vector Magnitude (EVM) requirements. This re-

quires a highly linear PA amplitude and phase response, often resulting in an increased PA back-off (driving

the PAs at lower output power levels) to maintain acceptable linearity to meet spectral mask and modulation

accuracy requirements. PAs are most power effi cient at close to peak drive levels. A high PA back-off results

in a drastic reduction in PA effi ciency.

6 Texas Instruments

Crest Factor

Reduction

Figure 4: Block diagram of an implementation of essential channelization and re-sampling functions

Symbol rateBase bandI/Q Data

To CFRorFrom RX

Small cellsto/from

L1/L2processingMacro cells

to/fromCPRI/OBSAI

Up sampledcompositeAntennastreams


Crest-factor-reduction techniques strive to reduce the peak-to-average power ratios of transmit signals by

deliberately introducing noise into the signals within the EVM and Adjacent Channel Power Ratio (ACPR) limits

imposed by the standards. Multi-carrier (and even single-carrier LTE) signals can have a peak-to-average

power ratio (PAR) as high as 12dB. The application of CFR can reduce signal peaks by as much as 4–6dB,

with acceptable in-band EVM degradation, allowing the PA to operate at higher input/output power levels

(resulting in more effi ciency) while maintaining linearity at the output of the PA.

Even for the smallest category of small cells with 100–200mW antenna output power, the 4–6dB decrease

in PA peak power through the use of CFR enables a roughly 2–4× difference in PA size and power effi ciency,

and a corresponding reduction in cost. This should be a key trade-off when doing power budgeting to meet

small cell power over Ethernet (PoE) limits.

Figure 5 shows CFR processing for a typical multi-carrier 3G test model signal. The Complementary Cumu-

lative Distribution Function (CCDF) plot on the right shows the signal sample distribution before and after CFR.

As can be seen, the signal peak-to-average power ratio is reduced from over 11dB to under 7dB. CFR can

reduce the PAR even more, but would be limited by the EVM limits set for the standard. The plot on the left

shows a snippet of the time domain waveform around a signal peak. A cancellation pulse scaled to the ap-

propriate gain and phase is applied to the signal to reduce the peak amplitude to below a set threshold. The

cancellation pulse needs to have an appropriate spectral shape suited to limit most of the noise in-band so as

not to violate spectral mask requirements.

CFR is usually applied in baseband at low sample rates suitable for digital signal processing. But the PAs

operate on signals up-converted to RF frequencies. This up-conversion process will generate signal peaks

that may not be visible at low baseband sample rates. For optimal peak cancellation, CFR signal processing

7Texas Instruments

Figure 5: Crest-factor-reduction performance example

CFR InputCFR Output

CFR Input (blue)CFR Output (red)Cancellation (green)

CFR Threshold

Cancelled Peaks


has to apply special interpolation techniques to estimate the RF signal peaks and apply fractionally adjusted

cancellation pulses to the signal. Also special care needs to be taken to accommodate multiple overlapping

peaks to limit over cancellation.

RF power amplifi ers achieve maximum power effi ciency near the saturation point of the PA (often listed as

Psat or P1dB or P3dB in PA datasheets). Due to the inherent nature of LDMOS/GaN/GaAs power transistors,

the PAs are most nonlinear near Psat (as shown in Figure 6 below), introducing severe distortion effects into

the transmitted signals. As shown in Figure 7 on the following page, these effects manifest themselves as

in-band distortion (degraded Error Vector Magnitude – EVM) and increased out-of-band spectral re-growth

(degraded Adjacent Channel Leakage Ratio – ACLR). Minimum EVM and ACLR requirements are defi ned by

regulatory bodies and OEMs need to add suffi cient margin on top of these requirements to allow for perfor-

mance variations with temperature and time (component aging). Very often the PA drive levels are backed off

such that the signal falls within the linear region of the PA to avoid these distortion effects. But at these back-

off regions, the PA power effi ciency is extremely poor. Linearization techniques need to be employed to oper-

ate the PA close to its saturation region, where it offers maximum output power and best power effi ciency.

A variety of power amplifi er linearization techniques such as RF feed-forward, RF feedback, RF/IF pre-

distortion and post-distortion have been proposed and implemented over the years. Of these, adaptive Digital

Pre-Distortion (DPD) schemes have proven to be the most effi cient and cost effective compared to traditional

Figure 6: Typical RF power amplifi er response

Input Power

Out

put P

ower

PA transistor characteristics cause signal distortion in and beyond this region because the output power drops below the ideal (linear) curve

Without CFR/DPD, the PA must be operated in this region to avoid distortion

Ideal (linear) PA response

Typical PA responseP3dB

P1dB

Optimal PA power efficiency close to the saturation points (P1dB/P3dB)

CFR reduces signal peaks to concentrate the signal power within a limited region –allows pushing the PA output power higher

DPD allows the PA to be operated closer to its saturation region to maximize efficiency -while still meeting Spectral Mask and Modulation Accuracy requirements

8 Texas Instruments

Digital

Pre-Distortion


analog/RF linearization techniques. Effi ciencies of traditional LDMOS Class AB power amplifi ers widely in use

today when operated under a back-off condition range from 3–10%. However, with crest factor reduction

and adaptive digital pre-distortion techniques, the effi ciencies can be improved by 3 to 5 times. Newer PA

topologies such as advanced Doherty, or Class AB with drain modulation, in combination with digital pre-

distortion and newer GaN or GaAs power transistors, can achieve effi ciencies over 50%.

For small cell power amplifi ers, DPD allows the PA to operate linearly closer to Psat, improving system ef-

fi ciency. DPD also enables more PA choices – cheaper PAs and less expensive board design minimizes BOM

cost, and provides margin for system performance – extending the reach and performance of a small cell

base station (bigger cell size, less interference). As discussed later in this whitepaper, DPD can provide from

~1W/antenna to ~20W/antenna system power savings for small cells ranging from 100mW to 2W antenna

output power with exponential increase in savings beyond that.

The idea behind Digital Pre-Distortion (DPD) is to cascade a non-linear system prior to the PA, which

provides an inverse response to the PA such that the cascaded system has a linear response. As shown in

Figure 8 on the following page, f(.) is the inverse of g(.) such that y is a linear representation of x (with the

desired amplifi cation factor). RF power amplifi ers have complex non-linear models, made more complicated

by the presence of memory effects. Memory effects refer to the bandwidth-dependant nonlinear behavior

often exhibited by RF PAs. These encompass envelope memory effects and frequency response memory

effects. Envelope memory effects are primarily a result of thermal hysteresis and electrical properties inherent

to PAs. Frequency memory effects are due to the variations in the frequency spacing of the transmitted signal

and are characterized by shorter time constants. These memory effects and non-linearity in general changes

over time and temperature and requires a real time adaptive DPD correction.

The plots in Figure 9 on page 11 show amplitude and phase responses of a typical RF PA, where with DPD

the resulting outputs (in blue) are clearly much more linear compared to the original PA outputs (in red). Typi-

cally, the harder a PA is driven to maximize its effi ciency, the more severe the non-linear distortion and the

Figure 7: Effects of RF PA non-linearities

Non-Linear distortion causes out of band spectral leakage (ACPR degradation)

Non-Linear and linear distortion causes in-band error (EVM degradation)

9Texas Instruments


wider the bandwidth a PA has to support, the more severe the memory effects are, making the need for DPD

even more pressing.

The DPD non-linearity order, memory depth and adaptation rates are often PA and signal dependent, and

a commercially viable small cell DPD solution has to envision all usage scenarios and draw reasonable trade-

offs between performance and hardware and software computational requirements.

Direct conversion or zero-IF radio architectures are a popular choice for small cell transceiver design since

they use fewer components and are easier to integrate comparing with the conventional heterodyne archi-

tectures. But those benefi ts also come with several well-known impairments, namely I/Q imbalance and DC

offset.

In a direct conversion transceiver, a quadrature modulator (QM) implements I/Q modulation and RF upcon-

version, while a quadrature demodulator (QDM) realizes I/Q demodulation and RF downconversion. Because

of the limitation in analog circuit precision, the quadrature carriers used in QM and QDM cannot have exactly

the same amplitude and a perfect 90-degree phase difference that are essential for accurate signal conver-

sion. Similarly, the analog reconstruction fi lters on the I and Q paths may not match exactly. These imperfec-

tions are called I/Q imbalance, which causes cross talk between I and Q channels and creates undesired

images of the original signal. In addition, because of limited isolation in analog components, some of the local

oscillator (LO) power leaks into the RF output, which creates LO spikes in transmitted signal and DC offset in

10 Texas Instruments

DC offset and

I/Q distortion

compensation

Figure 8: A model for PA linearization via digital pre-distortion

Typical PA responseDPD models a response inverse to the PA response

Input Signal Pre-Distorted Signal

PA Output Signal

DPD cancels out PA non-linearity and helps eliminate the distortion effects (ACPR and EVM degradation) from the PA output signal.


Figure 9: Power amplifi er memory effects

received signal. For traditional high IF heterodyne architectures these unwanted images can be fi ltered out by

analog/RF fi lters. But for zero-IF architectures these unwanted distortion images fall very close to or right on

top of the signal bands of interest, degrading signal SNR/EVM and/or violate spectral emissions limits, and

are very expensive (or often impossible) to eliminate via analog fi ltering. Digital pre- and post-compensation

techniques have to be employed to compensate for these distortions. Further complicating matters, these

distortion components are often frequency-dependent and may vary over time as components age, requiring

adaptive cancellation techniques.

Most existing compensation techniques treat transmit and receive I/Q imbalances separately. To compen-

sate for I/Q imbalance in the transmitter, the receive side is either assumed to have dedicated feedback loops

or digital demodulators with perfect quadrature carriers. To compensate for I/Q imbalance in the receiver,

the transmit side is usually assumed to be free of I/Q imbalance. For optimal zero-IF transceivers, the above

limitations are often impractical, resulting in the transmitter and receiver distortion components coexisting

and overlapping with each other, making extraction of the respective distortion compensation coeffi cients

ever more complicated.

The push for ever more compact small cell enclosures to minimize visual impact and installation costs

necessitates highly condensed transceiver board layouts. Traditional data-converter interfaces based on

parallel LVDS or LVCMOS signaling protocols require considerable board area and a great deal of analysis

and special layouts to minimize skew across data bits and optimize the setup/hold times relative to the clock

traces. Board bring up with high-speed parallel interfaces is a big challenge and often gates system/software

bring-up and delays time to market.

JESD204 is a new standard that defi nes a serial communications link between data converters (ADCs

and DACs) and other devices such as FPGAs, DSPs, ASICs and clocking devices. Similar to other more

well-known signaling protocols like PCIe or CPRI, this SerDes-based interface highly simplifi es the digital

11Texas Instruments

JESD204


data interface between devices. With the clock embedded in the data stream and embedded algorithms to

optimize sampling of the data bits, this simplifi es the routing between devices because there are much fewer

lanes on the PCB, and it simplifi es system design and board bring-up – no setup/hold time margin across as

many as 16 LVDS pairs with one data clock to worry about.

This new standard reduces the number of I/Os and thus pin count of devices allowing for smaller pack-

ages, and offers a fl exible and scalable solution to accommodate different data traffi c needs (e.g., multiple

ADCs on one JESD differential pair).

JESD204A (ratifi ed in 2008) and JESD204B (ratifi ed in 2011) both provide support for multiple lanes

per converter or multiple converters per lane. JESD204B supports data rates up to 12.5 Gbps compared to

3.125 Gbps for JESD204A. In addition, the JESD204B Subclass 1 operating mode provides support for ac-

curate synchronization across multiple converters. Multiple transmitters and receivers can get synchronized

in order to obtain a deterministic latency across multiple devices. This requires the use of an external system

reference signal (also known as SysRef) for synchronization. SysRef signals and device clocks need to be

distributed with matched length to all devices in order for the internal “local multi frame clocks (LMFC)” to

be synchronized properly. This ensures that the SysRef signal gets processed at the same instant across all

devices. But the JESD204B traces don’t have to be length matched. This provides a great deal of fl exibility

in board layouts while still maintaining synchronization and deterministic latency across devices. The spatial

benefi ts can be clearly seen in Figure 10.

Current macro cell system architectures often employ discrete DFE solutions with built-in linearization func-

tions (see reference 1 for an example). With macro cells typically designed for 10W–60W or higher antenna

output power, the 1–2W per antenna linearization cost is a small fraction of the overall system power budget

and is dwarfed by the power savings linearization brings to the table.

For small cell applications, with these discrete linearization solutions, the break-even PA output power at

which linearization starts adding net benefi t is high. But with high levels of integration and digital technology

Shrinking cost of

linearization


Dual 14bit Data converter• DDR LVDS• 16 diff pairs(14 data + clock + sync)

Dual 14bit Data converter• JESD204B• 4 diff pairs @ 3.1Gbit or• 2 diff pairs @ 6.2Gbit

Figure 10: Comparison of sample layouts with traditional LVDS and newer JESD interfaces

scaling, benefi t of linearization may be seen even for the lowest class of small cell applications. Many techno-

logical advances contribute to the shrinking cost of linearization, some of them being:

• High levels of integration in fi ner lithography SoCs:

As advanced DFE technologies were evolving over the last decade or so, low investment cost (but

high power and high production cost) ASIC/ASSP or FPGA solutions were effective given the pace

of change. But as DFE technologies have become more mature, and with built in fl exibility in newer

DFE architectures, integration with other high-throughput baseband and control-processing functions

in deep sub-micron process nodes becomes more attractive, and allows for signifi cant reduction in

power and cost for the same functionality compared to discrete solutions. As an example and shown in

Figure 11, over 4× reduction in power and 7× reduction in cost (die area) can be seen as we progress

from stand-alone DFE solutions in 90nm to integrated DFE solutions in 28nm.

• More power and area effi cient interfaces between devices:

Higher amounts of integration, and new high-speed serial interfaces can help with substantial reduc-

tion in board area and cost, eliminating what would have been seen as barriers to implementing

advanced high-sample-rate and adaptive algorithms. As we saw earlier, with JESD204B a 4 to 8×

reduction in the number of interface signals can be seen compared to traditional LVDS interfaces.

• Exploiting synergies enabled due to integration:

Various resources can be time shared between linearization and other functions required for small cell

operation – like sharing the feedback path with network listening for clock synchronization or spectral

monitoring, or sharing a DSP processor for L1/L2 processing as well as DPD and I/Q offset compensa-

tion adaptation. This helps reduce the number of components on the board signifi cantly, and makes

optimal use of all available resources.

13Texas Instruments

Figure 11: Reduction in power and area with semiconductor technology scaling

0

20

40

60

80

100

0 20 40 60 80 100

Are

a

Power

Technology Scaling90nm

65nm

40nm28nm


Lowering the bar

The theoretical analysis shown in the graph in Figure 12 is based on the following assumptions:

• 2× increase in PA effi ciency with CFR (typical 3dB PAR reduction and a linear PA effi ciency curve)

• 3× increase in PA effi ciency with DPD

• 4× drop in Linearization power from discrete to integrated DFE.

From this simplistic analysis it is apparent that with integrated DFE, benefi ts of linearization can be seen

even with output power as low as 150mW (region highlighted in the fi rst gray circle), whereas with discrete

DFE, the break even power at which linearization adds value is around 0.5W (region highlighted in second

gray circle).

As seen from the graph in Figure 12, even at 150mW output power, greater than 2W power saving per

transmitter can be realized by including integrated CFR and DPD in the solution – Especially important

when trying to meet PoE (power over Ethernet) requirements.

To validate the benefi ts of linearization for the lowest class of small cells, a variety of small cell power ampli-

fi ers from different vendors were evaluated in the lab with and without linearization, and the results are

encapsulated in Figure 13 on the following page. A 4-carrier W-CDMA test model signal was used for this

analysis. The PAs were tuned to output 200mW of transmit power, which after accounting for the 2–3dB post

PA loss due to fi lters/duplexers would correspond to a 100–125mW power level at the antenna. Per antenna

cost of integrated linearization (CFR/DPD datapath power, additional analog/RF power for requisite feedback

and differences in sampling/interface rates and power consumed in executing the adaptation algorithms) was

computed using 28-nm benchmarks and factored into the above analysis.

PA biasing and/or drain voltage can be tweaked to trade-off effi ciency and linearity. For the above

experiments, without linearization, the PAs were biased to optimal linearity to meet spectral mask (ACPR)


Figure 12: Theoretical analysis of linearization benefi ts

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60

Tota

l Pow

er C

onsu

mpt

ion

-PA

+ Li

near

izat

ion

(W)

Output Power (W)Power Consumptionwithout CFR/DPD (W)

Power Consumptionwith CFR, no DPD (W)

Power Consumptionwith discrete CFR & DPD (W)

Power Consumptionwith integrated CFR & DPD (W)


requirements. With linearization, the PAs were biased to optimal effi ciency, and the linearization algorithms

provided required ACPR improvement to meet spectral mask requirements.

As can be summarized from the results in Figure 13, even for this low end of small cell applications, with

CFR/DPD one can select a PA with > 3× better PA effi ciency (>27% compared to <8% for a PA without DPD,

or <7% for a PA without CFR/DPD). After factoring in the cost of linearization, 2.3× improvement in sys-

tem effi ciency is realized – while transmitting the same output power and meeting ACPR requirements. For a

2×2 single-band quad carrier MIMO 3G small cell with 100–125mW output power per antenna, inclusion of

linearization would provide >3.4W of system power savings, which may be critical to meet PoE budgets.

For higher output power levels, benefi ts of linearization are even more dramatic as can be seen from

Figure 14 on the following page.

Note that the analysis in Figure 14 shows only a comparison of power consumption with or without DPD,

with the assumption that the value CFR brings to the table for all classes of small cells is signifi cant enough

Figure 13: Experimental analysis of CFR/DPD benefi ts

15Texas Instruments


that its inclusion in any small cell solution is obviously warranted. If comparing results with neither CFR nor

DPD, against results with CFR and DPD, the projected power saving will be signifi cantly higher. CFR and

DPD are both key to optimal linearization – one without the other may give you less than half the benefi ts,

especially at higher output power levels.

It’s also worth mentioning that PA non-linear behavior and memory effects become worse as signal

bandwidth increases, leading to decreasing ACPR. Most PA datasheets provide performance results using

single-carrier W-CDMA test model (5MHz) or LTE (10MHz) data. But small cell deployment scenarios call for

a wide range of signal bandwidths to be supported, up to 40MHz occupied and beyond, sometimes with non-

contiguous carrier placements like in LTE rel10 and 11 with inter- or intra-band carrier aggregation, which

increases the edge-to-edge signal spread to be supported. The expanding signal bandwidth requirements

make the need for state-of-the-art linearization performance even more pressing, which may not be seem

obvious from reading PA datasheets.

Integrated digital front-end radio technology blocks are key additions to next-generation TI SoCs based on the

KeyStone II architectures, like the optimized dual-mode, dual-band small cell solution (TCI6630K2L) shown in

Figure 15 on the following page. Some of the key elements are briefl y described below.

• DDUC – Multiple digital up/down converter modules (shown as DDUCs in Figure 15) provide support

for a variety of signal types (W-CDMA, LTE-5MHz, LTE-10MHz, LTE-20MHz, etc.) with single- or multi-

band frequency confi gurations, with fl exibility that allows re-confi guring the BTS from single-mode

3G/4G to mixed-mode 3G/4G and vice versa. Also supported is both inter- and intra-band carrier


State-of-the-art DFE

capabilities integrated

in next-generation

TI KeyStone II SoCs

Figure 14: Experimental analysis of DPD benefi ts – Exponential power savings at higher output powers

0.0

5.0

10.0

15.0

20.0

25.0

30.0

0.10 0.50 1.00

Pow

er C

onsu

mpt

ion

PA+L

inea

rizat

ion

(W)

Antenna Output Power (W)(Assuming 3dB post-PA loss)

Power Consumptionwith CFR only, no DPD(Average 8% PA Efficiency)(W)Power Consumptionwith CFR/DPD(Including PA+Linearization power)(W)

200mW @ PA / 100mW @ Antenna

With CFR/DPD:~16% System

Efficiency~1.3W power

savings/antenna

1W @ PA / 0.5W @ AntennaWith CFR/DPD:~21% System

Efficiency~7.5W power

savings/antenna

2W @ PA / 1W @ AntennaWith CFR/DPD:~34% System

Efficiency~19W power

savings/antenna


aggregation with wide carrier separation fl exibility. As heterogenous network (Het-Net) strategies

evolve over the next few years, fl exibility to switch between carrier types, signal bandwidths and

frequency bands is of utmost importance.

• CFR – State-of-the-art algorithms in the TI CFR modules include advanced features like multiple

stages of peak cancellation with provisions to estimate fractional peaks and limit over cancellation,

automatic estimation of the CFR cancellation pulse shapes based on signal spectral content monitor-

ing, dynamic threshold adjustments and automatic gain control loops. As can be seen from the results

in Figure 16 below, optimal CFR cancellation and resultant signal PAR needs to be traded off against

system EVM budget, and a CFR algorithm that offers minimal EVM degradation with maximum PAR

reduction will be key to meeting system power and linearity constraints.

• DPD – An advanced datapath employing an optimized Volterra model to implement the PA pre-inverse

is an integral part of the TI DPD module. The Volterra coeffi cients are often adapted iteratively using a

17Texas Instruments

Figure 15: Block diagram of a KeyStone II-based TI baseband SoC with integrated digital radio functionality

TeraNet

Multicore Navigator

Security AccelerationPacAir and IP

Packet AccelerationPac

++**<<<<C66x DSPC66x DSP

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011100100010001111

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011100100010001111

Front End Dig. RadioBit Rate

NANDNAND USB3USB3 SPISPI 1GbE1GbE

EMIF and IO High Speed SerDes Lanes

CPRI/OBSAICPRI/OBSAI JESD204BJESD204B

USIMUSIM

I2CI2C UARTUART GPIOGPIO

PCIePCIe

Single-carrier LTE20:

Peak PAR (db) 11.01 7.76 7.39 7.01 6.62 6.21

EVM (%) 0.254 2.19 2.88 3.75 4.8 6.09

Dual-carrier LTE20:

Peak PAR (db) 10.66 7.77 7.4 7.03 6.64 6.28

Carrier 0 EVM (%) 0.551 2.44 3.07 3.87 4.87 6.07

Carrier 1 EVM (%) 0.538 2.43 2.86 3.87 4.8 6.06

Figure 16: Example TI CFR results (PAR vs. EVM) for single- and dual-carrier LTE-20 signals


variety of least-squares type algorithms (Conjugate Gradient, Kalman, etc.) which can be implemented

in software on the high-performance fl oating-point DSP or ARM® cores, with additional hardware ac-

celeration options available for faster iteration times.

Figure 17 shows the PA output spectrum without DPD (red) and after DPD correction has been applied

(blue) for a representative small cell PA biased to optimal effi ciency. As can be seen from this fi gure, TI’s

high-performance DPD enables the PA output spectrum to meet spectral mask requirements while achieving

highest obtainable power effi ciency for a given PA.

• TXRX – Novel joint I/Q distortion and DC offset/LO-leakage correction techniques like the one showed

in Figure 18 below and implemented in the TI TXRX modules (and accompanying integrated analog/

RF transceiver solution – AFE750x) can be used to jointly separate the transmit and receive side I/Q


Figure 18: A joint TX/RX I/Q distortion cancellation technique

Figure 17: Example TI DPD performance results for a small cell PA

Pre-DPD PA Output Spectrum –Violates Spectral Mask

Post-DPD PA Output Spectrum -Meets Spectral Mask With Margin

Adjacent Channel ACLR limit:

-45dBcAlternate Channel

ACLR limit: -50dBc


imbalance by introducing phase rotations in the analog domain. Since the phase rotations have differ-

ent effects on transmit and receive side I/Q imbalance, it enables using advanced digital algorithms to

separate the distortion effects and be able to pre-compensate (on the transmitter) or post-compensate

(on the receiver). Using real-time adaptive blind- or calibration-based least squares algorithms with

frequency dependent or frequency-independent compensation, optimal signal SNR and emissions-

mask compliance can be achieved. Figure 19 shows example results using such an algorithm, where

the I/Q distortion and DC offset images that would have violated spectral emissions requirements (or

degraded signal SNR if falling in-band underneath an adjacent carrier) are effectively eliminated down

to the system noise fl oor.

In addition to the above, TI’s digital radio modules include other functions like front-end and back-end

Automatic Gain Control loops (AGCs) that help maximize data-converter effi ciency and reduce dynamic range

required in baseband processing, transmit/receive equalizers to compensate for analog/RF fi lter droop and

phase distortion effects and digital protection functions to limit signal excursions to prevent damage to the

PA and associated circuitry. These are welcome additions to any BTS transceiver design, providing signifi cant

performance boost and RF/analog component cost reduction at the expense of low-cost integrated digital

logic.

State-of-the-art TI discrete and integrated data-converter, RF, clocking devices and BB SoCs now support

JESD204B subclasses 0 and 1 interfaces for optimal board designs, and enabling rapid system bring-up.

Last, but not least, integrated and tested, production-ready platform software from TI supporting not just

the baseband processing, but the digital radio processing, such as DDC/DUC, CFR and DPD libraries, as well

as analog/RF control enables rapid integration of system components and quick ramp to production.

As shown in Figure 20 on the following page, TI’s baseband SoC (TCI6630K2L) with integrated digital

front-end technologies, closely coupled with TI’s integrated radio transceiver solution (AFE750x) and other

clocking, power and RF devices from TI, with production ready software, enables a high-performance small

19Texas Instruments

Figure 19: Example I/Q distortion and DC offset cancellation results


cell solution with optimized power consumption meeting PoE requirements, with a low BOM cost, fast time to

market, and fl exibility to support evolving Het-Net strategies.

• Integrated DFE solutions bring the benefi ts of linearization to lower output power systems; the use of

CFR/DPD for PA output as low as 200mW (100–125mW at the antenna) seems not only viable, but

mandatory to meet stringent PoE requirements.

•• >3.4W total system power savings with CFR+DPD (compared to a solution with no CFR, no DPD)

for a 2×2 indoor small cell with a 25.5W overall system power budget seems very compelling.

• Power savings increase exponentially with higher output powers. Taking into account higher post-PA

losses of 2–3dB for small cells, savings can be much more.

•• >15W saved with DPD (compared to a solution with CFR but no DPD) for a 2×2 system at 1W

output power per PA (0.5–0.625W output power at the antenna)

•• >38W saved with DPD (compared to a solution with CFR but no DPD) for a 2×2 system at 2W

output power per PA (1–1.25W output power at the antenna)

• Dynamic nature of LTE signals, coupled with multi-mode and multiband requirements and the need

to extract the last ounce of system power savings make the need for best-in-class CFR and DPD

algorithms in integrated base-stations ever more compelling.


Conclusion

Figure 20: TI’s small cell system solution

AFE750x

JESD204B

JESD204B

2xA15

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DP

D/T

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Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringement of patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

SPRY236© 2013 Texas Instruments Incorporated

References

• Flexibility of any linearization solution is key towards reuse across multiple classes of base stations,

and to tackle future advances in PA technology – Could there be in the near future a PA available that

can simultaneously transmit multiple signal bands spread over 100s of MHz of spectrum with accept-

able effi ciency and cost? If so, a linearization solution which is capable of supporting such a PA is vital.

• TI’s fl exible small cell SoCs with best-in-class integrated-linearization solutions enable

optimum system cost and power consumption across different classes of small cells, and

provide an easy upgrade path to satisfy future evolutionary needs.

1. H. Gandhi, W. Abbott “A digital signal processing solution for PA linearization and RF impairment cor-

rection for multi-standard wireless transceiver systems,” in Proc. IEEE European Microwave Confer-

ence. Sept. 2010.

21Texas Instruments

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