digital integrated circuits© prentice hall 1995 design methodologies design for test

Digital Integrated Circuits © Prentice Hall 1995Design Methodologies

Designfor Test


Validation and Test of Manufactured Circuits

Components of DFT strategy

• Provide circuitry to enable test• Provide test patterns that guarantee reasonablecoverage

Goals of Design-for-Test (DFT)

Make testing of manufactured part swift andcomprehensive

DFT MantraProvide controllability and observability


Test Classification

Diagnostic test» used in chip/board debugging

» defect localization “go/no go” or production test

» Used in chip production Parametric test

» x [v,i] versus x [0,1]

» check parameters such as NM, Vt, tp, T


Design for Testability

M state regs

N inputs K outputs

K outputsN inputs

Combinational

Logic

Module

Combinational

Logic

Module

(a) Combinational function (b) Sequential engine

2N patterns 2N+M patterns

Exhaustive test is impossible or unpractical


Problem: Controllability/Observabilit

y

Combinational Circuits:controllable and observable - relatively easy to

determine test patterns

Sequential Circuits: State!Turn into combinational circuits or use self-test

Memory: requires complex patternsUse self-test


Test Approaches

Ad-hoc testing Scan-based Test Self-Test

Problem is getting harder » increasing complexity and heterogeneous

combination of modules in system-on-a-chip.» Advanced packaging and assembly techniques

extend problem to the board level


Generating and Validating Test-Vectors

Automatic test-pattern generation (ATPG)» for given fault, determine excitation vector (called test vector)

that will propagate error to primary (observable) output » majority of available tools: combinational networks only» sequential ATPG available from academic research

Fault simulation» determines test coverage of proposed test-vector set» simulates correct network in parallel with faulty networks

Both require adequate models of faults in CMOS integrated circuits


Fault Models

0

1

sa0

sa1

(output)

(input)

Most Popular - “Stuck - at” model

x1

x2x3

Z

, : x1 sa1

: x1 sa0 or

x2 sa0

: Z sa1

Covers almost all (other) occurring faults, such asopens and shorts.


Problem with stuck-at model: CMOS open fault

x1 x2

x1

x2

Z

Sequential effectNeeds two vectors to ensure detection!

Other options: use stuck-open or stuck-short modelsThis requires fault-simulation and analysis at the switch ortransistor level - Very expensive!


Problem with stuck-at model: CMOS short fault

‘0’

‘0’

‘0’

‘1’

C

A B

D

A

B

C

D

Causes short circuit betweenVdd and GND for A=C=0, B=1

Possible approach:Supply Current Measurement (IDDQ)but: not applicable for gigascale integration


Path Sensitization

Out

Techniques Used: D-algorithm, Podem

Goals: Determine input pattern that makes a faultcontrollable (triggers the fault, and makes its impactvisible at the output nodes)

sa011

0

11

10

1

Fault propagation

Fault enabling


Ad-hoc Test

Inserting multiplexer improves testability

I/O bus

Memory

Processor

data

addr

ess

I/O bus

Memory

Processor

data

addr

ess

selecttest


Scan-based Test

Logic

Combinational

Logic

Combinational

Reg

iste

r

Reg

iste

r

OutIn

ScanOutScanIn

A B


Polarity-Hold SRL (Shift-Register Latch)

Introduced at IBM and set as company policy

System Data

System Clock

Scan Data

Shift A Clock

D

C

SI

A

L1

L2Shift B Clock B

Q

Q

SO

SO


Scan-Path Register

SCANIN

IN

LOAD

SCAN PHI2 PHI1

KEEP

OUT

SCANOUT


Scan-based Test —Operation

TestScanIn

Test

Latch

In0

Out0

Test Test

Latch

In1

Out1

Test Test

Latch

In2

Out2

Test Test

Latch

In3

Out3

ScanOut

Test

1

2

N cycles 1 cycleevaluationscan-in

N cyclesscan-out


Scan-Path Testing

Partial-Scan can be more effective for pipelined datapaths

REG[5]

REG[4]

REG[3]REG[2]

REG[0]REG[1]

+

COMP

OUT

SCANIN

COMPIN

SCANOUT

A B


Boundary Scan (JTAG)Printed-circuit board

Logic

scan path

normal interconnect

Packaged IC

Bonding Pad

Scan-in

Scan-out

si so

Board testing becomes as problematic as chip testing


Self-test

(Sub)-Circuit

Under

Test

Stimulus Generator Response Analyzer

Test Controller

Rapidly becoming more important with increasingchip-complexity and larger modules


Linear-Feedback Shift Register (LFSR)

S0 S1 S2

R R R

1 0 00 1 01 0 11 1 01 1 10 1 10 0 11 0 0

Pseudo-Random Pattern Generator


Signature Analysis

R

Counter

In

Counts transitions on single-bit stream Compression in time


BILBO

S0

R R R

S1 S2

ScanOutScanIn mux

D2D1D0B0

B1

Operation modeB0

Normal

Scan

Signature analysis

1 1

0 0

1 0 Pattern generation or

0 1 Reset

B1


BILBO Application

Logic

Combinational

Logic

Combinational

BIL

BO

-B

BIL

BO

-A OutIn

ScanIn ScanOut


Memory Self-Test

FSMMemory Signature

AnalysisUnder Test

data

address &

R/W control

-in

data-out

Patterns: Writing/Reading 0s, 1s, Walking 0s, 1s Galloping 0s, 1s

digital integrated circuits© prentice hall 1995 design methodologies design for test

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