digital integrated circuits lecture 1: circuits &...
TRANSCRIPT
![Page 1: Digital Integrated Circuits Lecture 1: Circuits & Layouttwins.ee.nctu.edu.tw/courses/dic_10/lecture/Lec1.pdfDIC-Lec1 cwliu@twins.ee.nctu.edu.tw 1 Digital Integrated Circuits Lecture](https://reader031.vdocuments.mx/reader031/viewer/2022022506/5abf7cb17f8b9a5d718e52e2/html5/thumbnails/1.jpg)
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Digital Integrated CircuitsLecture 1: Circuits & Layout
Chih-Wei Liu
VLSI Signal Processing LAB
National Chiao Tung University
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Outline
A Brief History
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
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A Brief History
1958: First integrated circuitFlip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2003Intel Pentium 4 microprocessor (55 million transistors)
512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 yearsNo other technology has grown so fast so long
Driven by miniaturization of transistorsSmaller is cheaper, faster, lower in power!
Revolutionary effects on society
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Annual Sales
1018 transistors manufactured in 2003100 million for every human on the planet
0
50
100
150
200
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002
Year
Global S
emiconductor B
illings(B
illions of US
$)
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Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable1947: first point contact transistor
John Bardeen and Walter Brattain at Bell LabsSee Crystal Fireby Riordan, Hoddeson
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Transistor Types
Bipolar transistorsnpn or pnp silicon structureSmall current into very thin base layer controls large currents between emitter and collectorBase currents limit integration density
Metal Oxide Semiconductor Field Effect TransistorsnMOS and pMOS MOSFETSVoltage applied to insulated gate controls current between source and drainLow power allows very high integration
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1970’s processes usually had only nMOS transistorsInexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit μProc
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Moore’s Law
1965: Gordon Moore plotted transistor on each chipFit straight line on semilog scaleTransistor counts have doubled every 26 months
Year
Transistors
40048008
8080
8086
80286Intel386
Intel486Pentium
Pentium ProPentium II
Pentium IIIPentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
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Corollaries
Many other factors grow exponentially Ex: clock frequency, processor performance
Year
1
10
100
1,000
10,000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro/II/III
Pentium 4
Clock S
peed (MH
z)
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Complementary CMOS
Complementary CMOS logic gatesnMOS pull-down network
pMOS pull-up network
a.k.a. static CMOS
pMOSpull-upnetwork
outputinputs
nMOSpull-downnetwork
X (crowbar)0Pull-down ON
1Z (float)Pull-down OFFPull-up ONPull-up OFF
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Series and Parallel
nMOS: 1 = ONpMOS: 0 = ONSeries: both must be ONParallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
11 0 1
a
b
0 0
a
b
0
a
b
1
a
b
11 0 1
a
b
g1 g2
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Conduction Complement
Complementary CMOS gates always produce 0 or 1Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1Thus Y=1 when either input is 0Requires parallel pMOS
Rule of Conduction ComplementsPull-up network is complement of pull-downParallel -> series, series -> parallel
A
B
Y
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Compound Gates
Compound gates can do any inverting functionEx:
A
B
C
D
A
B
C
D
A B C DA B
C D
B
D
YA
CA
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
AOI22) INVERT,-OR-AND-(AND DCBAY ⋅+⋅=
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Signal Strength
Strength of signalHow close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0But degraded or weak 1
pMOS pass strong 1But degraded or weak 0
Thus nMOS are best for pull-down network
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Pass Transistors
Transistors can be used as switches
g
s d
g = 0s d
g = 1s d
0 strong 0Input Output
1 degraded 1
g
s d
g = 0s d
g = 1s d
0 degraded 0Input Output
strong 1
g = 1
g = 1
g = 0
g = 01
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Transmission Gates
Pass transistors produce degraded outputsTransmission gates pass both 0 and 1 well
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Transmission Gates
Pass transistors produce degraded outputsTransmission gates pass both 0 and 1 well
g = 0, gb = 1a b
g = 1, gb = 0a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a bg
gb
a bg
gb
a bg
gb
g = 1, gb = 0
g = 1, gb = 0
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Tristates
Tristate buffer produces Z when not enabled
11011000
YAENA Y
EN
A Y
EN
EN
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Tristates
Tristate buffer produces Z when not enabled
111001Z10Z00YAEN
A Y
EN
A Y
EN
EN
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Nonrestoring Tristate
Transmission gate acts as tristate bufferOnly two transistors
But nonrestoringNoise on A is passed on to Y
A Y
EN
EN
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Tristate Inverter
Tristate inverter produces restored outputViolates conduction complement ruleBecause we want a Z output
A
YEN
EN
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Tristate Inverter
Tristate inverter produces restored outputViolates conduction complement ruleBecause we want a Z output
A
YEN
A
Y
EN = 0Y = 'Z'
Y
EN = 1Y = A
A
EN
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Multiplexers
2:1 multiplexer chooses between two inputs
X11X011X00X0
YD0D1S0
1
S
D0
D1Y
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Multiplexers
2:1 multiplexer chooses between two inputs
1X110X0111X000X0YD0D1S
0
1
S
D0
D1Y
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Gate-Level Mux Design
How many transistors are needed?1 0 (too many transistors)Y SD SD= +
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Gate-Level Mux Design
How many transistors are needed? 201 0 (too many transistors)Y SD SD= +
44
D1
D0S Y
4
2
22 Y
2
D1
D0S
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Transmission Gate Mux
Nonrestoring mux uses two transmission gatesOnly 4 transistors
S
S
D0
D1YS
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Inverting Mux
Inverting multiplexerUse compound AOI22Or pair of tristate invertersEssentially the same thing
Noninverting multiplexer adds an inverter
S
D0 D1
Y
S
D0
D1Y
0
1S
Y
D0
D1
S
S
S
S
S
S
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4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selectsTwo levels of 2:1 muxesOr four tristates
S0
D0
D1
0
1
0
1
0
1Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
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D Latch
When CLK = 1, latch is transparentD flows through to Q like a buffer
When CLK = 0, the latch is opaqueQ holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
CLK
D Q
Latc
h D
CLK
Q
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D Latch Design
Multiplexer chooses D or old Q
1
0
D
CLK
QCLK
CLKCLK
CLK
DQ Q
Q
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D Flip-flop
When CLK rises, D is copied to QAt all other times, Q holds its valuea.k.a. positive edge-triggered flip-flop, master-slave flip-flop
Flop
CLK
D Q
D
CLK
Q
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D Flip-flop Design
Built from master and slave D latches
QMCLK
CLKCLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latc
h
Latc
h
D QQM
CLK
CLK
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Race Condition
Back-to-back flops can malfunction from clock skewSecond flip-flop fires lateSees first flip-flop change and captures its resultCalled hold-time failure or race condition
CLK1
D Q1
Flop
Flop
CLK2
Q2
CLK1
CLK2
Q1
Q2
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Nonoverlapping Clocks
Nonoverlapping clocks can prevent racesAs long as nonoverlap exceeds clock skew
We will use them in this class for safe designIndustry manages skew more carefully instead
φ1
φ1φ1
φ1
φ2
φ2φ2
φ2
φ2
φ1
QMQD
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Gate Layout
Layout can be very time consumingDesign gates to fit together nicely
Build a library of standard cells
Standard cell design methodologyVDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
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Example: NAND3
Horizontal N-diffusion and p-diffusion stripsVertical polysilicon gatesMetal1 VDD rail at topMetal1 GND rail at bottom32 λ by 40 λ
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Stick Diagrams
Stick diagrams help plan layout quicklyNeed not be to scaleDraw with color pencils or dry-erase markers
![Page 48: Digital Integrated Circuits Lecture 1: Circuits & Layouttwins.ee.nctu.edu.tw/courses/dic_10/lecture/Lec1.pdfDIC-Lec1 cwliu@twins.ee.nctu.edu.tw 1 Digital Integrated Circuits Lecture](https://reader031.vdocuments.mx/reader031/viewer/2022022506/5abf7cb17f8b9a5d718e52e2/html5/thumbnails/48.jpg)
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Wiring Tracks
A wiring track is the space required for a wire4 λ width, 4 λ spacing from neighbor = 8 λ pitch
Transistors also consume one wiring track
![Page 49: Digital Integrated Circuits Lecture 1: Circuits & Layouttwins.ee.nctu.edu.tw/courses/dic_10/lecture/Lec1.pdfDIC-Lec1 cwliu@twins.ee.nctu.edu.tw 1 Digital Integrated Circuits Lecture](https://reader031.vdocuments.mx/reader031/viewer/2022022506/5abf7cb17f8b9a5d718e52e2/html5/thumbnails/49.jpg)
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Well spacing
Wells must surround transistors by 6 λImplies 12 λ between opposite transistor flavorsLeaves room for one wire track
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Area Estimation
Estimate area by counting wiring tracksMultiply by 8 to express in λ
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Example: O3AI
Sketch a stick diagram for O3AI and estimate area( ) DCBAY ⋅++=
![Page 52: Digital Integrated Circuits Lecture 1: Circuits & Layouttwins.ee.nctu.edu.tw/courses/dic_10/lecture/Lec1.pdfDIC-Lec1 cwliu@twins.ee.nctu.edu.tw 1 Digital Integrated Circuits Lecture](https://reader031.vdocuments.mx/reader031/viewer/2022022506/5abf7cb17f8b9a5d718e52e2/html5/thumbnails/52.jpg)
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Example: O3AI
Sketch a stick diagram for O3AI and estimate area( ) DCBAY ⋅++=
![Page 53: Digital Integrated Circuits Lecture 1: Circuits & Layouttwins.ee.nctu.edu.tw/courses/dic_10/lecture/Lec1.pdfDIC-Lec1 cwliu@twins.ee.nctu.edu.tw 1 Digital Integrated Circuits Lecture](https://reader031.vdocuments.mx/reader031/viewer/2022022506/5abf7cb17f8b9a5d718e52e2/html5/thumbnails/53.jpg)
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Example: O3AI
Sketch a stick diagram for O3AI and estimate area( ) DCBAY ⋅++=