digital integrated circuits -...
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Digital Integrated Digital Integrated Digital Integrated Digital Integrated CircuitsCircuits
D i i C bi ti lD i i C bi ti lDesigning CombinationalDesigning CombinationalLogic CircuitsLogic Circuitsgg
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Combinational vs Sequential LogicCombinational vs Sequential LogicCombinational vs. Sequential LogicCombinational vs. Sequential Logic
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Static CMOS CircuitStatic CMOS CircuitStatic CMOS CircuitStatic CMOS Circuit
A i i i ( d i h i hiAt every point in time (except during the switching transients) each gate output is connected to eitherVDD or V via a low-resistive pathVDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuitof the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
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Static Complementary CMOSStatic Complementary CMOSStatic Complementary CMOSStatic Complementary CMOSVDDVDD
In1I 2 PUN PMOS only
F(In1,In2,…InN)
In2
InN
PUN PMOS only
( , , )In1In2 PDN
NMOS onlyInN NMOS only
PUN (pull-up network) and PDN (pull-down network) are dual logic networks
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NMOS Transistors NMOS Transistors i S i /P ll l C tii S i /P ll l C tiin Series/Parallel Connectionin Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
A
X YB Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
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NMOS Transistors pass a strong 0 but a weak 1
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PMOS Transistors PMOS Transistors i S i /P ll l C tii S i /P ll l C tiin Series/Parallel Connectionin Series/Parallel Connection
PMOS switch closes when switch control input is low
A B
PMOS switch closes when switch control input is low
X Y
A B
Y = X if A AND B = A + BY
A
X YB Y = X if A OR B = AB
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PMOS Transistors pass a “strong” 1 but a “weak” 0
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Threshold DropsThreshold DropsThreshold DropsThreshold DropsVDD VDDDDPUN DD
VDD
S D
0 → VDD 0 → VDD - VTnD S
VGS
V 0PDN
CL CL
V |V |VDD → 0PDN
CLVDD
VDD → |VTp|
CLSD
VGS
DD
S D
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Complementary CMOS Logic StyleComplementary CMOS Logic StyleComplementary CMOS Logic StyleComplementary CMOS Logic Style
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Example Gate: NANDExample Gate: NANDExample Gate: NANDExample Gate: NAND
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Example Gate: NORExample Gate: NORExample Gate: NORExample Gate: NOR
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Complex CMOS GateComplex CMOS GateComplex CMOS GateComplex CMOS Gate
AB
AC
OUT = D + A • (B + C)
D
DA
B C
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Constructing a Complex GateConstructing a Complex GateConstructing a Complex GateConstructing a Complex Gate
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Cell DesignCell DesignCell DesignCell Design
Standard CellsGeneral purpose logicGeneral purpose logicCan be synthesizedSame height varying widthSame height, varying width
Datapath CellsFor regular, structured designs (arithmetic)Includes some wiring in the cellFixed height and width
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Standard Cell Layout Methodology Standard Cell Layout Methodology ––198019801980s1980s
Routingh lchannel
VDD
signalsg
GND
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Standard Cell Layout Methodology Standard Cell Layout Methodology ––199019901990s1990s
No Routing V
Mirrored Cell
No Routingchannels VDD
VDD
M2
M3 GNDM3
GNDMirrored Cell
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GND
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Standard CellsStandard CellsStandard CellsStandard CellsN Well
C ll h i ht 12 t l t kCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch = repetitive distance between objects
VDD
repetitive distance between objects
Cell height is “12 pitch”
InOut
2λIn
Cell boundaryRails ~10λ
GND
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Standard CellsStandard CellsStandard CellsStandard CellsVDD VDDWith silicided
diffusionWith minimaldiffusionrouting
VDD
InOut In Out
O tIn
M2InOutIn
M1
GND GND
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Standard CellsStandard CellsStandard CellsStandard Cells
VDD 2-input NAND gate
VDD
BA B
B
OutA
GND
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Stick DiagramsStick DiagramsStick DiagramsStick Diagrams
Contains no dimensionsRepresents relative positions of transistors
VDDInverter
VDD
NAND2
Out
Inverter
Out
NAND2
In
Out
A
Out
BGND
AGND
B
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Stick DiagramsStick DiagramsStick DiagramsStick Diagrams
ACj
X
C
PUNLogic Graph
X C (A + B)
B
VDDX i
C
C
X = C • (A + B)
i j
DDX
AB
A B
j
GNDPDN
A GNDABC
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Two Versions of C Two Versions of C •• (A + B)(A + B)Two Versions of C Two Versions of C •• (A + B)(A + B)
CA B A B C
VDDVDD
X X
GNDGND
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Consistent Euler PathConsistent Euler PathConsistent Euler PathConsistent Euler Path
X
VX i
C
j
VDDX i
AB j
GND
AB
A B CGND A B C
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OAI22 Logic GraphOAI22 Logic GraphOAI22 Logic GraphOAI22 Logic Graph
A X PUNC
B D
VX
CD
C
X = (A+B)•(C+D) VDDX
ABD
A BGND
AB
PDNA GNDABCD
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Example: x = ab+cdExample: x = ab+cdExample: x ab cdExample: x ab cdx x
b c
VDDx
b c
VDDx
GND
a d
GND
a d
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
VDD
x
a c d
GND
(c) stick diagram for ordering {a b c d}b
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MultiMulti--Fingered TransistorsFingered TransistorsMultiMulti--Fingered TransistorsFingered TransistorsO fiOne finger Two fingers (folded)
Less diffusion capacitancep
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Properties of Complementary CMOS Gates Properties of Complementary CMOS Gates S h tS h tSnapshotSnapshot
High noise margins: VOH and VOL are at VDD and GND, respectively.
No static power consumption:No static power consumption:There never exists a direct path between VDD and VSS (GND) in steady-state modeVSS (GND) in steady state mode.
Comparable rise and fall times:(under appropriate sizing conditions)
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CMOS PropertiesCMOS PropertiesCMOS PropertiesCMOS PropertiesFull rail to rail swing; high noise marginsFull rail-to-rail swing; high noise marginsLogic levels not dependent upon the relative device sizes; ratiolessdevice sizes; ratiolessAlways a path to Vdd or Gnd in steady state; low output impedancelow output impedanceExtremely high input resistance; nearly zero steady state input currentsteady-state input currentNo direct path steady state between power and ground; no static power dissipationand ground; no static power dissipationPropagation delay function of load capacitance and resistance of transistors
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capacitance and resistance of transistors
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Switch Delay ModelSwitch Delay ModelSwitch Delay ModelSwitch Delay ModelReqA
AeqA
R
RpRpA
Rp
B
RpB
Rp
Ap
Ap
CLRn A
Rp Cint
A
Rn CLB
Rn CRn Rn CL
A
Rn Cint A BL
NAND2 INV NOR2
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NAND2
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Input Pattern Effects on DelayInput Pattern Effects on DelayInput Pattern Effects on DelayInput Pattern Effects on Delay
Delay is dependent on the pattern of inputsRp Rp
Low to high transitionboth inputs go low
R
Ap
Bp
g– delay is 0.69 Rp/2 CL
one input goes lowd l i 0 69 R C
CL
B
Rn
– delay is 0.69 Rp CL
High to low transitionb th i t hi hA
Rn Cint
both inputs go high– delay is 0.69 2Rn CL
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Delay Dependence on Input PatternsDelay Dependence on Input PatternsDelay Dependence on Input PatternsDelay Dependence on Input Patterns
2.5
3
A=B=1→0Input Data
PatternDelay(psec)
1 5
2
2.5
A=1 →0, B=1
V]
Pattern (psec)A=B=0→1 67
A=1 B=0→1 64
1
1.5
A=1, B=1→0
olta
ge [V
A 1, B 0→1 64
A= 0→1, B=1 61
A=B=1→0 45
0
0.5
0 100 200 300 400
Vo
A=B=1→0 45
A=1, B=1→0 80
A 1 0 B 1 81-0.50 100 200 300 400
time [ps]
A= 1→0, B=1 81
NMOS = 0.5μm/0.25 μmPMOS = 0 75μm/0 25 μm
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PMOS = 0.75μm/0.25 μmCL = 100 fF
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Transistor SizingTransistor SizingTransistor SizingTransistor Sizing
Rp Rp Rp
2 2 4
CR
A B B
Rp Ci
2 2 4
4CL
B
RnA
p Cint
24
A
Rn Cint
A
Rn
B
Rn CL2 111
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Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS Gate
B 8 6A
C4
83
6
OUT = D + A • (B + C)
D 4 6
OUT D A (B C)
DA
1
2
B C1
2 2
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FanFan--In ConsiderationsIn ConsiderationsFanFan--In ConsiderationsIn Considerations
DCBA DCBA
A CL Distributed RC model
C
BL
C3
Distributed RC model(Elmore delay)
D
C C2
C1
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deterioratesPropagation delay deteriorates rapidly as a function of fan-in –quadratically in the worst case.
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quadratically in the worst case.
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tt as a Function of Fanas a Function of Fan--InInttpp as a Function of Fanas a Function of Fan--InIn
1000
1250quadratic
ec)
Gates with a fan-in 750
t
t p(p
se greater than 4 should be avoided250
500tpH
L
tp
tpL
H
avoided.
0
250linear
fan-in2 4 6 8 10 12 14 16
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tt as a Function of Fanas a Function of Fan--OutOutttpp as a Function of Fanas a Function of Fan--OutOut
tpNOR2All gates have the tpNAND2
ec)
same drive current.tpINV
t p(p
se
Slope is aSlope is a function of “driving
2 4 6 8 10 12 14 16eff. fan-out
strength”
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tt as a Function of Fanas a Function of Fan--In and FanIn and Fan--OutOutttpp as a Function of Fanas a Function of Fan--In and FanIn and Fan--OutOut
Fan-in: quadratic due to increasing resistance and capacitanceresistance and capacitanceFan-out: each additional fan-out gate adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
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Fast Complex Gates:Fast Complex Gates:D i T h i 1D i T h i 1Design Technique 1Design Technique 1
T i t i iTransistor sizingas long as fan-out capacitance dominatesg
Progressive sizing
InN CLMNDistributed RC line
M1 > M2 > M3 > … > MN
C3In3 M3
(the fet closest to theoutput is the smallest)
C2
C1In1
In2
M1
M2 Can reduce delay by more than 20%; decreasing gains as t h l h i k
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C11 technology shrinks
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Fast Complex Gates:Fast Complex Gates:Design Technique 2Design Technique 2
Transistor ordering
critical path critical path
In
In3 M3 CL
CIn2
In1
M2
M3 CL
1
charged1
1
0→1 charged
dischargedC2
C1In1
In2
M1
M2 C2
C1In3
In2
M1
M2charged1
0→1charged 1 discharged
discharged
0→1
delay determined by time to discharge CL, C1 and C2
delay determined by time to discharge CL
EE141© Digital Integrated Circuits2nd Combinational Circuits38
discharge CL, C1 and C2 discharge CL
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Fast Complex Gates:Fast Complex Gates:D i T h i 3D i T h i 3Design Technique 3Design Technique 3Alternative logic structures
F = ABCDEFGHF ABCDEFGH
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Fast Complex Gates:Fast Complex Gates:D i T h i 4D i T h i 4Design Technique 4Design Technique 4
Isolating fan-in from fan-out using buffer insertioninsertion
C CCLCL
EE141© Digital Integrated Circuits2nd Combinational Circuits40
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Fast Complex Gates:Fast Complex Gates:D i T h i 5D i T h i 5Design Technique 5Design Technique 5
Reducing the voltage swing
t = 0 69 (3/4 (C V )/ I )tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )linear reduction in delayalso reduces power consumption
0.69 (3/4 (CL Vswing)/ IDSATn )
also reduces power consumptionBut the following gate is much slower!Or requires use of “sense amplifiers” on theOr requires use of sense amplifiers on the receiving end to restore the signal level (memory design)
EE141© Digital Integrated Circuits2nd Combinational Circuits41
(memory design)
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Sizing Logic Paths for SpeedSizing Logic Paths for SpeedSizing Logic Paths for SpeedSizing Logic Paths for Speed
Frequently, input capacitance of a logic path is constrainedLogic also has to drive some capacitanceExample: ALU load in an Intel’s pmicroprocessor is 0.5pFHow do we size the ALU datapath to achieve pmaximum speed?We have already solved this for the inverter ychain – can we generalize it for any type of logic?
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Buffer ExampleBuffer ExampleBuffer ExampleBuffer Example
In Out
CL1 2 N
( )∑=
⋅+=N
iiii fgpDelay
1(in units of τinv)
For given N: Ci+1/Ci = Ci/Ci-1To find N: Ci+1/Ci ~ 4How to generalize this to any logic path?
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Logical EffortLogical EffortLogical EffortLogical EffortCCRkDelay L
⎟⎟⎞
⎜⎜⎛
+⋅= 1
( )fgpC
CRkDelayin
unitunit
⋅+=
⎟⎟⎠
⎜⎜⎝
+=
τγ
1
( )fgpp – intrinsic delay (3kRunitCunitγ) - gate parameter ≠ f(W)g – logical effort (kRunitCunit) – gate parameter ≠ f(W)g g ( unit unit) g p ( )f – effective fanout
N li thi t i tNormalize everything to an inverter:ginv =1, pinv = 1
Divide everything by τinv(everything is measured in unit delays τinv)
EE141© Digital Integrated Circuits2nd Combinational Circuits44
( y g y inv)Assume γ = 1.
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Delay in a Logic GateDelay in a Logic GateDelay in a Logic GateDelay in a Logic Gate
Gate delay:d = h + pp
effort delay intrinsic delay
Effort delay:
h = g fg
logical effort
effective fanout = C /Ceffort Cout/Cin
Logical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate size
EE141© Digital Integrated Circuits2nd Combinational Circuits45
Effective fanout (electrical effort) is a function of load/gate size
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Logical EffortLogical EffortLogical EffortLogical Effort
Inverter has the smallest logical effort and intrinsic delay of all static CMOS gatest s c de ay o a stat c C OS gatesLogical effort of a gate presents the ratio of its input capacitance to the inverter capacitanceinput capacitance to the inverter capacitance when sized to deliver the same currentLogical effort increases with the gateLogical effort increases with the gate complexity
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Logical EffortLogical EffortLogical EffortLogical Effort
EE141© Digital Integrated Circuits2nd Combinational Circuits47
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Logical Effort of GatesLogical Effort of GatesLogical Effort of GatesLogical Effort of Gates
y (d
)tpINV
tpNANDg =
zed
dela
y tpINV
g =
g p =d =
Nor
mal
i
p =d =
1 2 3 4 5 6 7
F(Fan-in)
Fan-out (h)1 2 3 4 5 6 7
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Logical Effort of GatesLogical Effort of GatesLogical Effort of GatesLogical Effort of Gates
y (d
)tpINV
tpNANDg = 4/3
zed
dela
y tpINV
g = 1
g 4/3p = 2d = (4/3)h+2
Nor
mal
i
p = 1d = h+1
1 2 3 4 5 6 7
F(Fan-in)
Fan-out (h)1 2 3 4 5 6 7
EE141© Digital Integrated Circuits2nd Combinational Circuits49
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Logical Effort of GatesLogical Effort of GatesLogical Effort of GatesLogical Effort of Gates
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Add Branching EffortAdd Branching EffortAdd Branching EffortAdd Branching Effort
Branching effort:
pathon
pathoffpathonC
CCb
−
−− +=
pathon
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Multistage NetworksMultistage NetworksMultistage NetworksMultistage Networks
( )∑=
⋅+=N
iiii fgpDelay
1
Stage effort: hi = gifi
i 1
Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2 gNPath logical effort: G g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB
Path delay D = Σdi = Σpi + Σhi
EE141© Digital Integrated Circuits2nd Combinational Circuits52
Path delay D = Σdi = Σpi + Σhi
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Optimum Effort per StageOptimum Effort per StageOptimum Effort per StageOptimum Effort per Stage
HhN
When each stage bears the same effort:
HhN =N Hh =
Eff ti f t f h t hf
Stage efforts: g1f1 = g2f2 = … = gNfN
Minimum path delay
Effective fanout of each stage: ii ghf =
( ) PNHpfgD Niii +=+= ∑ /1ˆ
u pat de ay
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Optimal Number of StagesOptimal Number of StagesOptimal Number of StagesOptimal Number of StagesFor a given loadFor a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizingFind optimal number of stages and optimal sizing
N NpNHD += /1invNpNHD +=
( ) 0ln /1/1/1 ++∂ NNN HHHD ( ) 0ln /// =++−=∂ inv
NNN pHHHN
NHh ˆ/1=Substitute ‘best stage effort’
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Logical EffortLogical EffortLogical EffortLogical Effort
From Sutherland Sproull
EE141© Digital Integrated Circuits2nd Combinational Circuits55
From Sutherland, Sproull
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Example: Optimize PathExample: Optimize PathExample: Optimize PathExample: Optimize Path
EE141© Digital Integrated Circuits2nd Combinational Circuits56
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Example: Optimize PathExample: Optimize PathExample: Optimize PathExample: Optimize Path
EE141© Digital Integrated Circuits2nd Combinational Circuits57
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Example: Optimize PathExample: Optimize PathExample: Optimize PathExample: Optimize Path
1 a
b c 5a 5
g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1
Effective fanout, H = 5G = 25/9
g1 1 g2 5/3 g3 5/3 g4
G = 25/9F = 125/9 = 13.9f = 1.93a = 1.93b = fa/g2 = 2.23
fb/ 5 /f 2 59EE141© Digital Integrated Circuits2nd Combinational Circuits
58c = fb/g3 = 5g4/f = 2.59
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Example Example –– 88--input ANDinput ANDExample Example –– 88--input ANDinput AND
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Method of Logical EffortMethod of Logical EffortMethod of Logical EffortMethod of Logical Effort
Compute the path effort: F = GBHFind the best number of stages N ~ log FFind the best number of stages N log4FCompute the stage effort f = F1/N
Sk h h h i h hi b fSketch the path with this number of stagesWork either from either end, find sizes: Cin = Cout*g/f
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
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SummarySummarySummarySummary
Sutherland,S llSproullHarris
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Ratioed LogicRatioed LogicRatioed LogicRatioed Logic
EE141© Digital Integrated Circuits2nd Combinational Circuits62
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Ratioed LogicRatioed LogicRatioed LogicRatioed Logic
VDD VDD VDD
Resistive Depletion PMOS
F
RLLoad
F FVSS
es s ve DepletionLoad
PMOSLoadVT < 0
PDNIn1In2In3
In1In2In3
PDNIn1In2In3
PDN
VSS VSS VSS
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
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Ratioed LogicRatioed LogicRatioed LogicRatioed LogicVDD
LoadResistive
N transistors + Load
• VOH = VDD
•
RLLoad OH DD
• VOL = RPN
In1
F RPN + RL
• Assymetrical responsePDNIn2
In3
Assymetrical response
• Static power consumption
VSS• tpL= 0.69 RLCL
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Active LoadsActive LoadsActive LoadsActive LoadsVDD VDD
DepletionLoad
PMOSLoadVT < 0
F F
VSS
Load LoadT
In1In2In
PDNIn1In2In
F
PDN
VSS
In3
VSS
In3
SS SS
depletion load NMOS pseudo-NMOS
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PseudoPseudo--NMOSNMOSPseudoPseudo NMOSNMOS
VDD
A B C D
FCL
VOH = VDD (similar to complementary CMOS)
2kn VDD VTn–( )VOL
VOL2
2-------------–
⎝ ⎠⎜ ⎟⎛ ⎞ kp
2------ VDD VTp–( )
2=
VOL VDD VT–( ) 1 1kpkn------–– (assuming that VT VTn VTp )= = =
EE141© Digital Integrated Circuits2nd Combinational Circuits66
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
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PseudoPseudo--NMOS VTCNMOS VTCPseudoPseudo--NMOS VTCNMOS VTC
3.0
2.0
2.5
W/Lp = 4
1.5
t[V
]
p
W/L = 2
0.5
1.0Vou
t W/Lp = 2
W/Lp = 1W/Lp = 0.5
0.0 0.5 1.0 1.5 2.0 2.50.0
V [V]
W/Lp = 0.25
EE141© Digital Integrated Circuits2nd Combinational Circuits67
Vin [V]
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Improved LoadsImproved LoadsImproved LoadsImproved Loads
VDD
M1M2 M1 >> M2Enable
F
CA B C D
CL
Adaptive Load
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Adaptive Load
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Improved Loads (2)Improved Loads (2)Improved Loads (2)Improved Loads (2)VDD VDD
M1 M2
Out Out
M1 M2
PDN1 PDN2AAB
VSS VSS
BB
VSS VSS
Differential Cascode Voltage Switch Logic (DCVSL)
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DCVSL ExampleDCVSL ExampleDCVSL ExampleDCVSL Example
O
Out
Out
B B B B
A A
XOR NXOR t
EE141© Digital Integrated Circuits2nd Combinational Circuits70
XOR-NXOR gate
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DCVSL Transient ResponseDCVSL Transient ResponseDCVSL Transient ResponseDCVSL Transient Response
2.5
A B1.5
olta
ge[V
] A B
A B
A B0.5
V
A,BA,B
0 0.2 0.4 0.6 0.8 1.0-0.5
Time [ns]
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PassPass--TransistorTransistorLogicLogic
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PassPass--Transistor LogicTransistor LogicPassPass Transistor LogicTransistor Logic
O A
B
Inpu
ts Switch
Network
OutOut
A
BB
B
• N transistors• No static consumption
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Example: AND GateExample: AND GateExample: AND GateExample: AND Gate
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NMOSNMOS--Only LogicOnly LogicNMOSNMOS--Only LogicOnly Logic
3.0
In
VDD
In
x1.5μm/0.25μm 2.0
e[V
]
xOut
In
DDOut0.5μm/0.25μm
0.5μm/0.25μm 1.0Volta
ge0 0.5 1 1.5 20.0
Time [ns][ ]
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NMOSNMOS--only Switchonly SwitchNMOSNMOS only Switchonly Switch
C = 2.5V
A 2 5 V
C = 2.5 V
M2A = 2.5 V
B
CL
A = 2.5 V B
M1
Mn
CL 1
Th h ld lt lVB does not pull up to 2.5V, but 2.5V -VTN
Threshold voltage loss causesstatic power consumption
NMOS has higher threshold than PMOS (body effect)
EE141© Digital Integrated Circuits2nd Combinational Circuits76
NMOS has higher threshold than PMOS (body effect)
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NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring TransistorLevel Restoring TransistorLevel Restoring Transistor
M
VDDVDDLevel Restorer
M2
MrB
X
M1
Mn OutAX
• Advantage: Full Swing• Restorer adds capacitance, takes away pull down current at X
EE141© Digital Integrated Circuits2nd Combinational Circuits77
• Ratio problem
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Restorer SizingRestorer SizingRestorer SizingRestorer Sizing
3.0•Upper limit on restorer size
2.0 W/Lr =1.75/0.25 [V]
pp•Pass-transistor pull-downcan have several transistors in stack
1.0
W/Lr =1.50/0.25
Vol
tage
stack
0 100 200 300 400 5000.0
W/Lr =1.0/0.25 W/Lr =1.25/0.25
0 100 200 300 400 500Time [ps]
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Solution 2: Single Transistor Pass Gate with Solution 2: Single Transistor Pass Gate with VV =0=0VVTT=0=0
VDD
VDD0V 2.5V
OutVDD 0V
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
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Complementary Pass Transistor LogicComplementary Pass Transistor LogicComplementary Pass Transistor LogicComplementary Pass Transistor Logic
FPass-Transistor
Network
AABB
(a)
FPass-TransistorNetwork
AABB
Inverse
(a)
B B B B B B
A
B
A
BF=AB F=A+B
A
A F=A⊕ΒÝ
A
B
A
BF=AB F=A+B
A
A F=A⊕ΒÝ
(b)
EE141© Digital Integrated Circuits2nd Combinational Circuits80
OR/NOR EXOR/NEXORAND/NAND
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Solution 3: Transmission GateSolution 3: Transmission GateSolution 3: Transmission GateSolution 3: Transmission GateC
A B
C
A B
C
B
C
B
CC
C = 2.5 V
BCL
A = 2.5 V
L
C = 0 V
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Resistance of Transmission GateResistance of Transmission GateResistance of Transmission GateResistance of Transmission Gate
30
V2 5 V
2.5 VRn
20 ms
Rn
RpVout
0 V
2.5 V
Rp
stan
ce, o
hm
p
0 V10
Res
is
Rn || Rp
0.0 1.0 2.00
Vout, V
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PassPass--Transistor Based MultiplexerTransistor Based MultiplexerPassPass Transistor Based MultiplexerTransistor Based Multiplexer
VDD
S S
A
SVDD
AM2
M
S F
M1
B
S
GND
In InS S
EE141© Digital Integrated Circuits2nd Combinational Circuits83
In1 In2S S
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Transmission Gate XORTransmission Gate XORTransmission Gate XORTransmission Gate XOR
B
BM2
AF
A
M2
F
BM1 M3/M4
B
B
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Delay in Transmission Gate NetworksDelay in Transmission Gate NetworksDelay in Transmission Gate NetworksDelay in Transmission Gate Networks2.5 2.5 2.5 2.5
V1 Vi-1
C
.5
0 0
Vi Vi+1
CC
.5
0
Vn-1 Vn
CC
.5
0
In
V1 Vi Vi+1 Vn-1 VnInReqReq Req Req
(a)
C CC
In
CC
(b)
Req Req Req Req Req Req
m
CC CC CC CCIn
(c)
EE141© Digital Integrated Circuits2nd Combinational Circuits85
(c)
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Delay OptimizationDelay OptimizationDelay OptimizationDelay Optimization
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Transmission Gate Full AdderTransmission Gate Full AdderTransmission Gate Full AdderTransmission Gate Full Adder
P
AVDD
VDDCi
S
P
P S G iPA A Ci
A V
S
P
P Sum Generation
BVDD
AP
AB VDD
Co
P
P Carry GenerationCi
ACi
oCi
PSetup PSetup
Similar delays for sum and carry
EE141© Digital Integrated Circuits2nd Combinational Circuits87
y y
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Dynamic LogicDynamic LogicDynamic LogicDynamic Logic
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Dynamic CMOSDynamic CMOSDynamic CMOSDynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type) d idevices
D i i i l hDynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodeshigh impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors
EE141© Digital Integrated Circuits2nd Combinational Circuits89
transistors
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Dynamic GateDynamic GateDynamic GateDynamic Gate
MpClkOut Out
Clk Mp
In1
In PDN
Out
CL
Out
AIn2 PDNIn3
MClkB
C
MeClkClk Me
Two phase operationTwo phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)
EE141© Digital Integrated Circuits2nd Combinational Circuits90
Evaluate (CLK 1)
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Dynamic GateDynamic GateDynamic GateDynamic Gate
MpClkOut Out
Clk Mp on 1off
In1
In PDN
Out
CL
Out
A((AB)+C)
In2 PDNIn3
MClkB
C
MeClkClk Me
Two phase operation
offon
Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)
EE141© Digital Integrated Circuits2nd Combinational Circuits91
Evaluate (Clk 1)
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Conditions on OutputConditions on OutputConditions on OutputConditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
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Properties of Dynamic GatesProperties of Dynamic GatesProperties of Dynamic GatesProperties of Dynamic GatesL i f ti i i l t d b th PDN lLogic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary CMOS)CMOS)
Full swing outputs (VOL = GND and VOH = VDD)Non ratioed sizing of the devices does not affectNon-ratioed - sizing of the devices does not affect the logic levelsFaster switching speeds
reduced load capacitance due to lower input capacitance (Cin)d d l d it d t ll t t l di (C t)reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging CL
EE141© Digital Integrated Circuits2nd Combinational Circuits93
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Properties of Dynamic GatesProperties of Dynamic GatesProperties of Dynamic GatesProperties of Dynamic GatesOverall power dissipation usually higher than staticOverall power dissipation usually higher than static CMOS
no static current path ever exists between V and GNDno static current path ever exists between VDD and GND (including Psc)no glitchingg ghigher transition probabilitiesextra load on Clk
PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTnTn, M, IH IL q Tn
low noise margin (NML)Needs a precharge/evaluate clock
EE141© Digital Integrated Circuits2nd Combinational Circuits94
Needs a precharge/evaluate clock
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Issues in Dynamic Design 1: Issues in Dynamic Design 1: Ch L kCh L kCharge LeakageCharge Leakage
Clk M
CLK
CL
ClkOut
A
Mp
L
Clk
A
Me
VOutEvaluate
Leakage sources
Precharge
g
Dominant component is subthreshold current
EE141© Digital Integrated Circuits2nd Combinational Circuits95
Dominant component is subthreshold current
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Solution to Charge LeakageSolution to Charge LeakageSolution to Charge LeakageSolution to Charge LeakageK
Clk Mp Mkp
Keeper
CLA Out
Clk M
B
Clk Me
Same approach as level restorer for pass-transistor logic
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Issues in Dynamic Design 2: Issues in Dynamic Design 2: y gy gCharge SharingCharge Sharing
Charge stored originally on
C
Clk
AOut
Mp CL is redistributed (shared) over CL and CA leading to reduced robustnessCL
CAB=0
A reduced robustness
Clk CBMe
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Charge Sharing ExampleCharge Sharing ExampleCharge Sharing ExampleCharge Sharing Example
Clk
O tCL=50fFA A
Out
B B B !BCa=15fF Cb=15fF
CCCc=15fF Cd=10fF
Clk
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Charge SharingCharge SharingCharge SharingCharge Sharingcase 1) if ΔVout < VTn
VDD
CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=
) Vout VTn
Clk
Out
Mp
L DD L out ( ) a DD Tn X( )( )
orCa
CLA
Out
M ΔVout Vout t( ) VDD– aCL-------- VDD VTn VX( )–( )–= =
X
Ca
A Ma
Ca⎜ ⎟⎛ ⎞
case 2) if ΔVout > VTnB = 0CaMb
ΔVout VDDa
Ca CL+----------------------
⎝ ⎠⎜ ⎟⎛ ⎞
–=CbClk Me
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Solution to Charge RedistributionSolution to Charge RedistributionSolution to Charge RedistributionSolution to Charge Redistribution
Clk Mp
OutMkp
Clk
A
B
Out
Clk Me
B
Precharge internal nodes using a clock driven transistorPrecharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
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Issues in Dynamic Design 3: Issues in Dynamic Design 3: Backgate CouplingBackgate Coupling
C
Clk
A=0
Out1MpOut2
C In
=1 =0
CL1
B=0
A=0 CL2
Clk Me
Dynamic NAND Static NAND
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Backgate Coupling EffectBackgate Coupling EffectBackgate Coupling EffectBackgate Coupling Effect
3
2
Out11 Clk
0In Out2
-10 2 4 6Time, ns
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Issues in Dynamic Design 4: Clock Issues in Dynamic Design 4: Clock F dth hF dth hFeedthroughFeedthrough
Coupling between Out and
C
Clk
AOut
Mp Clk input of the precharge device due to the gate to drain capacitance SoCL
B
A drain capacitance. So voltage of Out can rise above VDD. The fast rising
Clk Me
above VDD. The fast rising (and falling edges) of the clock couple to Out.
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Clock FeedthroughClock Feedthrough
2.5Clk
Out
Clock feedthrough
1.5
In1
In2
Out
0.5
2
In3 In &Clk
-0.5Clk
In4 Out
0 0.5 1Time, ns
Clock feedthrough
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Other EffectsOther EffectsOther EffectsOther Effects
Capacitive couplingSubstrate couplingSubstrate couplingMinority charge injectiony g jSupply noise (ground bounce)
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Cascading Dynamic GatesCascading Dynamic GatesCascading Dynamic GatesCascading Dynamic GatesV
Clk Mp MpClk
Out2
V
Clk
Out1In
Out2
In
Clk Me MeClk Out1 VTn
Out2 ΔV
t
Only 0 → 1 transitions allowed at inputs!
EE141© Digital Integrated Circuits2nd Combinational Circuits106
y p
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Domino LogicDomino LogicDomino LogicDomino Logic
MClk MClk M
I
MpClk Out1MpClk
Out2Mkp
1 → 11 → 0
0 → 0In1
In2 PDNIn3
In4 PDNIn5
0 → 1
In3
MeClk
5
MeClk
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Why Domino?Why Domino?Why Domino?Why Domino?
ClkClk
Ini PDNInj
IniInj
PDN Ini PDNInj
Ini PDNInj
Clk
Like falling dominos!
EE141© Digital Integrated Circuits2nd Combinational Circuits108
Like falling dominos!
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Properties of Domino LogicProperties of Domino LogicProperties of Domino LogicProperties of Domino Logic
Only non-inverting logic can be implementedy g g pVery high speed
static inverter can be skewed only L H transitionstatic inverter can be skewed, only L-H transitionInput capacitance reduced – smaller logical effort
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Designing with Domino LogicDesigning with Domino LogicDesigning with Domino LogicDesigning with Domino LogicVDD VDD
MpClk MpClk M
VDD
Out1
Out2
Mr
PDNIn1In2In3
PDNIn4
Me
In3
Clk MeClk
Can be eliminated!
Inputs = 0during precharge
EE141© Digital Integrated Circuits2nd Combinational Circuits110
g p g
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Footless DominoFootless DominoFootless DominoFootless Domino
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Differential (Dual Rail) DominoDifferential (Dual Rail) DominoDifferential (Dual Rail) DominoDifferential (Dual Rail) Domino
MpClk MkpClk
O t ABMkp Mp
onoff
A
Out = AB Out = AB1 0 1 0
B!A !B
MeClk
Solves the problem of non-inverting logic
EE141© Digital Integrated Circuits2nd Combinational Circuits112
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npnp--CMOSCMOSnpnp--CMOSCMOS
MpClk Out1MeClk
In1
Out1
In4 PUN
1 → 11 → 0
In2 PDNIn3
In5
Out2(to PDN)
0 → 00 → 1
MeClk MpClk (to PDN)
Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUN
EE141© Digital Integrated Circuits2nd Combinational Circuits113
Only 1 → 0 transitions allowed at inputs of PUN
![Page 114: Digital Integrated Circuits - chungbuk.ac.krbandi.chungbuk.ac.kr/~bdyang/lecture_digital_integrated... · 2011-02-06 · Static CMOS Circuit Aiii(dihihiAt every point in time (except](https://reader030.vdocuments.mx/reader030/viewer/2022040515/5e7112eee078044d555eba47/html5/thumbnails/114.jpg)
NORA LogicNORA LogicNORA LogicNORA Logic
MpClk Out1MeClk
1 → 1
In1
I PDN
In4 PUNIn
1 → 11 → 0
In2 PDNIn3
In5
MClk
Out2(to PDN)
0 → 00 → 1
MeClk MpClk ( )
to other to otherto otherPDN’s
to otherPUN’s
EE141© Digital Integrated Circuits2nd Combinational Circuits114
WARNING: Very sensitive to noise!