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TRANSCRIPT
Adib AbrishamifarEE Department
IUST
Lecture 2 – Silicon Semiconductor Technology
Digital Integrated Circuit Design
silicon substratesource drain
gategateoxideoxide oxideoxide
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Various Fabrication Processes Bipolar Processes Isolation Methods MOS Processes BiCMOS Processes MASK Silicon on Insulator (SOI)
Contents
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Various Fabrication Processes
Planarization (Polishing the Wafers) Photolithography Oxide Growth Etching Doping (Diffusion, Ion Implantation) Metallisation
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Planarization
Problem: adding multiple layers of metal is difficult over uneven chip structures
Solution: Planarization Add thick oxide layer over chip Use Chemical-Mechanical Polishing (CMP) to grind flat
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Process by which the surface of a substrate can be patterned with micronsize features. Photolithography requires a photoresist layer to be put on the substrate, a photomask that has the required pattern and a UV light source
Photolithography
P-type substrate
Thick field oxide
photoresist
UV light
Mask
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Is process which results in the formation of a SiO2 layer on the top of thesilicon circuit. This oxide layer can be used as a mask for subsequent processing steps or can be used as an electrical component within a transistor such as the gate oxide of a MOSFET
Oxide Growth
Silicon Wafer Silicon Wafer
SiN / SiO2FOX FOXSiO2 Thin Oxide
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Processes involve the removal of SiO2 layers from the surface of the siliconsubstrate usually using a photoresist mask to pattern the SiO2 layer. This can be done by wet etching, (by dipping the photoresistpatterned substrate into buffered HF(hydro-fluoric acid) , where the acid willattack the exposed regions of SiO2 ) or by dry etching (where a chemical gas plasma will attack and etch the exposed SiO2 regions)
Etching
anisotropic etch (ideal)resist
layer 1
layer 2
resist
layer 1
layer 2
isotropic etchundercut
resist
layer 1
layer 2
preferential etchundercut
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Is the process of introducing dopant atoms into silicon for creating n and p type regions. Doping can be realized by diffusion or by ion implantation
Doping
nn+
pp+
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Is generally carried out by evaporating aluminium and depositing it on asilicon wafer. The process of evaporation is carried out in a vacuum chamber where an aluminium source is heated
Metallisation
Thick field oxide
P-type substrate
N+ N+
GateSiO2
Contact holesMetal
Transistor gate length
Substrate metaldefines active region
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NMOS CMOS TTL ECL
PMOS
Bi-MOS Many linearICs
2I L
Thickfilm
Thinfilm
Inertsubstrate
MOS Bipolar
Silicon
MESFET Bipolar
GaAs
Activesubstrate
Microelectronics
Major Processes Used in IC Fabrication
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Bipolar Processes
Processes: JIM SBC (Standard Buried Collector) CDI (Collector-Diffused Isolation) 3D (Triple-Diffused) Oxide Isolated (Isoplanar) Self Aligned Polysilicon Emitter (Dual Polysilicon)
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Basic Bipolar Process (Analog)
Mask1: Buried Mask2: Isolation Mask3: Base Mask4: Emitter Mask5: Contact Mask6: Metal Mask7: Pad
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(a) after selective diffusion of the n +- buried layer;
(b) after epitaxial layer decomposition and growth of protective oxide;
(c) after isolation diffusion;
(d) after drain collector diffusion;
(e) after base diffusion
Junction Isolated Monolithic (Digital)
Features: Large Size Low speed Schottky
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P- bulk
C E B
Vertical NPNBase width: 1µmEmitter area : 5µm×5µmAssociated to parasitic PNP
Node+ Node-Bulk N-Well
N-Well
P+
C E
N+N epi
P+P+P+
P- Substrate
P+P+
P-P+
P-P+
N+
N+ BL
C BC C CC Lateral PNP
Base witdh : 2.5µmEmitter area : 6µm×6µmAssociated to 2 parasitic PNPs
Emitter associated PNP (act in forward mode)Collector associated PNP (act in reverse mode)Both in saturation
P-implanted Resistor2kΩ/r
N epi
P- Substrate
P+
SUB
P+
P
N+
N+ P+P-P+
P-P+
N+ BL
C C C
JIM Devices and Parasitic
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Standard Buried Collector
Triple-Diffused (3D)
Collector-Diffused Isolation
Bipolar Processes (SBC,CDI,3D)
low collector series resistance n-epilayer
Schottky
low collector series resistance p-epilayer
rce is not good Base width is large No Schottky
high collector series resistance No Schottky
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Oxide Isolated Bipolar Process (Isoplanar)
Features: No Schottky Small Size is SmallC µ
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Features: Two polysilicon layers
P+ for extrinsic base, N+ for emitter Self-aligned with emitter window
opening Trench Isolation
Oxide lined, polysilicon filled Shallow Trench Isolation (STI)
Isolate base/emitter active region from collector reach-thru
Highly doped extrinsic base à lower Rb
Emitter (arsenic) diffused from N+ poly No Schottky
Dual Polysilicon
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Isolation Methods
Isolations: Lateral Triple Diffusion 2-Sided Diffusion (Double-Diffused Epitaxial) Oxide Isolated
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Localized oxidation isolation (LOCOS)
Lateral Isolation
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Bird’s Peak
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Other Isolations
Triple Diffusion
2-Sided Diffusion
Double-Diffused Epitaxial
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Oxide Isolated
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MOS Processes
Metal Gates Self-Aligned Gates MOS Technologies NMOS N-well P-well Twin-well Epitaxy Double-well
Modern CMOS Process Dual-Well Trench-Isolated Shallow Trench
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Source & drain p+ diffusion
Wet oxidation for field oxide
Dry oxidation for gate oxide
Al metallization for gate and contacts to S & D
Metal Gates
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Define active areasEtch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
CMOS Process at a Glance
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Self-Aligned Gates (2D)
Create thin oxide in the “active”regions, thick elsewhere
Deposit polysilicon
Etch thin oxide from active region (poly acts as a mask for the diffusion)
Implant dopant
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silicon substratesource drain
gategateoxideoxide oxideoxide
top nitride
metal connection to source
metal connection to gate
metal connection to drain
polysilicon gatedoped silicon
field oxide
gate oxide
Fabrication Process MOS (3D)
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silicon substrate
Fabrication Process MOS (3D)
The manufacture of a single MOS transistor begins with a silicon substrate
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silicon substrate
oxideoxide
field oxide
A layer of silicon dioxide (field oxide) provides isolation between devices manufactured on the same substrate
Fabrication Process MOS (3D)
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silicon substrateoxideoxide
photoresistphotoresist
Photoresist provides the means for transferring the image of a mask onto the top surface of the wafer
Fabrication Process MOS (3D)
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Ultraviolet Light
Shadow on photoresist
photoresistphotoresist
Exposed area of photoresist
Chrome platedglass mask
silicon substrate
oxideoxide
Ultraviolet light exposes photoresist .
Fabrication Process MOS (3D)
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Unexposed area of photoresist
silicon substrate
Exposed area of photoresist
oxideoxidephotoresistphotoresist
Exposed photoresist becomes soluble and can be easily removed by the develop chemical
Fabrication Process MOS (3D)
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silicon substrate
oxideoxide
photoresistphotoresistphotoresist
Unexposed photoresist remains on surface of oxide to serve as a temporary protective mask for areas of the oxide that are not to be etched
Fabrication Process MOS (3D)
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silicon substrate
oxideoxide oxideoxide
silicon substrate
photoresistphotoresist
Areas of oxide protected by photoresist remain on the silicon substrate while exposed oxide is removed by the etching process
Fabrication Process MOS (3D)
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silicon substrate
oxideoxide oxideoxide
silicon substrate
field oxide
The photoresist is stripped off -- revealing the pattern of the field oxide
Fabrication Process MOS (3D)
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silicon substrate
oxideoxide oxideoxide
gate oxidegate oxide
thin oxide layer
A thin layer of oxide is grown on the silicon and will later serve as the gate oxide insulator for the transistor being constructed
Fabrication Process MOS (3D)
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silicon substrate
oxideoxide oxideoxide
gate oxide
The gate insulator area is defined by patterning the gate oxide with a masking and etching process
Fabrication Process MOS (3D)
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silicon substrate
oxideoxide oxideoxide
gate oxide
polysiliconpolysilicongate oxide
Polysilicon is deposited and will serve as the building material for the gate of the transistor
Fabrication Process MOS (3D)
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silicon substrate
oxideoxide oxideoxidegate
gategate
ultra-thin gate oxide
polysilicongate
The shape of the gate is defined by a masking and etching step
Fabrication Process MOS (3D)
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silicon substrate
oxideoxide oxideoxidegategategate
photoresistphotoresist
Scanning direction of ion beam
implanted ions in active region of transistors
Implanted ions in photoresist to be removed during resist strip.
source drain
ion beam
Dopant ions are selectively implanted through windows in the photoresist mask
Fabrication Process MOS (3D)
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silicon substrate
oxideoxide oxideoxidegate
gategatesource drain
doped silicon
The source and drain regions of the transistor are made conductive by implanting dopant atoms into selected areas of the substrate
Fabrication Process MOS (3D)
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silicon substrate
source draingategate
top nitridetop nitride
A layer of silicon nitride is deposited on top of the completed transistor to protect it from the environment
Fabrication Process MOS (3D)
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silicon substratesource drain
gategate
contact holes
Holes are etched into selected parts of the top nitride where metal contacts will be formed
Fabrication Process MOS (3D)
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silicon substratesource drain
gategateoxideoxide oxideoxide
metal contacts
Metal is deposited and selectively etched to provide electrical contacts to the three active parts of the transistor
Fabrication Process MOS (3D)
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silicon substratesource drain
gategateoxideoxide oxideoxide
top nitride
metal connection to source
metal connection to gate
metal connection to drain
polysilicon gatedoped silicon
field oxide
gate oxide
Completed structure of a simple MOS transistor
Fabrication Process MOS (3D)
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Planarization Copper Interconnect Low-k dielectric for interconnect High-k dielectric for transistor gates Optical problems (and fixes)
Current Trends in Fabrication
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NMOS P-well N-well Twin-well Epitaxy Double-well
MOS Technologies
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NMOS Technology
Mask1: Active
Mask2: Gate
Mask3: Contact
Mask4: Metal
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P-well (tub)
N-well
Epitaxy Double-well
Other MOS Technology
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N-well CMOS Process
n-well
n-well maskMask(Top View)Cross Setion of Physical Structure
p-substrate n-well
p-substrate n-well
p-substrate n-well
active mask
active
nitrideoxide
p-channelstop
active maskresistImplant (Boron)
channel stop
(a)
(b)
(c)
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N-well CMOS Process
p-substrate n-well
active mask
p-substrate n-well
polysilicon
²lateral movement of field oxide results in “bird’s beak” (Fig.(d))
(e)
(d)
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N-well CMOS Process
n+ n+
p-substrate n-wellp+ p+
n+ n+
p-substrate n-well
n+ mask
n+ mask
p+ mask
p+ mask
poly
light implant
oxide
n- n-
shallow drain implant
poly
heavier implant
n- n-
n+ n+
LDD structureoxide spacer
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N-well CMOS Process
n+ n+
p-substrate n-wellp+ p+
n+ n+
p-substrate n-wellp+ p+
contact mask
metal mask
contact mask
metal mask
l final step (not shown):1. passivation
protect silicon surface from contaminants2. openings to bond pads
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Twin-well CMOS Process
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Modern CMOS Processes
Dual-Well Trench-Isolated Shallow Trench
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p-
p-epip well n well
p+n+
gate oxide
Al (Cu)
tungsten
SiO2
SiO2
TiSi2
field oxide
Dual-Well Trench-Isolated
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p+
p-epi Base material: p+ substrate with p-epi layer
p+
After plasma etch of insulating trenches using the inverse of the active area mask
p+
p-epi SiO2
3SiN
4
After deposition of gate-oxide and sacrifical nitride (acts as a buffer layer)
Dual-Well Trench-Isolated Walk-Through
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SiO2 After trench filling, CMP planarization, and removal of sacrificial nitride
After n-well and VTpadjust implants
n
After p-well and VTnadjust implants
p
Dual-Well Trench-Isolated Walk-Through
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After polysilicondeposition and etch
poly(silicon)
After n+ source/dram and p+ source/drain implants. These steps also dope the polysilicon.
p+n+
After deposition of SiO2 insulator and contact hole etch
SiO2
Dual-Well Trench-Isolated Walk-Through
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After deposition and patterning of first Al layer
Al
After deposition of SiO2 insulator, etching of via’s, deposition and patterning of second layer of Al
AlSiO2
Dual-Well Trench-Isolated Walk-Through
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Grow Pad Oxide: A very thin (~200Å) layer of silicon dioxide (SiO2) is grown on the surface by reacting silicon and oxygen at high temperatures. This will serve as a stress relief layer between the silicon and the subsequent nitride layer
Silicon Substrate P+
Silicon Epi Layer P-
Pad Oxide
Shallow Trench Formation
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Deposit Silicon Nitride: A layer (~2500Å) of silicon nitride (Si3N4) is deposited using Chemical Vapor Deposition. This will serve as apolish stop layer during trench formation
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Shallow Trench Formation
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Pattern Photoresist for Definition of Trenches: One of the most critical patterning steps in the process. 0.5 - 1.0 microns of resist is spun, exposed, and developed
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Photoresist
Shallow Trench Formation
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Etch Nitride and Pad Oxide: A reactive ion etch (RIE) utilizing fluorine chemistry is used
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Photoresist
Shallow Trench Formation
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Etch Trenches in Silicon: A reactive ion etch (RIE) utilizing fluorine chemistry is used. Defines transistor active areas
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Photoresist
Transistor Active Areas
Isolation Trenches
Shallow Trench Formation
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Remove Photoresist: An oxygen plasma is used to burn off the resist layer
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Transistor Active Areas
Isolation Trenches
Shallow Trench Formation
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Fill Trenches with Oxide: A CVD oxide layer is deposited to conformally fill the trenches. The oxide will prevent “cross-talk”between the transistors in the circuit
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Future PMOS Transistor
Silicon Dioxide
Future NMOS Transistor
No current can flow through here!
Shallow Trench Formation
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Polish Trench Oxide: The surface oxide is removed using a Chemical Mechanical Polish (CMP). The CMP process is designed to stop on silicon nitride
Silicon Substrate P+
Silicon Epi Layer P-
Silicon Nitride
Future PMOS Transistor Future NMOS Transistor
No current can flow through here!
Shallow Trench Formation
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Remove Silicon Nitride: A wet etch in hot phosphoric acid (H3PO4) is used, completing formation of Shallow Trench Isolation (STI)
Silicon Substrate P+
Silicon Epi Layer P-
Future PMOS Transistor Future NMOS Transistor
Shallow Trench Formation
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Completed Shallow Trenches - Layout View:
Trench Oxide
Cross Section
Bare Silicon
Shallow Trench Formation
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Pattern Photoresist for N-Well Formation: A non-critical masking layer, utilizing thicker resist to block the implant
Silicon Substrate P+
Silicon Epi Layer P-
Future PMOS Transistor Future NMOS Transistor
Photoresist
Shallow Trench: Well Formation
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Implant N-Well: A deep (high-energy) implant of phosphorous ions creates a localized N-type region for the PMOS transistor
Silicon Substrate P+
Silicon Epi Layer P-
Future NMOS Transistor
Photoresist
N- Well
Phosphorous (-) Ions
Shallow Trench: Well Formation
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Strip N-Well Photoresist:
Silicon Substrate P+
Silicon Epi Layer P-
Future NMOS TransistorN- Well
Shallow Trench: Well Formation
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Photoresist
Pattern Photoresist for P-Well Formation: A non-critical masking layer, utilizing thicker resist to block the implant
Silicon Substrate P+
Silicon Epi Layer P-
Future NMOS TransistorN- Well
Shallow Trench: Well Formation
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Implant P-Well: A deep (high-energy) implant of boron ions creates a localized P-type region for the NMOS transistor
Silicon Substrate P+
Silicon Epi Layer P-
Photoresist
N- Well
Boron (+) Ions
P- Well
Shallow Trench: Well Formation
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Strip P-Well Photoresist:
Silicon Substrate P+
Silicon Epi Layer P-
N- Well P- Well
Shallow Trench: Well Formation
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Anneal Well Implants: This step repairs damage to the silicon surface caused by the implants and electrically activates the dopants. It also drives the dopants somewhat deeper, but Rapid Thermal Processing is used to minimize dopant spreading
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Shallow Trench: Well Formation
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Completed Wells - Layout View:
Trench OxideN- WellP- Well
Cross Section
Shallow Trench Formation
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Grow Sacrificial Oxide: A thin (~250Å) oxide layer is grown to capture defects in the silicon surface
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Sacrificial Oxide
Shallow Trench: Gate Formation
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Remove Sacrificial Oxide: Sac ox is immediately removed in a wet HF solution, leaving behind a clean silicon surface
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Shallow Trench: Gate Formation
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Grow Gate Oxide: This is the most critical step in the process! A very thin (20-100Å) oxide layer is grown that will serve as the gate dielectric for both transistors. It must be extremely clean, and grown to a very precise thickness (+/- 1Å)
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Gate Oxide
Shallow Trench: Gate Formation
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Deposit Polysilicon: Polycrystalline silicon is deposited using Chemical Vapor Deposition to a thickness of 1500-3000 Å
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Polysilicon
Shallow Trench: Gate Formation
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Pattern Photoresist to Define Gate Electrodes: This is the most critical patterning step in the process! Precise sizing of the poly gate length is a first-order determinant of transistor switching speed. The highest-technology patterning systems are used (i.e. DUV) along with thinner-than-normal photoresist due to the critical nature of the layer
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Photoresist
Channel Length
Polysilicon
Shallow Trench: Gate Formation
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Etch Polysilicon: Reactive Ion Etching using fluorine chemistry is used. The etch must precisely transfer the gate dimensions from the resist to the polysilicon
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Photoresist
Channel Length
Shallow Trench: Gate Formation
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Strip Photoresist: This completes the formation of the “gate stack”
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Gate Oxide
Poly Gate Electrode
Shallow Trench: Gate Formation
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Completed Gates - Layout View:
Trench OxideN- WellP- Well
Cross Section
Polysilicon
Shallow Trench Formation
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Oxidize Polysilicon: A thin layer of oxide is grown on top of the polysilicon to act as a buffer between the poly and the subsequent silicon nitride layer
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Gate Oxide
Poly Gate Electrode
Poly Re-oxidation
Shallow Trench: Oxidize Polysilicon
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Pattern Photoresist for NMOS Transistor Tip Implant:
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Photoresist
Shallow Trench: Source/Drain Formation
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NMOS Transistor Tip Implant: A very shallow (low energy) and low dose implant of arsenic ions begins the formation of the NMOS transistor source and drain. The “tip” will serve to reduce hot electron effects near the gate region
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Photoresist
Arsenic (-) Ions
N Tip
Shallow Trench: Source/Drain Formation
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Strip Photoresist:
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N Tip
Shallow Trench: Source/Drain Formation
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Pattern Photoresist for PMOS Transistor Tip Implant:
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Photoresist
N Tip
Shallow Trench: Source/Drain Formation
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PMOS Transistor Tip Implant: A very shallow (low energy) and low dose implant of BF2 ions begins the formation of the PMOS transistor source and drain. The “tip” will serve to reduce hot electron effects near the gate region
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Photoresist
BF2 (+) Ions
N TipP Tip
Shallow Trench: Source/Drain Formation
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Strip Photoresist:
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N TipP Tip
Shallow Trench: Source/Drain Formation
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Deposit Silicon Nitride Layer: Using Chemical Vapor Deposition to achieve a very conformal film. Thickness: 1200-1800Å
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Silicon Nitride
Thinner Here
Thicker Here
N TipP Tip
P Tip
Shallow Trench: Source/Drain Formation
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Etch Nitride to Form Spacer Sidewalls: Using a carefully controlled RIE etch, the thin nitride is removed from the horizontal surfaces, but the sidewalls remain. These sidewalls will precisely position the implants that form the transistor sources and drains
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Spacer Sidewall
N TipP Tip
P Tip
Shallow Trench: Source/Drain Formation
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Pattern Photoresist for NMOS Transistor Source/Drain Implant:
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Photoresist
N TipP Tip
Shallow Trench: Source/Drain Formation
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NMOS Transistor Source/Drain Implant: A shallow and high-dose implant of arsenic ions completes the formation of the heavily-doped NMOS transistor source and drain. The spacer shadows the implant near the gate region
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
Photoresist
Arsenic (-) Ions
N+ Drain N+ SourceP Tip
Shallow Trench: Source/Drain Formation
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Strip Photoresist:
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP Tip
Shallow Trench: Source/Drain Formation
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Pattern Photoresist for PMOS Transistor Source/Drain Implant:
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ Source
Photoresist
P Tip
Shallow Trench: Source/Drain Formation
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PMOS Transistor Source/Drain Implant: A shallow and high-dose implant of BF2 ions completes the formation of the heavily-doped PMOS transistor source and drain. The spacer shadows the implant near the gate region
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
BF2 (+) Ions
Photoresist
N+ Drain N+ SourceP+ SourceP+ Drain
Shallow Trench: Source/Drain Formation
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Strip Photoresist and Anneal Implants: Use Rapid Thermal Annealing to virtually eliminate dopant migration in the shallow source and drains. The electronic devices are now completely formed. All that remains is to connect them together
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ SourceP+ Drain
Lightly Doped “Tips”
Shallow Trench: Source/Drain Formation
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Trench Oxide Polysilicon
Cross Section
N- WellP- Well
N+ Source/DrainP+ Source/Drain
Spacer
Shallow Trench: Source/Drain FormationCompleted Sources and Drains - Layout View: (tips are not shown as they are beneath the spacer)
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Strip Surface Oxides: A quick dip in HF to expose bare silicon in the source, gate, and drain areas
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
Shallow Trench: Salicide Formation
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Deposit Titanium: Use a sputterer to deposit a thin (200-400Å) layer of titanium across the entire wafer surface
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ SourceTitanium
Shallow Trench: Salicide Formation
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Titanium Silicide Formation: Rapid Thermal Processing in nitrogen at 800 oC causes the titanium to react with silicon, forming titanium silicide, where the two are in contact. In other areas, the titanium isunchanged. This process perfectly aligns the silicide to the exposed silicon, and is called Self-Aligned Silicide, or Salicide
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
Titanium SilicideUnreacted Titanium
Shallow Trench: Salicide Formation
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Titanium Etch: The unreacted titanium is removed using a wet etch in NH4OH + H2O2. The titanium silicide remains. TiSi2 provides an ohmiccontact between silicon and metal
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
Titanium Silicide
Shallow Trench: Salicide Formation
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Deposit BPSG: Silicon dioxide, doped with small amounts of boron and phosphorous to enable film reflow and to getter contaminants, is deposited using Chemical Vapor Deposition. Approximate thickness is 1 micron. This layer will electrically insulate the devices from the 1st metal layer
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Shallow Trench: 1st Interconnect Layer
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Polish BPSG: Use Chemical Mechanical Polishing to achieve a flat surface on the BPSG layer. If not removed, the bumps on the surface from the underlying topography would cause focus problems for the subsequent photolithography steps and degrade metal step coverage
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Shallow Trench: 1st Interconnect Layer
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Pattern Photoresist to Define Contacts: Contacts are openings in the BPSG layer enabling electrical access to the devices below. This is a critical photolithography step
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Photoresist
Shallow Trench: 1st Interconnect Layer
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Contact Etch: A carefully designed RIE etch using fluorine chemistry to achieve vertical sidewalls
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Photoresist
Shallow Trench: 1st Interconnect Layer
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Strip Photoresist:
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Shallow Trench: 1st Interconnect Layer
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Titanium Nitride Deposition: A sputterer is used to deposit TiN to a thickness of about 200Å. This layer will help the subsequent tungsten layer to adhere to the oxide
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Titanium Nitride
Shallow Trench: 1st Interconnect Layer
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Tungsten Deposition: Tungsten is chosen because it deposits conformally (via CVD) and can fill the contact holes. The thickness must be at least half of the diameter of the contact
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG
Titanium Nitride
Tungsten
Shallow Trench: 1st Interconnect Layer
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Polish Tungsten: CMP is used to remove the surface tungsten. The remaining tungsten forms “plugs”. The surface titanium nitride is also removed
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Shallow Trench: 1st Interconnect Layer
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Trench Oxide Polysilicon
Cross Section
N- WellP- Well
N+ Source/DrainP+ Source/Drain
SpacerContact
Shallow Trench: 1st Interconnect LayerTungsten Contact Plugs - Layout View: (top contact to polysilicon not shown in cross section)
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Deposit Metal1 Layer: Each interconnect layer is actually a sandwich of different layers. A sample is shown below. The films are deposited by sputtering
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSGW Contact Plug
Metal1
Ti (200Å) - electromigration shuntTiN (500Å) - diffusion barrier
Al-Cu (5000Å) - main conductor
TiN (500Å) - antireflective coating
Shallow Trench: Metal1 Layer
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Pattern Photoresist for Metal1 Interconnects:
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Photoresist
Shallow Trench: Metal1 Layer
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Etch Metal1: An RIE etch utilizing chlorine chemistry. Multiple etch steps are required due to the multiple different metal layers
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Photoresist
Shallow Trench: Metal1 Layer
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Strip Photoresist: First interconnect layer is completed
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Shallow Trench: Metal1 Layer
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Trench Oxide Polysilicon
Cross Section
N- WellP- Well
N+ Source/DrainP+ Source/Drain
SpacerContactMetal1
Shallow Trench: Metal1 Layer
Completed 1st Interconnect Layer - Layout View: (metal lines shown in outline-only for clarity)
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Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1
Shallow Trench: 2nd Through Nth (8)
Deposit IMD1: Undoped silicon dioxide is deposited using successive CVD depositions and etches to achieve filling between metal lines. Approximate thickness is 1 micron. This layer will electrically insulate the metal layers from one another
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Polish IMD1: Use Chemical Mechanical Polishing to achieve a flat surface on the IMD layer. If not removed, the bumps on the surface from the underlying topography would cause focus problems for the subsequent photolithography steps and degrade metal step coverage
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1
Shallow Trench: 2nd Through Nth (8)
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Pattern Photoresist to Define Vias: Vias are contact openings in the IMD layers enabling electrical access between metal layers
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1
Photoresist
Shallow Trench: 2nd Through Nth (8)
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Via Etch: A carefully designed RIE etch using fluorine chemistry to achieve vertical sidewalls
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Photoresist
IMD1
Shallow Trench: 2nd Through Nth (8)
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Strip Photoresist:
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1
Shallow Trench: 2nd Through Nth (8)
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Tungsten
Deposit Titanium Nitride and Tungsten: Same as for the first interconnect layer
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
Shallow Trench: 2nd Through Nth (8)
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Polish Tungsten and Ti Nitride: Completing tungsten vias
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
Shallow Trench: 2nd Through Nth (8)
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Trench Oxide Polysilicon
Cross Section
N- WellP- Well
N+ Source/DrainP+ Source/Drain
SpacerContactMetal1
Via1
Shallow Trench: 2nd Through Nth (8)
Tungsten Vias - Layout View:
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Deposit Metal2: Subsequent metal stacks will be similar to Metal1, but tend to increase in thickness and width as their runs are longer and they carry more current
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
Metal2
Shallow Trench: Metal2 Interconnect
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Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Photoresist
IMD1 W Via Plug
Metal2
Shallow Trench: Metal2 InterconnectPattern Photoresist for Metal2 Interconnects: Adjacent metal layers are patterned perpendicular to each other to minimize inductive coupling between layers
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Etch Metal2: An RIE etch utilizing chlorine chemistry. Multiple etch steps are required due to the multiple different metal layers
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
Photoresist
IMD1 W Via Plug
Metal2
Shallow Trench: Metal2 Interconnect
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Strip Photoresist: 2nd interconnect layer is completed
Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
Metal2
Shallow Trench: Metal2 Interconnect
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Trench Oxide Polysilicon
Cross Section
N- WellP- Well
N+ Source/DrainP+ Source/Drain
SpacerContactMetal1
Via1Metal2
Shallow Trench: Metal2 InterconnectCompleted 2nd Interconnect Layer - Layout View: (top right bond pad included in cross sectional diagrams)
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Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
PassivationMetal2
Shallow Trench: Passivation LayerDeposit Passivation Layer: There are many types of passivation (silicon nitride, silicon oxynitride, polyimide, and others). Its purpose is to protect the completed circuit from scratches, contamination, and moisture
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Silicon Substrate P+
Silicon Epi Layer P-P- WellN- Well
N+ Drain N+ SourceP+ Drain P+ Source
BPSG W Contact Plug
Metal1
IMD1 W Via Plug
Passivation
Bond Pad
Poly Gate
Gate Oxide
Silicide Spacer
Metal2
Shallow Trench: Passivation LayerPattern Passivation Layer: Polyimide passivation is photo-definable. Other passivation layers require a patterned photoresist layer followed by an etch step. Bond pad openings allow electrical access to the chip
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Cross Section
Final Composite Layout: Showing electrical connections and partial bond pads
Trench OxideN+ Source/DrainP+ Source/Drain
SpacerContactMetal1
Polysilicon Via1
+5V Supply
VOUT
N- WellP- Well
Metal2
Ground
Bond Pad
VIN
Shallow Trench: Passivation Layer
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Now Let’s Review!!
Shallow Trench
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MASK Generation Example CMOS Inverter
MASK
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Mask Design using Layout Editor user specifies layout objects on different layers output: layout file
Pattern Generator Reads layout file Generates enlarged master image of each mask layer Image printed on glass reticle
Step & repeat camera Reduces & copies reticle image onto mask One copy for each die on wafer Note importance of mask alignment
MASK Generation
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Example: CMOS Inverter
VDD
Vout
CL
Vin
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cut line
p well
Simplified CMOS Inverter Process
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P-Well Mask
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Active Mask
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Poly Mask
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P+ Select Mask
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N+ Select Mask
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Contact Mask
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Metal Mask
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Dual-Well CMOS + NPN Process Twin-Well Process + High energy Implantation Advanced Smart Power
Only one is described here
BiCMOS Processes
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BiCMOS Process
N+ buried P+ well Nepi (Collector + Ch. Of PMOS) FOX Planarization Base (Source/Drain)
Emitter (Source/Drain) Gate Oxide Metal1 Deposition SiO2 Metal2 Deposition SiO2 Metal3
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BiCMOS With Double-Level Metal Interc.
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Why? Simple SOI CMOS Process SOI Wafer Fabrication (Basic Steps) SOI Transistors Disturbance Is SOI just in the textbooks? Novel SOI Devices
Silicon On Insulator (SOI)
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Silicon on Insulator (SOI) is a new technology that has a number of advantages over ordinary silicon technologies including: SOI Devices are 25%-30% faster Replacement for SOS Need to extend Moore’s Law Commercial Availability of SOI wafers SOI Devices have less leakage current through the substrate
due to the buried insulator layer SOI Devices have reduced parasitic capacitance Improve Latch-up Susceptibility (Suitable for Sub-Micron) Higher Integration Density (Denser Layout = Low Cost)
Why SOI?
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Simple SOI CMOS Process
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SOI Wafer Fabrication
Bond and Etch Back SIMOX (Separation by IMplantation Of oXygen) SIMON (Separation by IMplantation Of Nitrogen)
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heat
silicon
BOX
SIMOX SIMOX
SIMOX
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S il ic o n
S i l i c o n D io x id e 4 0 0 0 Å
S i l i c o n 9 0 0 Å
Source D rainSubstrate (G ate)
1. Bare silicon wafer (for our case p-type).2. High energy implant of oxygen atoms.3. Source and Drain Boron implant.4. Source, Drain, and Substrate contacts.5. Addition of the molecular layer.
SOI Wafer Fabrication (Basic Steps)
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Bulk
DrainSource
Gate
MOS/BULK
Gate
Drain
Source
Bulk
DTMOS (Dynamic Threshold MOS) Body Tied to Source
Gate
Drain
Source
BulkBody
Gate
Drain
Source
BulkBody
Bulk
DrainSourceGate
Buried oxide
MOS/SOI (SOI: Silicon On Insulator)
Body
Less junction capacitance
Good isolation between devices
The variation of the body voltage impacts the threshold voltage.
SOI Transistors Disturbance
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AMD 90nm processorEnd 2004
Apple’s Xserve G5March 2004
TI’s commercial 64k SRAM1989
HP’s 2GHz CMOS circuit1988
IBIS’s commercial SIMOX wafers (3’’ – 6’’)1987
Is SOI just in the textbooks?
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Dual gate SOI SOI Single electron transistors
Novel SOI Devices