digital double column & end of column status, verification, and simulation results
DESCRIPTION
Digital Double Column & End of Column status, verification, and simulation results . Tomasz Hemperek. Pixel Digital Region - Functionalities. Pixel Digital Region - Layout. 190 m. 100 m. Region Parameters (4 pixels). Area 102x100 um (ARM Cells) Buffer Overflow Inefficiency - PowerPoint PPT PresentationTRANSCRIPT
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Digital Double Column & End of Column
status, verification, and simulation results Tomasz Hemperek
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Pixel Digital Region - Functionalities
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190m
100m
Pixel Digital Region - Layout
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Area 102x100 um (ARM Cells)
Buffer Overflow Inefficiency about 0. 05 % for 3xLHC about 2.20% for 10xLHC
Power consumption (average) with parasitics (ETS) ~12 uW/region (~3uW/pixel)- 1hit/BC/DC, 100kHz
trigger
Region Parameters (4 pixels)
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Array Organization
TokenBus
control
Two token scenario (column and periphery level)
One data bus (token type) End of column logic
selects column to read Chip control logic controls
trigger and read Pixels are always read in
the same order
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Digital Double Column
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Signal Distribution
Clock Distribution
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Digital Double Column – yield
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Possibility to turn off digital region (in and out) Triplicated Token with majority voting in every
region Hamming protection code on data bus Hamming protected row address with thermal
decoder
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Digital Double Column - layout
BUFFERS
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Digital Double Column – average power
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Parasitic extraction with QRC Results for Double-Column (2x336 pixels) Activity : 1hit/25ns/DC, 100kHz trigger Tools: PrimeTime
Parameters Double Column [mW] Pixel [uW]
1.2 [V], 25 C, TT 4.437 6.61.32 [V], 0 C, FF 5.217 7.61.08 [V], 70 C, SS 3.680 5.5
clock network (TT): 3.721 mW
2 hits/25ns/DC (TT): 5.290 mW
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Digital Double Column – analog simulation 4 region (16 pixels) post-layout simulation
(QRC+HSIM)
10no decupling
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End of Column Logic
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Column token management
Controls the read of column
Distribute signals to DDC Triple redundant logic Hamming protected data Stop clock enable Logic
Layout ready and simulated
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Summary
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All blocks ready and verified (post layout)
Need integration with other analog and digital blocks
Need some mixed-signal verification
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BACKUP SLIDES
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Hit processing (HC3 mode)- schematic
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Receives comparator output
BC resolution Generates Leading
Edge (LE) Generates Small hit
Leading Edge (sLE) Generates Trailing
Edge (TE) Generates ToT counter
reset and enable (rst_cnt, en_cnt)
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ToT processing - schematic
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Start ToT Counter Global LE
generation (orLE) Reset memory
signal generation (rst_mem)
Memory pointer selection (freeAddr)
Record reset/small in memory
Record neighbor Record TOT value in
memory
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Memory Management - schematic
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Selects free memory
Token management Selects triggered
memory during read
Enables outputs
Design: x5 latency cell
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Latency Memory/Trigger- schematic
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Start/Reset latency counter Indicate status (full) Trigger (triggered) Store/Recognize trigger ID
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Buffer overflow inefficiency Physical data from Genova
Buffer overflow inefficiency in [%]
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MemoriesSimulation Analytical
3xLHC 10xLHC 3xLHC 10xLHC
5 0.047 2.19 0.029 2.25
6 0.011 0.65 0.003 0.57
7 <0.01 0.16 <0.01 0.13
3xLHC 10xLHC4pixel / BC hit probability 0.00441 0.01290
Mean pixels hit / 4pixel region 1.41 1.42