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Digital Circuits II

VHDL for Digital System Design

Chapter 12 Counter Circuits and VHDL for State Machines

Part 1 of 2

References:

1) Text Book: Digital Electronics, 9th edition, by William Kleitz, published by

Pearson

Spring 2015

Paul I-Hai Lin, Professor of ECET

Dept. of Computer, Electrical and Information Technology

Indiana University-Purdue University Fort Wayne

Prof. Paul Lin

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Topics of Discussion

Analysis of Sequential Circuit

Ripple Counters: JF FFs and VHDL Code

Divide by N Counter

System Design Applications

7-Segment LED Display Decoder: the 7447 and VHDL Code

Synchronous Counter

Up/Down Counters

VHDL and LPM Counters

State Machine Implementation Using VHDL

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Introduction

Sequential Logic Circuits vs. Combinational Logic

Circuits

Sequential Logic Circuits

• A mix of combinational logic gates and flip-flops

• Used to count events and time the duration of processes

• Sequential since they follow a predetermined sequence and

are triggered by a timing pulse or clock

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Introduction

Sequential Circuits/Logic,

http://en.wikipedia.org/wiki/Sequential_logic

• A type of logic circuit whose output depends not only on the

present value of its input signal, but also on the sequence of past

inputs

• Two Main Types:

Synchronous Sequential Circuits (synchronized by a clock

signal)

Asynchronous Sequential Circuits (not synchronized by a

clock signal)

Other References:

• Chapter 3., Sequential Circuits,

http://www.ee.surrey.ac.uk/Projects/Labview/Sequential/Course/03-

Seq_Intro/Intro.html

• Sequential Logic,

http://courses.cs.washington.edu/courses/cse370/03au/lectures/06-Seq.pdf

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State Machine

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Characteristic Equations

Characteristics Equation: The Boolean equation for a latch

circuit is called its Characteristic equation

S-R Latch with NOR gates

Function Table

S R Q

----------------

0 0 Hold

0 1 0

1 0 1

1 1 (not used, not allow)

Q’ = (S+Q)’

Q+ = ((S+Q)’ + R)’ = ((S +Q)’)’ ∙R’ = (S+Q)∙R’ = S∙R’ + Q∙R’

Q : present state output; Q+ : next state output

Both Q and Q+ represent a variable for the same output.

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NOR2

inst

NOR2

inst1

VCCS INPUT

VCCR INPUT dT

Q+

Q

Q

(S+Q)'

(S+Q)'

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State Diagrams for the R-S Latch

S∙R’

Q=0 Q=1S’R’+S’R

R

S’R’+SR’

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Q=0 Q=1

Hold 0S R0 00 1

SetS R1 0

ResetS R0 1

Hold 1S R0 01 0

MOD 8 Binary Counter

Figure 12-1 MOD 8 Binary Counter (asynchronous)

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Figure 12-2 Waveforms for MOD 8 Binary Counter

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Analysis of Sequential Circuits

Example 12-1: Input and output waveforms from the edge-

triggered D flip-flop based circuit.

Figure 12-3: D = A∙ Q’; X = A∙Q

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Analysis of Sequential Circuits

Example 12-2: Input and output waveforms from the edge-

triggered D flip-flop based circuit.

Figure 12-3: D = A∙ Q’; X = A∙Q

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Analysis of Sequential Circuits

Example 12-3: This circuits uses negative edge-triggered JK

flip-flops; Figure 12-6: J1 = A∙ Q1; K1 = A∙Q0; Figure 12-7

Input and Output Waveforms

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Analysis of Sequential Circuits

Example 12-4: This circuits uses negative edge-triggered JK

flip-flops; Figure 12-6: J1 = A∙ Q1; K1 = A∙Q0; Figure 12-8

Input and Output Waveforms

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Ripple Counters

Flip-flops can be used to form binary counters

Cascade – Q output of one to clock input of the next

Three flip-flops for a 3-bit, MOD 8 counter

• 23 = 8 different combinations

• Binary 000 through 111

• Figure 12-10 (b) State Diagram

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Ripple Counters

Three J-K Flip-flops used toggle mode to form a MOD-8 (3-bit)

ripple counter

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Ripple Counters

Maximum frequency is approximately equal to the

reciprocal of the combined propagation delays

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) to( flop-flipeach ofdelay n propagatio average

flops-flip ofnumber

1max

QCt

N

tNf

pp

p

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Ripple Counters

16-bit counter and waveforms

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Ripple Counters

MOD-8 Down counter: Outputs from Q’

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VHDL Description of Mod-16 Up counter

Figure 12-16 VHDL Code Listing

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Design of Design by N Counter

Reduce the frequency of periodic waveforms

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Design of Design by N Counter

Devide-by-5 (MOD 5) Counter

Reset all FFs to zero: Q2 = Q1 = Q0 = 0, when 510

(1012) is reached.

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Design of Design by N Counter

Devide-by-5 (MOD 5) Counter

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Design of Design by N Counter

MOD 6 Counter with a manual reset

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Design of Design by N Counter

MOD 6 Counter with a manual reset

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Ripple Counter- 7493 Binary Ripple Counter

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Ripple Counter- 7493 Binary Ripple Counter

7493 connected as a MOD-16 ripple counter

Divide by 10, Divide by 2 and Divide by 5

Divide by 12, Divide by 2 and Divide by 6

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7490 Decade Counter

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Example 12-11 VHDL Description of Mod-10 Up counter

Figure 12-27 VHDL Code Listing

-- Mod-10 Glitch-Free Up-Counter --

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY ex12_12 IS

PORT(n_cp, n_rd :

IN std_logic;

q :

BUFFER integer RANGE 0 TO 15);

END ex12_12;

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ARCHITECTURE arc OF ex12_12 IS

BEGIN

PROCESS (n_cp, n_rd)

BEGIN

IF (n_rd='0‘ OR q=10) THEN

q <= 0;

ELSIF (n_cp'EVENT AND

n_cp='0' ) THEN

q <=q+1;

END IF;

END PROCESS;

END arc;

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Example 12-11 VHDL Description of Mod-10 Up counter

Assignments > Settings > Simulation Settings > Simulation

Mode: Timing

Tools > Options > Waveform Editor > View > Group & Bus Bits

> MSB first , or LSB first

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Example 12-11 VHDL Description of Mod-10 Up counter

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Example 12-12 VHDL Description of Glitch-Free Mod-10

Up counter

Figure 12-29 VHDL Code Listing

-- Mod-10 Glitch-Free Up-Counter --

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY ex12_12 IS

PORT(n_cp, n_rd :

IN std_logic;

q :

BUFFER integer RANGE 0 TO 15);

END ex12_12;

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ARCHITECTURE arc OF ex12_12 IS

BEGIN

PROCESS (n_cp, n_rd)

BEGIN

IF (n_rd='0') THEN

q<= 0;

ELSIF (n_cp'EVENT AND

n_cp='0' ) THEN

IF (q=9) THEN

q<=0;

-- Reset at the end of #9 period

ELSE q<=q+1;

END IF;

END IF;

END PROCESS;

END arc;

Example 12-12 VHDL Description of Glitch-free Mod-10

Up counter

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Summary & Conclusion

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