digital baseband architecture in ar1243/ar1642 automotive

Application Report Lit. Number – June 2015

1

Digital Baseband Architecture in AR1243/AR1642 Automotive Radar Devices

Sriram Murali, Karthik Ramasubramanian Wireless Connectivity Solutions

ABSTRACT

This application note describes the digital baseband architecture present in the TI AR1243/AR1642 automotive radar devices. The purpose of this application note is to enable the customer to understand the details behind the baseband processing steps performed in the device and the various configuration options that are available. Specifically, this application note focuses on the digital baseband block diagram, starting from the raw sigma-delta ADC output, till the final output samples that are sent to the DSP for radar signal processing.

Document History

Version Date Author(s) Notes

0.1 29 June 2015 Sriram Murali, Karthik Ramasubramanian

First draft

0.5 6 July 2015 Sriram Murali, Karthik Ramasubramanian

Fixed some typos. Added more details.

0.6 18 Aug 2015 Sriram Murali, Karthik Ramasubramanian

Updated with improved settling times

Lit. Number

2 TI Confidential – NDA Restrictions

1 Introduction

The AR1243 and AR1642 products are highly-integrated 77GHz CMOS automotive radar devices. The devices integrate all of the RF and Analog functionality, including VCO, PLL, PA, LNA, Mixer and ADC for multiple TX/RX channels into a single chip. The AR1243 is an RF transceiver device and it includes 4 receiver channels and 3 transmit channels in a single chip. The AR1243 also supports multi-chip cascading. The AR1642 is a radar-on-a-chip device, which includes 4 receive channels and 2 transmit channels and additionally an integrated DSP for radar signal processing.

Both devices include a built-in BIST (Built-in Self-Test) processor, which is responsible to configure the RF/Analog and digital front-end in real-time, as well as to periodically schedule calibration and functional safety monitoring. This enables the mm-Wave front-end to be self-contained and capable of adapting itself to handle temperature and ageing effects, and to enable significant ease-of-use from an external host perspective.

This application note describes the digital baseband architecture present in these devices. The purpose is to provide information to the customer regarding the processing steps performed in the device and the configuration options available, starting from the sigma-delta ADC, till the final output samples that are sent to DSP for further radar signal processing.

2 Receive Complex Baseband Architecture

Figure 1 below shows the high-level block diagram of a single radar receiver channel. Unlike conventional real-only radar receivers, the AR1243/AR1642 devices support a complex baseband architecture, which uses quadrature mixers and dual IF and ADC chains to provide complex I and Q outputs for each receiver channel.

Figure 1 - High-level block diagram of Receiver

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TI Confidential – NDA Restrictions 3

A description of the complex baseband architecture and its potential advantages is covered in a separate application note [1]. Here, a brief explanation of complex baseband output in FMCW radar is provided, to serve as a background for the digital front-end description given in the next section.

It is well-known that in FMCW radar, the received signal comprises of different delayed and attenuated versions of the transmit (LO) signal, corresponding to reflections from objects at various distances. The beat frequency (intermediate frequency) signal corresponding to the different objects occupy one side of the complex baseband spectrum. This is easily seen from Figure 2, where objects at different distances appear as tones in the beat frequency spectrum, from DC till a certain maximum beat frequency (say, fb,max) corresponding to the farthest object of interest.

Figure 2 - Received FMCW radar signal and Beat frequency spectrum

In conventional real-only radar receivers, the real ADC output has a spectrum as shown in the left side of Figure 3. The spectrum of the real output is symmetric around DC and has higher noise floor due to image band noise folding back inband. The samples sent to the DSP are real samples at 2fb,max samples/second (assuming Nyquist rate sampling for now).

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The right side of the figure shows the spectrum in the case of complex baseband output. The spectrum is one-sided and is devoid of image band noise fold-back. This results in a noise figure benefit for the case of complex baseband output. In the case of complex baseband, it is possible to filter out the image band noise and reduce the sampling rate by a factor of 2. For convenience of the image reject filtering, the spectrum is centered around DC using digital down-conversion, filtered, decimated, and then the resulting complex output is sent to the DSP at the rate fb,max.

Thus, the signal of interest is preserved in both cases – namely, the real output (at 2fb,max samples/sec), as well as in the complex output (at fb,max samples/sec). The difference, however, is that the complex baseband output enjoys an improved noise figure.

Figure 3 - Beat frequency spectrum for real and complex baseband output

In practice, the sampling rate required needs to be higher than the Nyquist rate to allow some room for filtering. For this purpose, in our design, the sampling rate fs in the complex baseband case is set to be fs = fb,max/0.9. Also, it is important to note that the frequency shift to center the spectrum around DC causes a change in the mapping of the FFT bin to the range measurement – i.e., FFT bin 0 will no longer correspond to a range of 0m. This can be addressed by appropriately adjusting the mapping between the FFT bin to range measurement in the DSP processing. Alternately, it is possible to perform another frequency shifting operation to shift the frequency back to the original frequencies (i.e., de-center the spectrum) such that FFT bin to range measurement mapping does not change w.r.t conventional FMCW radar processing.



These aspects are covered in more detail as part of the detailed digital front-end block diagram in the following section.

3 Digital Baseband Processing

3.1 Block diagram

A representative block diagram of the digital front-end (DFE) is shown in Figure 4. The base-band can be operated either as a real chain (with the Q arm disabled) or as a complex base-band signal chain. The processing steps are as follows.

3.1.1 Decimation chain and re-sampler

The ADC is a 3rd order sigma-delta ADC that is clocked at 1.8 GHz (an optional 900 MHz half-rate mode is available as well). The sigma-delta ADC output is processed by a chain of decimation stages as shown in the block diagram. The decimation chain starts with a 3rd order CIC decimation-by-9, which produces 1.8GHz/9 = 200MHz output sampling rate. This is further decimated by 2 using an FIR filter (denoted A1) that produces 100MHz output sampling rate. At the output of this filter, there is provision for digital DC subtraction and IQ imbalance correction.

AAF

A6A5A4A3A2

1.8 GHzLR mode: 0.9 GHz

1 bitSD-ADC3rd order

From

RF/Analog CIC

92

A1

2

FIR IQ imbalance

correction

Digital DC

correction register

FIR

2 2

FIR

2

FIRFIR

22

FIR Variable Rate

Resampler

(Ratio 0.5~1)

100 MHzLR mode: 50 MHz

A7

2

FIR FIR Anti-

aliasing Filter (min phase) 2

Sample

drop

Output

formatting16 bits

12/14/16 bits

fs

fs

Freq shift(centering)

Freq shift(de-centering)

AAF

FIR Anti-


Sample

drop

Rx Statistics

Collection

(for AGC, etc.)

Rx Statistics

Collection

(for AGC, etc.)

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Figure 4 - Simplified block diagram of the Digital Front-End (DFE)

From this point, there is a series of FIR decimate-by-2 stages (denoted A2-A6 in the figure), which are engaged or bypassed based on the desired output sampling rate. Specifically, the lower the final output sampling rate, the more the number of decimation stages engaged. This series of decimation stages is followed by a variable rate re-sampler, whose output sampling rate is programmable to be anywhere between 0.5~1x of its input sampling rate. This allows the final sampling rate to the DSP to be fully configurable by the customer, based on the chirp configuration and use-case requirements. The re-sampler is followed by final anti-alias filtering and further decimation to produce the final output samples.

3.1.2 Operation modes and final anti-alias filtering

After the re-sampler, the final anti-alias filtering, decimation and output mode selection is performed, and three output modes are supported, as described below.

fs0-fs fs/20-fs/20 fs/2-fs/2

Complex 1X Complex 2X Real

InbandAlias InbandImage

Band

InbandInband

(mirror)

Figure 5 – DFE Output spectra for the three output configurations

3.1.2.1 Default Configuration: Complex 1X Output

For complex baseband operation, in order to produce the optimal output sampling rate (i.e., output sampling rate fs = fb,max/0.9), the re-sampler is followed by a frequency shifter which centers the spectrum around DC and a decimate-by-2 stage (A7). Next, there is an anti-aliasing filter (AAF) that provides 60 dB of suppression for out-of-band signals. The output of this filter goes to another frequency shifter which de-centers the spectrum back to the original frequencies and subsequently the sample rate is dropped by 2.

At this point, the sampling rate corresponds to the final desired output sampling rate for further DSP processing. The entire decimation chain is designed such that 90% of the final output sampling rate is preserved as the passband of interest. The typical output spectrum in this mode is shown on the left side of Figure 5. A more detailed description of the filter’s passband and stopband characteristics is presented in section 4.

This default configuration achieves the best noise figure and the lowest (optimal) sampling rate.



3.1.2.2 Alternate Configuration: Complex 2X Output

For complex baseband operation, it is possible to bypass the frequency centering, decimation and de-centering path altogether and simply produce complex baseband outputs at 2X the optimal rate (i.e., fs = 2fb,max/0.9). This results in both the in-band and the image band being visible at the final output, and since the image band is kept as alias-free as the in-band, image band monitoring can be used for purposes such as interference detection, etc. The in-band noise figure in this mode is identical to the default Complex 1X configuration.

The typical output spectrum in this mode is shown in the middle section of Figure 5. Again, a more detailed description of the filter’s passband and stopband characteristics is presented in section 4.

3.1.2.3 Alternate Configuration: Real-only Output

In this configuration, the receiver is operated in real-only mode. Thus, the Q-channel IF, ADC and decimation chain are unused, and hence the noise figure is poorer compared to the complex baseband configurations. In this case, similar to Complex 2X configuration, it is possible to bypass the frequency centering, decimation and frequency-decentering path altogether, to produce real-only output at the optimal (for real) output sampling rate of fs = 2fb,max/0.9. The typical output spectrum in this mode is shown on the right hand section of Figure 5. A more detailed description of the filter’s passband and stopband characteristics is presented in Section 4.

To summarize again, the digital front-end supports three output modes:

The default mode being complex baseband output at fs = fb,max/0.9, which achieves the best noise figure and lowest (optimal) output sampling rate

An alternate mode being complex baseband output at 2X the optimal rate (i.e., fs = 2fb,max/0.9), which can be used if both inband and image band visibility is desired at the final output

Another alternate mode being real output at fs = 2fb,max/0.9, which can be used if real-only analog chain is desired, for low power operation at a noise figure penalty.

These modes are explained in more detail for a specific output sampling rate configuration in section 3.2.

3.1.3 Frequency centering and de-centering

The frequency centering and de-centering blocks are used primarily in the Complex 1X configuration, as described in section 3.1.2.1. The purpose is to digitally down-convert the in-band spectrum to be centered around DC, for ease of image-reject and anti-alias filtering using a real low pass filter. After low-pass filtering, the signal is digitally up-converted back to the original frequency, so that the mapping between the beat frequency and the range measurement remains unchanged.

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The frequency centering block can also be used to compensate for any inter-RX phase mismatch across the four RX channels, by applying different digital phase shifts for the different RX channels. Note that the AR1243/AR1642 devices include built-in RF loopback capability to measure inter-RX phase mismatches. The BIST processor periodically invokes the RF loopback capability to measure inter-RX phase mismatch and then programs the frequency centering block with appropriate starting phase values for the different RX chains, such that the measured inter-RX phase mismatch is compensated. Thus, across temperature and ageing, the final samples output to the DSP are kept well-matched across the four receive chains.

3.1.4 Output data formatting

The output samples produced by the digital front-end chain are 16-bits wide and can be sent to the built-in DSP (AR1642) or to an external DSP (via LVDS/CSI interface in AR1243) as 12-bit, 14-bit or 16-bit wide samples. The selection of bits and left/right justification are kept completely programmable.

3.1.5 DC offset correction

The DFE includes a DC offset correction block, as shown in Figure 4, which is independently controllable for each receiver chain. This post-ADC DC correction is primarily intended to handle any residual DC offsets introduced in the post-HPF IF stages including the ADC. The DC correction value is automatically calibrated and compensated for by the dedicated built-in BIST processor. However, if required, provision can be made for the DC correction value to be controlled by the DSP. Details about the BIST processor subsystem and the control/configuration interface to the radar chip appear in a separate application note.

3.1.6 RX statistics collection

The DFE allows monitoring of some key signal statistics, such as the average energy on the I and the Q arms, the average level of cross-correlation between the I and the Q arms and the (residual) DC level on the I and the Q arms at one of two tap-off points in the signal chain, as shown in Figure 4.

The tap-off point can either be at the 100 MHz sampling rate point in the chain (50 MHz for half-rate ADC mode), to provide visibility to out-of-band energy in addition to in-band energy, or at the final output rate of the decimation filter chain, in order to monitor just the in-band (and, in the Complex 2X configuration, the image band) signal statistics.

These statistics collection blocks can be configured to monitor a programmable window of data samples for each chirp in a frame, and can report the average statistics across chirps for each frame.

The reports from either of the monitors can be used by the DSP for Automatic Gain Control (AGC) across frames. Alternately, the BIST subsystem can be configured to automatically perform this gain control operation for a desired target back-off at the ADC.



3.1.7 IQ imbalance correction

In a complex baseband receiver chain, a gain imbalance between the I and the Q arms of the mixer or IF chain, or any deviation from phase quadrature (also known as phase imbalance) between the I and Q arm mixers, can result in an “image fold-back” phenomenon. This image fold-back phenomenon causes a “mix-up” of positive and negative frequency components in the complex base-band spectrum, as shown in Figure 6.

0

Ideal IQ Baseband

InbandUnwanted image band artefacts

(noise, intermod, crossing

interference, etc.)

0

Non-ideal IQ Baseband

Images of

unwanted artefacts

IMRR

Inband

Figure 6 - IQ imbalance causing image fold-back

A real-only chain can be looked at as an extreme version of this negative-positive frequency mix-up, because of the absence of any phase quadrature (the Q-chain being absent), resulting in the positive and negative frequencies being identical in the base-band signal spectrum.

In general, the level of this mix-up can be quantified in terms of the Image Rejection Ratio (IMRR), a quantity in dB that specifies the level of attenuation seen by negative frequencies before they show up as images on the positive frequencies, and vice-versa, as annotated in Figure 6. Thus, in terms of IMRR, a real-only chain has 0 dB IMRR, whereas an ideal complex chain results in infinite IMRR (no mix-up of positive and negative frequencies).

A typical raw analog gain imbalance of 2 dB and phase imbalance of 5 degrees can result in a poor IMRR of only 18 dB. This means that any unwanted image-band artefacts, such as image-band noise or intermodulation products, that would normally show up only on the negative frequency side (and thus would not impact in-band performance, assuming the desired IF signal occupies positive frequencies), will have images on the positive frequency side which are only 18 dB suppressed.

It is possible to estimate and correct for the raw analog gain/phase imbalance in the digital base-band. Such an IQ mismatch compensation mechanism is included in the DFE signal chain, as shown in Figure 4, for the complex baseband modes, and is designed to target a post-correction residual gain imbalance less than 0.1 dB and residual phase imbalance of under 0.5 degrees, which effectively achieves a residual IMRR that is in the range of 35 to 40 dB.

3.2 Example – 4.5 MHz max beat frequency

3.2.1 Default configuration: 5 Msps complex baseband output (Complex 1X)

Let us consider an illustrative example, such as 5Msps complex baseband output, to understand how the decimation chain would be configured for such a case. This example might be relevant to an SRR use-case with a sample chirp configuration as shown in the table below.

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Example chirp configuration used for illustration

Sweep bandwidth 900 MHz

Valid chirp duration 50 us

Ramp slope 18 MHz/us

Max range 37.5 m

Max beat frequency 4.5 MHz

Table 1 - Example chirp configuration

The maximum beat frequency of interest is 4.5 MHz. This means that the output sampling rate for this example should be at least 5 Msps complex (90% of 5Msps being 4.5MHz). To achieve the 5 Msps complex baseband output sampling rate, the decimation chain would be configured as follows.

Decimation stages A2, A3 and A4 bypassed

Decimation stages A5 and A6 engaged Sampling rate at A6 output is 25 MHz

Variable Rate Resampler configured for output to input sampling rate ratio of 4/5 Sampling rate at resampler output is 20 MHz

Frequency centering, decimation and de-centering path is engaged Final output is 5 MHz complex



AAF

A6A5A4A3A2



From

RF/Analog CIC

92

A1

2

FIR IQ imbalance

correction

Digital DC

correction register

FIR

2 2

FIR

2

FIRFIR

22

FIR Variable Rate

Resampler

(Ratio 0.5~1)


A7

2

FIR FIR Anti-


Sample

drop

Output

formatting16 bits

12/14/16 bits



AAF

FIR Anti-


Sample

drop

Rx Statistics

Collection #2

(for AGC)

Rx Statistics

Collection #1

(for AGC)

25 MHz 20 MHz

5 MHz

(complex)

Figure 7. Block diagram of the Digital Front-End showing 5 MHz complex output example

3.2.2 Alternate configuration (Complex 2X): 10 Msps complex output

In this configuration, the receiver is used in complex baseband mode, however, the frequency centering, decimation and de-centering path is not engaged. The output will be complex samples at 10Msps and will include both inband and image-band visibility.

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AAF

A6A5A4A3A2



From

RF/Analog CIC

92

A1

2

FIR IQ imbalance

correction

Digital DC

correction register

FIR

2 2

FIR

2

FIRFIR

22

FIR Variable Rate

Resampler

(Ratio 0.5~1)


A7

2

FIR FIR Anti-


Sample

drop

Output

formatting16 bits

12/14/16 bits



AAF

FIR Anti-


Sample

drop

Rx Statistics

Collection #2

(for AGC)

Rx Statistics

Collection #1

(for AGC)

25 MHz 20 MHz

10 MHz

(complex)

Figure 8. Block diagram of the Digital Front-End showing 10 MHz complex output example

3.2.3 Alternate configuration (Real-only): 10 Msps real output

In this configuration, the receiver is operated in real-only mode. Thus, the Q-channel IF, ADC and decimation chain are unused and hence the noise figure is degraded. In this case, the output will be real samples at 10 Msps rate. The block diagram is identical to the one shown in Figure 8, except that only the real-arm of the receiver is used. There is no image band visibility in this case and the spectrum will simply be symmetric around DC.

4 Filter Response

The filtering provided by the analog IF and digital decimation stages consists of two parts.

The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set of available HPF corners is summarized in Table 2.



Available HPF Corner Frequencies (kHz)

HPF1 HPF2

175, 235, 350, 700 350, 700, 1400, 2800

Table 2 - HPF Corner Frequency Options

The filtering performed by the baseband chain is targeted to provide:

(a) Under +/- 0.5 dB pass-band ripple/droop, and

(b) Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.

As an illustration, we present the effective response for the 4.5 MHz max beat frequency use-case described in the earlier section, for the three configurations described therein.

4.1 Default configuration (Complex 1X Rate)

In this configuration, the output sampling rate is the optimum, with 90% bandwidth utilization (4.5 out of 5 MHz). The effective HPF + digital low pass filtering response is shown below. The passband in this example is 0 to 4.5 MHz, and the aliasing bands lie outside -0.5 MHz and +5.0 MHz.

As can be seen in Figure 9 and Figure 10, the pass-band ripple/droop is under +/- 0.5 dB, while the anti-aliasing attenuation is greater than 60 dB, starting at 5 MHz. In Figure 9, the green patch represents the frequencies visible at the final output rate.

Figure 9 – Anti-aliasing Attenuation - 5 Msps (Complex 1X Rate) Configuration

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Figure 10 – In-band Response - 5 Msps (Complex 1X Rate) Configuration

Also shown in Figure 11 is the one-sided filtering response referred to the ADC rate, on a logarithmic frequency scale. This picture more clearly presents the net high-pass filter response. In this example, the HPF corners are configured to be 235 kHz and 350 kHz.

Figure 11 – Net Filtering - 5 Msps (Complex 1X Rate) Configuration



4.2 Alternate configurations (Complex 2X Rate and Real-only modes)

In both these alternate configurations, the output rate of the chain is 10 Msps. In the real mode, this is the minimum possible rate (at 90% BW utilization). In the complex output configuration, this is 2X the minimum possible rate, but also provides visibility of the image band frequencies.

Since the overall filtering response of the chain for both these scenarios is identical, they are presented together here. The passband in this example is 0 to 4.5 MHz, and the aliasing bands lie outside +/-5.5 MHz

As can be seen in Figure 12 and Figure 13, the pass-band ripple/droop is under +/- 0.5 dB, while the anti-aliasing attenuation is > 60 dB, starting at 5.5 MHz.

Figure 12 – Anti-aliasing Attenuation - 10 Msps Configurations (Complex 2X Rate or Real-only)

Figure 13 – In-band Response - 10 Msps Configurations (Complex 2X Rate or Real-only)

The HPF response on a logarithmic frequency scale remains identical to what is shown in Figure 11, when the corner frequencies are chosen as before (235 kHz and 350 kHz).

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5 Settling Time

The settling time of the filtering stages is presented as two aspects: the step response time of the analog HPF stages, which is a function of the HPF corner frequencies and independent of the output sampling rate, and the step response settling time of the digital filter chain, which scales roughly inversely as the output sampling rate.

5.1 HPF settling

The HPF settling time is presented in terms of the 1% settling time for a DC step input. This scales inversely as the HPF corner frequency (higher settling time for lower cut-offs). The representative 1% settling times for some HPF1 and HPF2 corners are tabulated in Table 3.

Step Response Settling - HPF

HPF1 Corner (kHz)

HPF2 Corner (kHz)

1% Settling Time (us)

175 350 4.1

235 350 3.5

350 350 2.8

700 700 1.4

Table 3 - HPF Step Response Times

5.2 Digital filter chain settling

The digital filter chain’s settling time is measured in terms of the step-response magnitude settling time for a step-input in-band tone. This settling time is, to a large extent, independent of the actual in-band tone frequency.

When the HPF is also included in this analysis, there is some dependence on the frequency of the in-band tone. However, beyond the 3-dB point of the HPF response, the sensitivity to the choice of tone frequency is not significant. The 95% and 99% settling times of the filter chain for our example output sampling rates are tabulated below. The numbers here correspond to a tone frequency of 500 kHz, which is approximately the 3dB point in the example configuration, as shown in Figure 11. Note: pipeline latencies (non-filter buffers) in the DFE are not accounted for in the settling time analysis here.

Step Response Settling Times

Output Rate (Msps)

Digital Filter Chain HPF + Digital Filter Chain





10 (Complex 2X or Real-only) 1.8 2.2 2.2 2.8

5 (Complex 1X) 3.5 4.1 3.6 4.2

Table 4 - Filter Chain Step Response Times



The settling time of the digital filter chain roughly scales inversely as the output sampling rate, and so, is also dependent on the digital chain configuration for a given desired bandwidth. Thus, as can be seen in Table 4, the Complex 2X digital chain configuration has a lower settling time compared to the Complex 1X configuration, for the 4.5 MHz max beat frequency use-case. The plots in Figure 14 and Figure 15 below show the time-domain magnitude settling behavior of the filtering stages for this use-case. As can be seen, the inclusion of the HPF in this analysis only impacts the settling time slightly.

Figure 14 – Filter Chain Settling Times - 5 Msps (Complex 1X Rate) Configuration

Figure 15 – Filter Chain Settling Times - 10 Msps Configurations (Complex 2X Rate or Real-only)

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6 Summary

This document covered the digital baseband processing present in the AR1243/AR1642 devices. A brief overview of complex baseband architecture was presented and the processing steps in the digital baseband, starting from the sigma-delta ADC till the final output was explained, along with various configuration modes available. The filter response and settling times were presented for a typical use-case as well.

7 References

1. Karthik Ramasubramanian, Complex Baseband Architecture for FMCW Radar Systems, Application Note

2. Donald E. Barrick, “FM/CW Radar Signals and Digital Processing”, NOAA Technical Report

ERL 283-WPL 26, July 1973

3. A. G. Stove, ‘‘Linear FMCW radar techniques’’, IEE Proceedings F, Radar and Signal

Processing, vol. 139, pp. 343--350, October 1992

digital baseband architecture in ar1243/ar1642 automotive

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