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Development of ATLAS Liquid Argon CalorimetersReadout Electronics for HL-LHC

Kai Chen, on behalf of the ATLAS Liquid Argon Calorimeter Group

Abstract—The high-luminosity phase of the Large HadronCollider (LHC) will provide 5-7 times greater instantaneous andtotal luminosities than assumed in the original design of theATLAS Liquid Argon (LAr) Calorimeters and their readoutsystem. The improved trigger system has a higher acceptancerate of 1 MHz and a longer latency of up to 60 micro-seconds.This requires an upgrade of the readout electronics, and abetter radiation tolerance is also required. This paper willpresent concepts for the future readout of the 182,468 calorimeterchannels at 40 or 80 MHz with a 16 bit dynamic range. Progressof the development of low-noise, low-power and high-bandwidthelectronic components will be presented. These include radiation-tolerant preamplifiers, analog-to-digital converters (ADC) up to14 bits and low-power optical links providing transfer rates ofat least 10 Gbps per fiber.

Index Terms—ATLAS, Liquid Argon Calorimeters, ReadoutElectronics.

I. INTRODUCTION

AS the LHC run plan shown in Figure 1, the LHC will beupgraded to HL-LHC (High Luminosity LHC) after Run

3. HL-LHC will have an instantaneous luminosity of 5-7×1034

cm−2s−1, with the ability to provide an integrated luminosityof 3-4.2 ab−1 after 12 years of running. The LAr calorimetersare used in the electromagnetic barrel, electromagnetic endcap,hadronic endcap and forward calorimeters of the ATLASdetector [1]. There is a total of 182,468 calorimeter cells [2].We will focus here on the upgrades that are planned for Phase-2, after the phase-1 upgrades will have be completed.

Fig. 1: Run plan of LHC and HL-LHC [3]

Figure 2 shows the readout architecture of Phase-I upgrade[5]. The signals with higher spatial granularity are digitizedand processed. After the third long shutdown, main readoutelectronics of the ATLAS LAr calorimeters will be upgradedfor Phase-II as shown in Figure 3. Readout of all calorimetercells will be sampled by the ADC with 14 bit resolution to

K. Chen is with the Physics Department, Brookhaven National Laboratory,Upton, NY, 11973 USA e-mail: kchen@bnl.gov

cover the 16 bit calorimeter signal, without trigger selection.To mitigate the pile-up effects in energy reconstruction, thesecond trigger level can get calibrated energies of all cells ata rate of 1 MHz. For the new architecture, the hardware basedfirst level trigger will be divided into two levels (Level-0 andLevel-1). The main function of Level-0 trigger is done byLAr Trigger Digitizer Board (LTDB), LAr Digital ProcessingSystem (LDPS), and the Feature Extractor (FEX) systemsinstalled in Phase-I upgrade. The Level-1 trigger will accessthe full granularity detector information to further enhancediscrimination against backgrounds [4].

SCA

MUX/SerializerOptical Links

Front-End Board

Preampl.

NewLayer Sum

Boards[LSB]

ADC

SCA

SCA

SCA

TimingTriggerControl

RCxSCA

Controller

Linear Mixer

Shaper

Baseplane

ROD

Optical ReceiverDeserializer Channel

De-multiplexerINPUT FPGA

Timing Trigger

Control Rx

PedSub

PedSub

PedSub

PedSub

E,t N-tap FIR

E,t N-tap FIR

E,t N-tap FIR

E,t N-tap FIR

DSP

DAQOutputFPGA

Controller Board Timing Trigger Control DistributionFixed Latency (~3.0us max)

80-100m fibers

TTC Partition Master

ADC

ADC

Optical Links

ADC

MUX/Serializer(FPGA)

ADC

LAr Digital Processing System (LDPS)

Optical ReceiverDeserializer

Timing Trigger

Control Rx

FPGA

SDRAM

Feature Extractor

[FEX]

PedSub

PedSub

PedSub

PedSub

E,t N-tap FIR

E,t N-tap FIR

E,t N-tap FIR

E,t N-tap FIR

S(t)

Receiver

480Gbps/module1.92 Tbps/board

~250 Gbps/board

Level-1 Calorimeter Trigger System

Current L1Calo

Processors

LAr Trigger Digitizer Board (LTDB)

Tower Builder Board [TBB]

iS(t- i)

Trigger Tower Sum and Drivers

PZ+Dly

Crate Monitoring

OTxCLK & Cfg.

CLK FanoutORx

Fig. 2: Schematic block diagram of the LAr Phase-I upgradetrigger readout architecture. The new components are indicatedby the red outlines and arrows. [5]

In the front-end, the legacy trigger electronics (mainly thetower builder board) will be decommissioned. The LTDBand LDPS installed in Phase-I upgrade will be kept for theLevel-0 trigger. Main readout electronics with new Front-End Boards (FEB2) will amplify and shape the calorimetercell signals, and digitize them with ADC running at 40MHz or 80 MHz sampling frequency. The digitized data willbe directly sent over high-speed optical links to the newback-end board LAr Pre-Processor Boards (LPPR). In totalthere will be 60-120 LPPRs in Advanced TelecommunicationsComputing Architecture (ATCA) crates. The LPPR will usethe Phase-I LAr Digital Processing Blades (LDPB) board asthe prototype. High performance signal filtering methods willbe implemented in the FPGAs [6]. The amplitude and timingof a signal pulse can be obtained.

ATLASPhase-II Upgrade

Scoping DocumentSeptember 25, 2015 - Version 1.0

Σ

Optical Links

Phase-II UpgradeFront-End Board

Preampl.

Layer SumBoards[LSB]

CLKFanout

Σ

Σ Linear Mixer

Shaper

Baseplane

Phase-II Upgrade Pre-Processor

FELIXOutputOTx

80-100m fibers

ADC

ADC

Optical Links

ADC

MUX/Serializer(FPGA)

ADC

Digital Processing System (DPS)

Optical ReceiverDeserializer

Timing Trigger Control

Rx

FPGA

L0 TriggerProcessor

PedSub

PedSub

PedSub

PedSub

E,t N-tap FIR

E,t N-tap FIR

E,t N-tap FIR

E,t N-tap FIR

Σ480Gbps/module1.92 Tbps/board

~250 Gbps/board

L1 Trigger ProcessorLAr Trigger Digitizer Board (LTDB)

Crate Monitoring

Σ

ADC & Gain Selec.

MUX/Serializer

FPGA

L1-buffers

PedSub

PedSub

PedSub

PedSub

E,t N-tap FIR

E,t N-tap FIR

E,t N-tap FIR

E,t N-tap FIR

L0 Accept Logic&

L1 Trigger FeatureExtractor

Level-0,1 Calorimeter Trigger System

L1 AcceptLogic

L0-pipelines

ADC & Gain Selec.

ADC & Gain Selec.

ADC & Gain Selec.

2,3 Gains

ORxArrays

OTx

CLK Fanout

ORx

FELIX

SDRAM

TTC Partition Master

Figure 20. Architecture of the Phase-II readout system of the ATLAS LAr Calorimeters. The new Phase-IIreadout components are shown along the top row of the signal flow. The FEB-2 boards are amplifying andshaping the detector signals and digitize all data at 40-80 MHz. High-bandwidth optical data-transmission isused to send the data to the back-end system equipped with Pre-Processor boards, which are the interfaceto the L1 trigger and the ATLAS DAQ. The Super-Cell trigger readout, to be installed already during thePhase-I upgrade, is shown in the bottom half of the flow diagram. It will provide the input to the low-latencyL0 trigger.

performance requirements hold for the other LAr Calorimeter areas. Cooling capabilities require thepower per channel to be less than 50 mW. Furthermore, the serializer and optical transmitter shouldprovide a data rate of at least 9 Gb/s per fibre excluding packaging and forward error corrections.

Custom ASICs in technologies with feature sizes between 65 nm and 180 nm are being devel-oped to fulfill these requirements [24–26]. Pictures of prototype ADC chips developed within thePhase-I and Phase-II R&D processes are shown in Fig. 22, together with irradiation test resultsfor one of the prototypes. All 12-bit ADC prototypes are confirmed to meet the Phase-II require-ments in terms of radiation and power consumption. Commercial 12-bit ADCs were tested withinthe Phase-I R&D and found to fulfill the specifications [17]. Recent custom developments includetriple-redundant layouts and an active correction of Single Event Effect (SEE) effects [24], schemat-ically shown in Fig. 23, which further improves radiation robustness.

The goal of the further ASIC development is an integration of the pre-amplifier, shaper and ADCstages in a single chip in order to reduce the system complexity and power consumption. It alsoallows fewer supply voltages compared to the current system which will simplify the power distribu-tion system. Early successful designs of pre-amplifier and shaper in SiGe BiCMOS technologies

Chapter V: Calorimeters Page 66 of 229

Fig. 3: The readout architecture for LAr Phase II upgrade [7]

II. ASIC RESEARCH AND DEVELOPMENT

The front-end electronics need to be radiation tolerant andlow power consumption. The radiation tolerance requirementfor the FEB2 will be about 300 kRad. Compared to the oldFEB, most of the functions will be implemented by ASICson the new one, like the pre-amplifier, shaper, ADC and theserializer. Some research and development is ongoing with 65nm and 130 nm CMOS technologies.

For the front-end analog part, the termination and dynamicrange are programmable, they can be 25 ohm with 10 mArange, or 50 ohm with 2 mA range. There will be a lowgain output and a high gain output in both cases. Two parallelinvestigations are on the way. One design employs the 65 nmCMOS technology for a fully-differential preamplifier (shownin Figure 4) and a shaper using 1.2 V power [8]. Capacitivefeedback is used to set the gain, and to decrease the noise.The simulation shows that the linearity is within 0.2% at 8mA range, and within 0.4% for 9 mA range. The noise is 160nA for a 1.3 nF detector capacitance.

Fully‐Differential Amplifier with Passive FeedbackRR

‐ vovi = ‐vo/N

++ ‐ ‐vo

inRii

‐vo/NC

• R‐noise  4kT/R C∙(N‐1)

• Input impedance  +R/(N+1)positivepositive

7• Fully‐differential outputFig. 4: The fully differential preamplifier in 65 nm CMOS

technology [8]

Another design containing a preamplifier is with 130 nmCMOS technology [8]. The power supply is 2.5 V. The

simulation shows that the noise is 150 nA with 1.5 nF detectorcapacitance. The integral non-linearity with CR-RC2 shapingis within 0.2%. The 8 channels prototype has been submittedin April 2016. Figure 5 shows the layout of this chip. Acommon test bench named Front-End Test Board (FETB) isbeing developed for both ASICs, aiming to obtain preliminaryresults in late 2016 and early 2017.

Fig. 5: Layout of the 8 channel preamplifier in 130 nm CMOStechnology [8]

A radiation-tolerant redundant SAR (Successive Approxi-mation) ADC prototype with 65 nm Global Foundry CMOStechnology has been designed, as depicted in Figure 6. With

TWEPP 2015 - 11 - 2015-10-01

Split ADC for SEE Protection

Vi

DoA

Do

ΔDo

DoB

ADCA

SEE Det.

SEE Det.

ADCB

Logic /2

Mu

x

• If ΔDo is large, chose the output of the ADC that is not hit

• A 3-dB SNR gain with normal operation (i.e., no hit)

Fig. 6: Architecture of the SAR ADC in 65 nm CMOStechnology [9]

the pipeline architecture, bit number in the first stage is chosento be 9 bits, which allows fast conversion speed. A SEEdetector is formed by a pair of resistors, a subtract currentamplifier and some digital logic. Layout of the ADC is shownin Figure 7. When SEE occurs in one split-ADC, outputs ofthe two ADCs will be different. By analyzing the outputs,SEE detection circuits will discard the digital output from theADC which is hit by the ionizing particle and choose the otheroutput as the final output.

The first ADC prototype has been tested, and large Digital-to-Analog Converter (DAC) mismatch is observed due to alayout error: some area is not filled with dummy around theSAR. Focused Ion Beam (FIB) surgery is performed to reducethe most significant bit capacitor size by cutting the metal-oxide-metal capacitor fingers. After the FIB, the preliminaryresult shows a 12.1 bits ENOB measured at 10 MHz input fora 40 Msps sampling rate [10].

TWEPP 2015 - 21 - 2015-10-01

Layout Screenshot

Stage1Stage2

CLK GenReference

buffer

Stage1Stage2

65-nm

CMOS

Fig. 7: Layout of the SAR ADC [9]

As part of the versatile link development [11], the VLAD(VCSEL Array Driver) and its low power version low powerVLAD (lpVLAD) have being designed in the 65 nm CMOStechnology. The aim is to include 8 to 12 VLAD lanesin an array optical transmitter (ATx). Figure 8 shows its

Not

revi

ewed

,for

inte

rnal

circ

ulat

ion

onlySMU Developing multi-lane

array optical transmitter, Atxtargeting 8 – 12 lanes

28

Vin_p

Vin_n

VCSELs

Pre_driver current_driverequalizer

Vin_p

Vin_n

Fig. 8: Architecture of the VLAD

architecture. The two-stage pre-driver has a bandwidth of 12.5GHz. Amplitude of its output is 700 mV, which is enoughfor the vertical cavity surface emitting laser. The post layoutsimulations indicate that the power consumption is 35 mWper channel for VLAD, and 20 mW per channel for lpVLAD.Both prototypes are in 65 nm TSMC process. Figure 9 showstheir layout. The test is expected in summer of 2016.VLAD

•  Forpeoplewhomaywanttohaveacloserlookatthelayout

4

o Die2mm×2mm.

o  channelpower~35mW,includingVCSEL.

o Mustbewire-bondedtoacommoncathodeVCSELarraytowork.

lpVLAD•  Forpeoplewhomaywanttohaveacloserlookatthelayout

5

o Die2mm×2mm.

o  channelpower~20mW,includingVCSEL.

o Mustbewire-bondedtoacommoncathodeVCSELarraytowork.

Fig. 9: Layout of the VLAD and lpVLAD

III. CONCLUSION

The new LAr calorimeter main readout system will bedesigned for the Phase-II upgrade. All of the FEBs willbe replaced with a new design. The back-end electronicswill also be upgraded to be compatible with the new two-stage hardware trigger. Research and development of ASICsis ongoing, and some preliminary results will be obtained.Depending on the results, the basic requirement will be to

integrate the preamplifier and shaper. The desirable design willbe to integrate the ADC. The best design is to also integrateserializer, and form an Front-End System On Chip (FESOC)for LAr readout for HL-LHC. The plan is to install the newreadout electronics on the ATLAS detector during the thirdlong shutdown in 2024 to 2026.

REFERENCES

[1] ATLAS Collaboration, The ATLAS Experiment at the CERN LargeHadron Collider, 2008 JINST 3 S08003

[2] ATLAS Collaboration, ATLAS Liquid Argon Calorimeter Technical De-sign Report, CERN-LHCC-96-041, https://cds.cern.ch/record/331061

[3] http://hilumilhc.web.cern.ch/about/hl-lhc-project[4] ATLAS Collaboration, Technical Design Report for the Phase-I Up-

grade of the ATLAS TDAQ System, CERN-LHCC-2013-018, http-s://cds.cern.ch/record/1602235

[5] ATLAS Collaboration, ATLAS Liquid Argon Calorimeter Phase-I Upgrade Technical Design Report, CERN-LHCC-2013-017, http-s://cds.cern.ch/record/1602230

[6] D. O. Damazio, Signal processing for the ATLAS liquid argon calorime-ter: Studies and implementation, 2013 IEEE NSS/MIC, Seoul, Korea,October-November 2013.

[7] ATLAS Collaboration, ATLAS Phase-II Upgrade Scoping Document,CERN-LHCC-2015-020, https://cds.cern.ch/record/2055248/

[8] Laurent Serin, Front End Electronics Developments for the ATLAScalorimeters at HL-LHC, ACES 2016, CERN, March 7-10, 2016

[9] Yun Chiu, Redundant SAR ADC architecture and circuit techniques forATLAS LAr Phase-II upgrade, TWEPP 2015, Lisbon, September 28-October 2, 2015

[10] Hongda Xu et al., Preliminary Experimental Results of A 14-bit Split-SAR ADC for ATLAS LAr Phase-II Upgrade, ACES 2016, CERN, March7-10, 2016 Redundant SAR ADC architecture and circuit techniques forATLAS LAr Phase-II upgrade

[11] https://espace.cern.ch/project-Versatile-Link-Plus/SitePages/Home.aspx