designing wireless communication systems in xilinx...

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Designing Wireless Communication Systems in

Xilinx FPGAs

Copyright © 2011. Avnet, Inc. All rights reserved. Follow @avnetxfest | Tweet this event: #avtxfest

3 Course Objectives

Review wireless communications trends

Explore wireless design challenges Present Xilinx solutions for FPGA-

based wireless and DSP design Introduce Xilinx Software-Defined

Radio Kit for fast prototype of high-bandwidth RF-to-bits wireless systems


4 Agenda

Wireless Communications Trends and Challenges Wireless Receiver Design Xilinx Solutions for Wireless Demos


5 Wireless Communications Infrastructure

Today’s high-performance networks demand high throughput and low latency

Future-proof network designs to support evolving interfaces and connectivity standards

Scale from enterprise femtocell to macrocell


6

Challenge Shannon’s law of data communications – available bandwidth ~ 100 Mhz – spectral efficiency ~ 0.2-0.3 bps/Hz – maximum capacity ~ 100 Mbps avg, 1 Gbps peak / Km2

Multi Carrier Modulation (MCM) – Orthogonal Frequency Division Multiplex (OFDM) – Quadrature Phase-Shift Keying (QPSK); Multilevel

Quadrature Amplitude Modulation (M-QAM) – Challenges of Inter Symbol Interference (ISI) and Peak

to Average Ratio (PAVR) Intelligent antenna arrays (MIMO)

4G Wireless Communications / LTE


7 Wireless Hardware Trends

ENOB = Effective Number of Bits (equivalent performance)

12

14

16

10 11 12 13 14 Range of Actual ENOB

BITS

0

50

100

150

200

250

300

350

400

450

500

Clo

ck R

ate

(MS

PS

)

Time (Not exact)

Clock Rate vs Time

10b

12b

14b

16b

Growing demand for bandwidth Faster data converter sampling rates, up to 3 GSPS Requires increased DSP performance Reduce OPEX by reducing power


8 Kintex-7 FPGAs

Built on low power 28 nm HPL processes

Includes up to 1920 DSP48E1 slices – 2,845 GMACs

Scalable architecture – Artix-7 – Virtex-7

Industries Best Price / Performance

Logic Cells 65,600 - 477,760

DSP Slices 240 - 1920

Max. Transceivers 8 - 32

Transceiver Performance

.5 – 12.5 (Gb/s)

Memory Performance 1,866 (Mb/s)

Max. SelectIO 300 - 500

Virtex Class Performance at ½ the cost and ½ the power


9 ZynqTM-7000 Extensible Processing Platform

Complete ARM®-based Processing System – Dual ARM Cortex™-A9 MPCore™, processor

centric – Integrated memory controllers & peripherals – Fully autonomous to the Programmable Logic

Tightly Integrated Programmable Logic – Used to extend Processing System – High performance AXI based Interface – Scalable density and performance

Flexible Array of I/O – Wide range of external multi-standard I/O – High performance integrated serial transceivers – Analog-to-Digital Converter inputs

7 Series Programmable

Logic

Common Peripherals

Custom

Peripherals

Common Accelerators

Custom Accelerators

Common Peripherals

Processing System

Memory Interfaces

ARM®

Dual Cortex-A9 MPCore™ System


10

Flexible precision through 5 shared interconnect – Implement up to 42x18 mult without pre-add or 36x18

multiply with pre-add Up to 741 MHz Fmax Independent access to pre-adder, adder and accumulator Up to 96 bits of accumulation per DSP48 tile

DSP48E1 Slice

DSP48E1 Slice In

terc

onne

ct

DSP48 Tile

DSP48E1 Slice

DSP48E1 Slice


11 Zynq-7000 DSP Performance

Data Out

Single-MAC Unit

Coefficients

1.2 GHz 50 clock cycles

= 24 MSPS

50 clock cycles

needed

Data In

X

+ Reg

638 MHz 1 clock cycle

= 638 MSPS

Data Out

Fully Parallel Implementation (Zynq-7000 EPP)

50 operations in 1 clock cycle

Data In

X

+

C0 C0 X C1 X C2 X C3 X C49 …

Reg

Reg

Reg

Reg

Sequential (Standard DSP Processor)

Flexible resource / performance trade-off Highest efficiency when DSP48E1 operates near Fmax Zynq-7000 delivers up to 1080 GMACs


12 Power Reduction in Xilinx 7 Series

28nm

Nor

mal

ized

Tot

al P

ower

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

40nm

I/O Power

Dynamic Power

Static Power

50% Lower Power

Increase Usable Performance and Capacity

65%

25+*%

30%

*Savings Beyond 25% from Optimized Hardened Blocks

Transceiver Power 60%

Multi-mode I/O Control

Intelligent Clock Gating

HPL Process

Re-architected Transceivers

7 Series Innovations

Power Binning / Voltage Scaling


13

2x2 LTE Radio Processor

CPRI/OBSAI MASTER

Memory

CPRI/OBSAI SLAVE

Micro Interface

Memory Interface SPI

DAC

DAC

ADC

TxA

TxB

sRX

ADC

ADC

RxA

RxB

Control To ASSPs

DAC’s, ADC’s & Synths (3v3)

SerDes

SerDes

DUC

DUC

DDC

DDC

PC-CFR

PC-CFR

DPD

DPD

SFP/ SFP+

Connectors

Processor

CPRI/OBSAI MASTER

Memory

CPRI/OBSAI SLAVE

Micro Interface

Memory Interface SPI

DAC

DAC

ADC

TxA

TxB

sRX

ADC

ADC

RxA

RxB

Control To ASSPs

DAC’s, ADC’s & Synths (3v3)

SerDes

SerDes

DUC

DUC

DDC

DDC

PC-CFR

PC-CFR

DPD

DPD

SFP/ SFP+

Connectors

2x2 LTE Radio

Virtex-6 LX75T Kintex-7 K70T Requirements Virtex-6

LX75T-FF784 Kintex-7

K70T-FBG676 FPGA Cost 1.0 .30

Sys Performance 368MHz 368MHz

Power 8.7W 4.48W

48% lower power

3X better price /

performance

Kintex-7 Power Reduction Example


14 Agenda



15

Analog / RF

DFE

Baseband Processing

Network Interface

Main Processor

Network Interface

Typical OFDMA Basestation

ADC DAC

ADC

Digital Analog

FEC Decode

FEC Encode

DDC DUC

Constellation Demapper

Constellation Mapper

FFT iFFT DPD & CFR

RF IQ De-Mod

RF IQ Mod

Low noise Amp

ADC

Power Amplifier

Baseband Interface (OBSAI / CPRI)

Control

Processor Control

Interface

Packet

Processing

Focus RX TX

Commercial Radio Communications Architecture


16

ADC

ADC

DAC

DAC

IQ Mod

IQ Demod

FPGA

FPGA

Dist. PLL PLL

VGA

PA

TX/RX Diplexer

LNA

Direct Conversion Architecture TX and RX

VGA

VGA

40 MSPS < Fs < 3 GSPS

400 MSPS < Fs < 3 GSPS


17

d[n]

1

bit stream

SERIAL / PARALLEL J

J bits/symbol

MAP

d

I

Q

d -d

-d

θ

Ex. QPSK constellation

)22 ()( tjeQIjQI θ+=+ 1 2 2( )cos( ( ))oI Q t tθ= + Ω +

)Re()( tj oejQIts Ω+=

)sin()cos( tQtI oo Ω−Ω=

1

S(t)

Digital

Analog

L HI(z) DAC

DAC L HQ(z)

+

_

Digital Up Converter

(DUC)

IQ Modulator

Q

I

)cos( toΩ

)sin( toΩ +

Complex Modulation / Direct Up Conversion


18

-jsin cos

)(tI )cos( toΩ )sin()( ttQ oΩ−=)(ts

ΩoΩ

oΩ−

Q LPF

I LPF

oΩ2

oΩ− 2

oΩ2

oΩ− 2

RF FRONT END

RE

IM

RE

IM

RE

IM

Direct Down Conversion from RF to Baseband


19

cos

Q LPF

I

LPF ADC

RF FRONT END

Q

ADC

Pros: Requires lower ADC

bandwidth = 2fB Broadband capability

Cons: Quadrature errors

from mismatch phase / gain balance between the 2 ADCs

DC offsets

I/Q De-Mod

Bf

Bf

RE

IM

RE

IM

-jsin

Direct Down Conversion from RF to Baseband


20

LPF Decimation filter

Digital Down-Converter (DDC)

nj FIe /ω−

ADC

Pros: Single ADC Eliminates phase / gain

imbalance between the 2 ADCs

Cons: Requires higher ADC

bandwidth and SNR More sensitive to clock

jitter

FPGA

-jsin cos

LPF

LPF

Decimation filter

Decimation filter

RF Mixer

I/F Filter

I

Q

Bf

Bf

RE

IM

RE

IM

I/F Sampling with Digital Quadrature Mixing


21

)(tI )cos( toΩ )sin()( ttQ oΩ−=)(ts

ΩoΩ

oΩ−RF

FRONT END

RE

IM

oj te− Ω

ΩoΩ

oΩ−

RE

IM

0( )δ Ω + Ω

LPF

Euler: cos( ) sin( )oj to oe t j t− Ω = Ω − Ω

Fourier: 0( ) ( )oj te δ± Ω = Ω Ω Multiplication in time domain convolution in

frequency domain

Zero-IF Receiver Complex Math


22

I/Q DEMODULATOR

LOIN

RFIN0

89.5

G1

G4

G3

G2

fVo s1

V fo s2

I IN

QIN

The Imperfect I/Q Demodulator

Offset voltages

Gain Imbalance

(G1,G2,G3,G4) Imbalance in phase splitter

I/Q demodulator is dominant source of mismatch Imbalance in 900 phase splitter is the primary source of phase

imbalance Offset voltages between the I and Q paths cause DC offset


23 Imperfections in the I/Q Signal Path

Offsets within the dual channel ADC

PCB and Layout mismatches

Component mismatches

Control Tuning 90

0

R +/ - 5 %

R +/ - 5 %

LPF

LPF

Voffset 1

Voffset 2

3

Voffset 4 ADC

Voffset3 ADC

Quadrature de-modulator


24

(1 )2 2

o o o oj t j t j t j tj je e e e e ejj

α α

εΩ − Ω Ω − Ω −+ −

= − +

RF FRONT END

ΩoΩ

oΩ−

RE

IM

1LPF

1 1 (1 ) 1 (1 )2

o oj t j tj je e e eα αε εΩ − Ω − = − + + + +

( ) ( )1 1 (1 ) cos sin 1 (1 ) cos sin2

o oj t j te j e jε α α ε α αΩ − Ω = − + + + + + −

cos( ) (1 )sin( )oj to oe t j tε α− Ω = Ω − + Ω +

for 1, 1, cos( ) 1, sin( )α ε α α α≈ ≈

12 2 2

o oj t j te j e jε α αΩ − Ω− ≈ − + −

2α

2α

2ε

Phase & Gain Imbalance in I/Q Demodulator


25

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5

fLO

+10% Quadrature Gain Error

fLO

1o Quadrature Phase Error

fLO

+1% Quadrature Offset Error

Effects of Gain, Offset, and Phase Errors

IQ imbalance distorts constellation at receiver Degradation of receiver performance


26 ADL538x Amplitude and Phase Performance

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700RF Frequency (MHz)

Mag

nitu

de E

rror

(dB

)

TA= -40°CTA= 25°CTA= 85°C

-4

-3

-2

-1

0

1

2

3

4

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700RF Frequency (MHz)

Qua

drat

ure

Phas

e Er

ror

(Deg

rees

)

TA= -40°CTA= 25°CTA= 85°C

ADL5

387

ADL5

382


27 Agenda

Wireless Communications Trends and Challenges Wireless Receiver Design Xilinx Solutions for Wireless Demo


28

High-Speed Analog & RF

DSP Focused Tools Core Generator Wireless IP & Reference Designs

Development Kits

DSP Focused Silicon

Xilinx Solutions for Wireless

Zynq-7000 Software-Defined Radio Kit

Kintex-7 DSP Kit


29

Hardware – Avnet ZEDBoard featuring

Xilinx Zynq-7020 EPP – High-speed analog FMC

module Software Tools

– Xilinx ISE® Design Suite: Embedded Edition(device locked)

– MathWorks Model-Based Design Evaluation Tools

Targeted Reference Designs

Xilinx Zynq-7000 Software-Defined Radio Kit


30 Xilinx Zynq SDR Kits / Target Applications

Wireless communications infrastructure demonstrator – Remote radio head – Software-defined radio – MIMO diversity receivers – Satellite modems

Test and measurement equipment Radar and advanced imaging General-purpose data acquisition


31

Features Software-tunable across wide bandwidth 400MHz → 4GHz

Bypass RF section for baseband sampling Powered from single LPC FMC connector Extensible to multiple FMCs for MIMO

AES-ZSDR-ADI-G / $1450 Avnet ZED baseboard Analog Devices

AD-FMCOMMS1-EBZ Linux drivers, applications

software, HDL source, reference designs

www.em.avnet.com/adizynqsdr

Analog Devices / Zynq-7000 SDR Kit

http://www.em.avnet.com/anazynqsdr


32 Analog Devices AD-FMCCOMMS1-EBZ

Clock Generator /

Sync

Clock distribution

Frequency Synthesizer

ADL5375 ADL5602

ADL5380 AD8366 AD9643

AD9548 AD9523-1 ADF4351

FMC

Connector

RF Out

RF In

Slave Clock In Sync In

DAC

16-bit 1250MSPS*

AD9122 Modulator 400 – 6000MHz

20dB Fixed Gain 50 – 4000MHz

ADC

14-bit 250MSPS

0.25dB Step Size 600MHz Bandwidth

Demodulator 400 – 6000MHz

Output: 1 – 1000MHz Input: 1 Hz - 750MHz

Output: 35 - 4400MHz

ADL5605/6

700 - 1000MHz 1800 – 2700MHz

π π


Master Clock Out

16 + 1 LVDS Pair @ 1000 Mbps 500MHz (DDR)

16 + 1 LVDS Pair @ 500 Mbps 250MHz DDR

π Pi network

Solder bump jumper S

S

S

S

S

1 LVDS Pair

50MHz Ref Clock

SMA connector

I2C / USB to SPI

SPI

SPI SPI SPI

SPI

SPI

SPI

Power

5V @ 500mA

ADL5523

400MHz to 4000MHz Low Noise Amplifier Tuned for frequency

π

Tx

Rx

Optional Front end

Optional Front end 2

2

-9dB

0dB 0dB

Non-SMA connector


33

Processing System

DDR Memory Controller

AMBA® Switches Dual Core Cortex-A9

AMB

A® S

witc

h Hardened Peripherals (USB, GigE, CAN, SPI, UART,I2C)

DDS

S_AXI_GP 32b bit

S_AXI_HP 64 bit

AXI Interconnect

ADC

ADC

DAC

DAC

FMCCOMMS1-EBZ

IQ Mod

IQ Demod

Linux IIO drivers for HDL (data path) and control Linux user-space application for basic example code

Analog Devices Linux-Based Network Scope

Programmable Logic

TCP/IP

Over-the-air RX TX single tone on RF carrier Data analysis displayed in web browser

ADI D

eveloped H

DL (Verilog)

2.4 GHz


34 AD-FMCOMMS1-EBZ potential use case 2x2 MIMO systems with sync

Master / Slave – Connect Master

Clock Out (SMB) to Slave Clock In (SMB)

– Sync Input (SMB) must be connected to same GPIO (CMOS) on FPGA, which asserts once

ADC and DAC Sampling within 1 sampling period, at same phase

FPGA D

evelopment Platform

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC

Master FMC

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC

Slave FMC


35 Pulse 4G LTE antenna SPDA24700/2700

4G Swivel Blade Antenna Performance across the LTE frequency bands -

698-960/1710-2170/2500-2700 MHz Up to 2 dBi Gain SMA connector RoHS Compliant Product Applications - 4G Router, Hub or Access point - Small Base Station / Femto Cell - SOHO / MIMO / Diversity


36

Features Software-tunable across wide bandwidth 400MHz → 4GHz

TDD and FDD support Powered from single LPC FMC connector Extensible to 2X2 MIMO

AES-ZSDR-TI-G / $1850 Avnet ZED baseboard Texas Instruments

FMC30RF FMC HDL source, reference

designs, schematics

www.em.avnet.com/tizynqsdr

Texas Instruments / Zynq-7000 SDR Kit

http://www.em.avnet.com/tizynqsdr


37 Texas Instruments FMC30RF Module

RX Chain & RX LO Clock & Reference

TX Chain

Complete transceiver signal chain – high component integration / low power – Integrated dual DAC & ADC

in AFE7225 – Integrated IQ demodulator +

PGA + buffer + filters in TRF371109

– Integrated and stand-alone PLL/VCO (TRF372017, TRF3765)

– On-board clocking (CDCE62005)


38

RF Switch

DAC

DAC

CDCE62005

ADC

2 lvds

2 lvds

2 lvds

AFE 7225

90

0 Σ

TRF372017

(Max BW=30MHz)

Gain control, general control

Ext. PLL in

TRF3765 400 MHz - 4.8GHz

Rx VCO Out

Tx VCO Out

Clock Out

Ext Clock in

Up to 30MHz IF bandwidth

Texas Instruments FMC30RF Block Diagram

ADC

2 lvds

0 / 90

Clock Generation

TRF3711

PLL VCO

PLL VCO

Ext. PLL in

FMC

Connector

Gain control, general control


39 FPGA-Based IQ Correction

TI offers proven FPGA-based IQ compensation IP http://www.ti.com/lit/an/slwa065/slwa065.pdf


40 EVM Improvement with IQ Correction

Ex: 20.73MHz of LPF Complex BW in TRF3711 EVM is improved by 15dB IQ correction improves receiver performance

-35.90dB -50.30dB

Before IQ Correction After IQ Correction


41

Hardware – KC705 Evaluation Board

• Featuring Kintex-7 325T FF900-2 – 4DSP FMC150 High-Speed analog FMC Module

Software – ISE Design Suite: System Edition

• Device-locked to Kintex-7 325T • Includes System Generator for DSP

Reference Designs – DSP Targeted Reference Design

Documentation – Getting Started Guide – Design Tutorials

Kintex-7 DSP Kit with High-Speed Analog

Ordering Information – Part Number: AES-K7DSP-325T-G – Price: $3,995 www.em.avnet.com\k7DSPkit

http://www.em.avnet.com/k7DSPkit




42

800 MSPS, 16-bit, dual channel, DAC – TI DAC3283

250 MSPS, 14-bit, dual channel, ADC – TI ADS62P49

Clock synchronizer / jitter cleaner – TI CDCE72010

Internal or external clock generation – 491.52 MHz on-board VCXO

4DSP FMC150 Block Diagram

4DSP FMC150 Daughter Card


43 DSP Performance with Over-Clocked DSP48E

Kintex-7 DSP Kit RTL reference design / tutorial Sampling rate 245.76 MSPS (ADC), 491.52 MSPS (DAC) DUC/DDC FIRs over-clocked, 491.52 MHz system clock


44 Xilinx Core Generator FIR Compiler

High-performance finite impulse response (FIR)

Polyphase decimator / interpolator Half-band, Hilbert transform Efficient hardware over- clocking


45 Xilinx Core Generator Wireless IP

Radio – DUC/DDC, CFR, DPD

Connectivity – CPRI/OBSAI, JESD204, SRIO

Baseband – Turbo, Viterbi, MIMO, Channel

Estimation, Channel Encoding, etc

http://www.xilinx.com/esp/wireless/refdes_listing.htm


46 LTE Remote Radio Head

Xilinx radio IP (DUC/DDC/CFR/DPD) Xilinx connectivity IP

– 9.8Gbps CPRI, JESD204B, LVDS Dual core A9 / 800 MHz

– RTOS for housekeeping / DPD coefficient estimation


47 Wideband Direct Conversion Receiver

IF strip millimeter wave backhaul

I

Q

I PP

I PA

QPP

QPA

MAX105

Xilinx FPGA

Digital Baseband DEMOD

Filter

Filter

VCO/PLL SYNTH

MAX2121

MAX2870 PLL/Synthesizer

Millimeter Wave Radio

Down Converter

IF Strip 925-2150MHz BW=200MHz

RFIN=60GHz-80GHz

FCLK=800MHz

I/Q BW=100MHz

Control DC COR

LVDS x4 6-bit Bus

Modulation = 8PSK, Data Rate = 600Mbps

80 dB gain


48 Remote Radio Head Application

Direct RF transmitter architecture advantages – Wide bandwidth, 700MHz to

2.7GHz – No analog mixer/modulator

required – No analog local oscillator

required – DUC in FPGA


49 Direct RF Transmitter

Data Sync

Parity Check

DLL

2:1/4:1 Registered

MUX

DAC Core

FREQ Mode Select

Voltage REF

CLK

MAX5879

Xilinx FPGA

Digital Up Converter

MAX2870 PLL/Synthesizer

FCLK=2.304GHz

LVDS x4 14-bit Bus Direct RF Out

Filter PA

Multi-carrier: 4C-GSM, 4C-WCDMA, and 2C-LTE Multi-band: Simultaneous TX GSM1800 & WCDMA2100 2600MHz LTE in RF mode


50

4 Carrier GSM Center Frequency: 1840MHz Equivalent Amplitude: -15dBFS

MAX5879 – 2.304Gsps using 2:1 MUX and RF Modes

4 Carrier WCDMA Center Frequency: 2140MHz Equivalent Amplitude: -6dBFS

Multi-band Direct RF Transmitter


51 Agenda



52

Symbol Timing

Recovery ( )x t ( )sy kT ( )iy kT

Data strobes

ADC

Digital Symbol Timing Recovery

Analog Digital

Free running sampling clock 1/Ts

PAM signal,

symbol rate T, T/ Ts irrational

Process of re-sampling symbols at optimal time- points, (possibly) asynchronous to ADC sampling clock

Critical receiver function in synchronous communication systems

Matched Filter


53

Interpolator ( )x t

PAM signal,

symbol rate T, T/ Ts irrational

( )sy kT ( )iy kTFilter

Timing Error

Detector

Data strobes

Interpolator adjusts the effective sample interval Ti to synchronize strobes with data symbols

When loop is locked, Ti = T

Matched Filter

Loop filter controller

ADC

Digital Symbol Timing Recovery

Analog Digital

Free running sampling clock 1/Ts

Multirate Digital Filters for Symbol Timing Synchronization in Software Defined Radios IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 19, NO. 12, DECEMBER 2001 Fredric J. Harris and Michael Rice, Senior Members, IEEE


54 Gardner Timing Error Detector (TED)

TED locates optimal symbol re-sampling point

..


55 MathWorks Model-Based Design

The leading environment for technical computing

The leading environment for modeling, simulating, and implementing dynamic and embedded systems

Toolboxes (signal, comms, etc.)

HDL Coder

Embedded Coder TM TM


56 High-Speed Analog With FPGA-Based DSP

System level modeling of FPGA-based DSP in Simulink Data converters free-running at full sampling rate 245.76 MSPS Integrated design flow with Xilinx System Generator and

MathWorks HDL Coder for auto-code generation

Xilinx Kintex-7 DSP Kit with High-Speed Analog

JTAG

www.em.avnet.com\k7dspkit

HDL Coder

http://www.em.avnet.com/k7dspkit


57

FPGA

Demo: QPSK Symbol Timing Recovery

RX FIFO

TX FIFO

Data Converter Interface Hardware

Co-simulation Control

SPI Control

Control FIFO

DAC

JTAG / Ethernet

Simulink transmit-side sources QPSK data to FPGA / DAC Sampled at ADC / FPGA returns data to Simulink receiver-side QPSK symbol timing recovery loop running in Simulink Data converters free-running at full sampling rate

ADC

Kintex-7 DSP Kit with High-Speed Analog

4DSP FMC150


58 Simulink BSP \ Deployment Mode

Simulink board-support package

Auto-generated HDL code connects data converters to user design

ISE project automatically created

Supports Kintex-7 DSP Kit Zynq-7000 SDR Kit support

planned


59

Processing System

DDR Memory Controller

AMBA® Switches Dual Core Cortex-A9

AMB

A® S

witc

h Hardened Peripherals (USB, GigE, CAN, SPI, UART,I2C)

DDS

S_AXI_GP 32b bit

S_AXI_HP 64 bit

AXI Interconnect

ADC

ADC

DAC

DAC

FMCCOMMS1-EBZ

IQ Mod

IQ Demod

Linux IIO drivers for HDL (data path) and control Linux user-space application for basic example code

Analog Devices Linux-Based Network Scope

Programmable Logic

TCP/IP

Over-the-air RX TX single tone on RF carrier Data analysis displayed in web browser

ADI D

eveloped H

DL (Verilog)

2.4 GHz


60

Approved for selected audience – distribution is unauthorized.

LTE / WCDMA

Texas Instruments Zynq SDR Kit Demo

TX RX loopback over-the-air with 2.4 GHz carrier Tx: Continuous waveform offloading Rx: Continuous FFT visualisation


61

TBD TI / 4 DSP / Pierrick

Texas Instruments Zynq SDR Kit Demo

FMC30RF

FPGA


62 Next Steps

Visit FPGA-based wireless communications demos in the exhibit area

Attend hands-on Zynq workshop – Software Defined Radio Development Using Zynq – Coming Fall 2012 – Visit www.em.avnet.com/zynqspeedways

Xilinx Training Courses – In-depth, multi-day training courses

• Zynq EPP System Architecture • Advanced Features and Techniques of Embedded Systems

Software Design

– Visit www.xilinx.com/training for more details

http://www.em.avnet.com/zynqspeedways

http://www.xilinx.com/training

Follow @avnetxfest Tweet this event: #avtxfest www.facebook.com/xfest2012

Thank You Please Visit the Demo Area


64

APPENDIX


65

—Analog Devices Confidential Information—

AD-FMCOMMS1-EBZ Block Diagram

66

Clock Generator /

Sync

Clock distribution


ADL5375 ADL5602

ADL5380 AD8366 AD9643

AD9548 AD9523-1 ADF4351

LPC (32 D

ata + 3 CLK

LVDS) FM

C C

onnector (500MH

z) FPG

A Developm

ent Platform

RF Out

RF In`


DAC

16-bit 1250MSPS*

AD9122 Modulator 400 – 6000MHz

20dB Fixed Gain 50 – 4000MHz

ADC

14-bit 250MSPS


Demodulator 400 – 6000MHz



ADL5605/6

700 - 1000MHz 1800 – 2700MHz

π π


Master Clock Out

16 + 1 LVDS Pair @ 1000 Mbps 500MHz (DDR)

16 + 1 LVDS Pair @ 500 Mbps 250MHz DDR

π Pi network

Solder bump jumper S

S

S

S

S

1 LVDS Pair

50MHz Ref Clock

SMA connector

I2C / USB to SPI

SPI

SPI SPI SPI

SPI

SPI

SPI

Power

5V @ 500mA

ADL5523


π

Tx

Rx

RF output power control is accomplished by adjusting baseband data

Optional Front end

Optional Front end 2

2

-9dB

0dB 0dB

Non-SMA connector

• AD9122 DAC runs at 1000MSPS, due to max speed of AD9523-1


Theory of Operation

Tx Path The transmit path is responsible for taking complex I

and Q signals from system memory and converting these into an appropriate RF signal.

This is accomplished by using the modulation capabilities built into the AD9122 16-bit 1.2GSPS DAC. The DAC interpolates the data and applies a frequency translation to the baseband data. Complex IF shifts the fundamental signal away from DC where LO feed-through and images can be easily filtered and otherwise mitigated.

The complex analog output from the DAC feeds an ADL5375 quadrature modulator via an appropriate filter and matching stage where it is translated to the specified RF output frequency. This signal is then passed through an image rejection filter to an ADL5602 for +20dB gain. RF output power control is accomplished by adjusting the baseband data.

RF outputs up to 4.0 GHz can be synthesized with this board at power levels up to 7.5dBm

Rx Path The Receive path is responsible for taking an

appropriate RF signal and converting this into complex I and Q signals which are placed into system memory.

This is accomplished via an ADL5380 demodulator, which demodulates the observed RF signal to a suitable complex IF (50 to 200MHz).

The I and Q IF signal is filtered and then passed to an AD8366 DVGA, which provides 15.75dB of gain range.

An anti-alias filter is used to remove harmonics and other out of band signals before the signal is digitized with an AD9643 14-bit 250MSPS ADC, and then passed to the FPGA which places the data into system memory.

Clock The AD9548 provides clocking outputs (30.72MHz) directly

related in phase to a reference clock provided by the FPGA (which can be as low as 1pps, from IEEE1588), but with jitter characteristics primarily governed by the system clock (19.2MHz xtal). This drives the AD9532-1, which in turns creates a low jitter (120fs) 982.04MHz (DAC), and 491.52 MHz (ADC) clocks, which are phase synced to each other.

Multiple boards (Master/Slave) can be locked to each other by providing the AD9648 Clock from the Master to the Slave (via a SMB to SMB Cable).

67


Theory of Operation

Optional external boards: The AD-FMCOMMS1-EBZ Tx path can be followed

by an off board ADL5605 (700 – 1000MHz) or ADL5606 (1800 – 2700MHz) 1 Watt amplifier to drive the antenna for ISM based communication standards. Boards available for different frequency bands.

The Rx chain can be driven by an optional (off-board) ADL5523,which is a high performance GaAs pHEMT low noise amplifier. This provides high gain and low noise figure for single-down conversion IF sampling receiver architectures as well as direct-down conversion receivers. Boards available for different frequency bands.

Command/Control paths: Although all devices which require a control

channel are SPI, control of the registers is done via an I2C to SPI translator block (microcontroller). This is done to minimize pin count and maintain LPC form factor.

Control of the board is normally done via I2C accesses from the FPGA but can also be done via USB using a Windows user interface.

Power:

All required power is obtained from the FMC connector (12V @ 1A & 3.3V @ 3A)

68


AD-FMCOMMS1-EBZ Parts/datasheets: Receive Chain

AD9643: 14-bit dual 250MSPS ADC (2011) http://www.analog.com/AD9643 14- bit LVDS output ports, SPI control 785 mW (typ) / $131.57 (1k units)

AD8366: Programmable VGA (2011) http://www.analog.com/AD8366 Dual independent digitally-controlled VGAs −3dB bandwidth of 600MHz 900 mW (typ) / $6.57 (1k units)

ADL5380: 400 - 6000MHz Demodulator (2008) http://www.analog.com/ADL5380 Demodulation Bandwidth ~390MHz 1225 mW (typ) / $5.28 (1k units)

Clocking AD9548: Clock Generator/Synchronizer (2009)

http://www.analog.com/AD9548 Input reference frequencies from 1 Hz to 750MHz 762 mW (typ) / $22.59 (1k units)

AD9523-1: Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs (2010) http://www.analog.com/AD9523-1 Output frequency: <1MHz to 1 GHz 546 mW (typ) / $8.34 (1k units)

ADF4351: Wideband Synthesizer with VCO (2011) http://www.analog.com/ADF4351 fractional-N or integer-N PLL (35MHz to 4400MHz) VCO : 2200MHz to 4400MHz 512mW (typ) / $11.13

Transmit Chain AD9122: 16-Bit, 1200MSPS DAC (2009)

http://www.analog.com/AD9122 LVDS interface, Multiple chip synchronization interfaces 800 mW @ 500 MSP (typ) / $34.50 (1k units)

ADL5375: 400 – 6000MHz Modulator (2008) http://www.analog.com/ADL5375 Output return loss < 14dB from 450MHz to 5.5 GHz 1000mW (typ) / $5.04 (1k units)

ADL5602: 50 – 4000MHz RF/IF Gain Block (2009) http://www.analog.com/ADL5602 Fixed gain of 20dB 445 mW (typ) / $1.75 (1k units)

Power (Switchers & Low Dropout Regulators) ADP2323: Dual 3A, 20V Step-Down Switcher (2011)

http://www.analog.com/ADP2323 >90% efficient over 500mA $2.40 (1k units)

ADP7104: High Accuracy, 500mA LDO (2011) http://www.analog.com/ADP7104 $1.58 (1k units)

ADP150/1: Ultra Low Noise, 150/200 mA LDO (2010) http://www.analog.com/ADP150 $0.31 (1k units)

ADP1740: Low VIN, 2A LDO (2010) http://www.analog.com/ADP1740 $1.20 (1k units)

69

http://www.analog.com/AD9643


http://www.analog.com/ADL5380


http://www.analog.com/AD9523-1

http://www.analog.com/ADF4351




http://www.analog.com/ADP2323





Front end Parts/datasheets: Potential/Optional

Power AMP Boards tuned for 900 or 2400 ISM Bands ADL5605: 700 -1000MHz 1W RF Amplifier (2011)

http://www.analog.com/adl5605 1535mW (typ) / $7.75 (1k units)

ADL5606: 1800 - 2700MHz 1W RF Amplifier (2011) http://www.analog.com/adl5606 1810mW (typ) / $7.75 (1k units)

Low Noise Amplifier ADL5523: 400MHz to 4000MHz LNA (2009)

http://www.analog.com/ADL5523 Noise figure of 0.8dB at 900MHz 300mW (typ) / $1.49 (1k units)

Logarithmic Detector/Controllers AD8318 : 1MHz to 8 GHz, 70dB Logarithmic

Detector/Controller (2007) http://www.analog.com/AD8318 High accuracy: ±1.0dB over 55dB range (f < 5.8 GHz) Low noise measurement/controller output (VOUT) 340mW (typ) / $5.05 (1k units)

True RMS Responding Power Detectors ADL5902 : 50MHz to 9 GHz 65dB TruPwr™ Detector

(2011) http://www.analog.com/ADL5902 Accepts inputs from −62dBm to at least +3dBm Provides voltage output 365mW (typ) / $6.33 (1k units)

70

http://www.analog.com/adl5605

http://www.analog.com/adl5606





ADI supported AD-FMCOMMS1-EBZ use case High speed sampling system

RF section can be bypassed for baseband sampling

Requires moving of “Solder jumpers” default shipping is with RF enabled In this configuration, RF section is powered down (Vcc

not applied to RF) I/O are separate SMB connectors (not

same as used in RF section) 2 channel, 16-bit, 1250 MSPS DAC Clock limits to 1000MSPS

2 channel, 14-bit, 250MSPS ADC

71

FPGA D

evelopment Platform

ADC

ADC

DAC

DAC

FMC


Networked based instruments: Arbitrator waveform generator

Data pattern in memory dumped out DAC (repeat)

Oscilloscope ADC captures data to buffer in memory

Interface is available over Ethernet (web based)

Linux drivers for all devices

72

ADI supported AD-FMCOMMS1-EBZ use case High speed sampling system – software support


ADI supported AD-FMCOMMS1-EBZ use case Loopback

No external cards needed Just a single SMA cable

Used primarily for testing performance and functionality

Tests supported by ADI Dual tone only (No advanced vector

types) Signal analysis done in software on

ARM core (not in HDL) Clocks FPGA provided high speed (50MHz)

and 1Hz clocks

73

FPGA D

evelopment Platform

ADC

ADC

IQ Mod

IQ Demod

DAC

DAC

Master FMC


2-tone test Tones are generated with FPGA DDS,

mixed and sent to DACs Data goes out modulator, and gain

block (0dB) and is fed directly into RF input, where it is demodulated

Data is captured into FIFO/memory on FPGA and data analysis (FFT) is performed via hard or soft core

Data analysis results are available over Ethernet interface Time domain Frequency domain

Linux drivers for all devices

74

ADI supported AD-FMCOMMS1-EBZ use case Loopback – software support:


ADI supported AD-FMCOMMS1-EBZ use case Master/Slave Configuration

Master / Slave Connect Master Clock Out

(SMB) to Slave Clock In (SMB) Sync Input (SMB) must be

connected to same GPIO (CMOS) on FPGA, which asserts once

ADC on different cards (Master/Slave) should be within system level noise figures (1 sample)

75

FPGA D

evelopment Platform

ADC

ADC

IQ Mod

IQ Demod

DAC

DAC

Master FMC

ADC

ADC

IQ Mod

IQ Demod

DAC

DAC

Slave FMC


AD-FMCOMMS1-EBZ potential use case

The following potential use cases are a possibility, which are left as an exercise to be investigated/completed by the user (or third party partner)

Hardware is capable but ADI can not support nor invest effort into developing these demos at the system level

ADI will provide device support (register level, analog implementation support) for anyone wishing to take on these efforts

ADI is interested in discussing appropriate front ends for these types of systems (and others)

76


AD-FMCOMMS1-EBZ potential use case Full or half Duplex Radio

Optional External LNA/PA Card Needs to be frequency tuned

(900MHz, 2400MHz, 4000MHz will use different LNA/PA solutions) Specific solutions in datasheets

Other considerations: external Rx/Tx Switch (not shown/no plan) RF Power Measurement via AMS (no plan)

AD8318 - 1MHz to 8GHz, 70dB − http://www.analog.com/en/circuits-from-the-

lab/CN0150/vc.html ADL5902 - 50MHz to 9GHz, 65dB RF Power

Measurement System − http://www.analog.com/en/circuits-from-the-

lab/CN0178/vc.html

77

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC

Master FMC

FPGA D

evelopment Platform

TruPwr™ Detector

http://www.analog.com/en/circuits-from-the-lab/CN0150/vc.html





AD-FMCOMMS1-EBZ potential use case 2x2 MIMO systems without sync

2 LPC, with no SMB cabling Common clock (from FPGA)

drives 2 Master AD-FMCOMMS1-EBZ Cards

ADC and DAC Sampling within 8-16 sampling periods, and could be off in phase

78

FPGA D

evelopment Platform

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC

Master FMC

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC

Master FMC


AD-FMCOMMS1-EBZ potential use case 2x2 MIMO systems with sync

Master / Slave Connect Master Clock

Out (SMB) to Slave Clock In (SMB) Sync Input (SMB) must

be connected to same GPIO (CMOS) on FPGA, which asserts once

ADC and DAC Sampling

within 1 sampling period, at same phase

79

FPGA D

evelopment Platform

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC

Master FMC

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC

Slave FMC


AD-FMCOMMS1-EBZ potential use case 4x4 MIMO systems

4x4 MIMO – scalable 1GigEthernet IEEE 1588: Precision Time

Protocol (PTP) > 4ns 1 sigma synchronization

possible on sync signals and clocks

AD9548 cleans up pps PTP clock from FPGA PTP slave

Development system connected via Ethernet

4 FMC Cards ADC and DAC Sampling within 1

sample (same phase) between Master/Slave, and within 16 samples between masters (with unknown phase differences)

80

FPGA

Developm

ent Platform

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC Master FMC

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC Slave FMC

FPGA

Developm

ent Platform

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC Master FMC

ADC

ADC

IQ Mod

IQ Demod

PA

DAC

DAC Slave FMC

Netw

ork

The World Leader in High Performance Signal Processing Solutions

ADI Confidential Information – Not for external distribution

AD-FMCOMMS1-EBZ System Level Performance Goals

81


Tx Signal Chain Analysis for RF ~ 2.1GHz

AD9122 NSD ~ -163dBm/Hz

ADL5375 Gain: -3dB, Pout for Vin = 1Vpp: 1dBm P1dB = 9.8dBm OIP3 = 24.6dBm NSD = -160dBm/Hz

ADL5602 Gain: 19.5dB P1dB = 19.3dBm OIP3 = 42dBm NF = 3.3dB

Overall – at RF Out SMA connector Max Pout for 1Vpp: 18.5dBm Typ Pout (PAR=8dB & -3dBFS backoff): 7.5dBm OIP3: 39.8dBm P1dB = 19.3dBm NF = 16.1dB

ADL5605 Gain: 24.3dB P1dB: 30.8dB OIP3: 45.5dBm NF = 4.7dB

82

ADL5375 ADL5602

AD9548 AD9523-1 ADF4351

RF Out DAC

16-bit 1250MSPS*

AD9122

Modulator 400 – 6000MHz

50 – 4000MHz

ADL5605/6

700 - 1000MHz 1800 – 2700MHz

π π

Optional Front-end

• AD9122 DAC runs at 1000MSPS, due to max speed of AD9523-1


Signal Chain Analysis

83

AD9548 Reference inputs: 1pps (Hz) → 750MHz Output frequency 1Hz → 450MHz

AD9523-1 Reference input: up to 400MHz Outputs: 1MHz → 1GHz (independent) Output jitter: <150 fs @122.88MHz (12kHz –

20MHz) Timing jitter : 124fs (rms) Skew between outputs: <50ps

ADF4351 Reference inputs: 1pps (Hz), 800MHz Output jitter: Output phase noise:

ADC/DAC Clocks: Output jitter: -160dBc/Hz SNR impact:

Modulator/Demodulator Clocks: Output jitter: Timing jitter :

Clock Generator /

Sync

Clock distribution


AD9548 AD9523-1 ADF4351





Master Clock Out

1 LVDS Pair

50MHz Ref Clock

SPI SPI SPI

SPI

Demodulator: 35 - 4400MHz

Modulator: 35 - 4400MHz DAC: up to 1000MHz

ADC: up to 500MHz

FPGA provided Clock: 1 Hz - 750MHz • 1pps from IEEE 1588 •System Clock


Rx Signal Chain Analysis for RF ~ 2.1GHz Full Scale Input = +10dBm (At RF In SMA connector)

84

ADL5380 AD8366 AD9643

RF In ADC

14-bit 250MSPS


Demodulator 400MHz – 6000MHz

ADL5380 Gain: 0dB (Rload = 200Ω) IIP3: 29dBm IP1dB: 11.7dB NF: 12dB

AD8366 Gain: -4.5dB OIP3: 50dBm, IIP3 = 55dBm OP1dB: 19dBm, IP1dB: 24dBm NF: 10.5dB

AD9643 SNR = 72dBFS

Overall with Full Scale Input = +10dBm Power Gain: -16dB ADC Input Power: -6dBm IP1dB: 17.8dBm IIP3: 37.9dBm NF: 46.2dB NSD: -143.7dBm/Hz

ADL5523


π -9dB

Optional Front end


Rx Signal Chain Analysis for RF ~ 2.1GHz Full Scale Input = -10dBm (At RF In SMA connector)

85

ADL5380 Gain: 0dB (Rload = 200Ω) IIP3: 29dBm IP1dB: 11.7dB NF: 12dB

AD8366 Gain: +15dB IIP3 = 35dBm (OIP3: 50dBm) IP1dB: 4dBm (OP1dB: 19dBm) NF: 10.5dB

AD9643 SNR = 72dBFS

Overall with Full Scale Input = -10dBm Power Gain: 3.9dB ADC Input Power: -6dBm IP1dB: 0.8dBm IIP3: 33.5dBm NF: 27.5dB NSD = -142.4dBm/Hz

ADL5380 AD8366 AD9643

RF In ADC

14-bit 250MSPS



ADL5523


π -9dB

Optional Front end


Rx Signal Chain Analysis Input at SMB connector

86

AD9643

ADC

14-bit 250MSPS

I Data Q Data


Rx Signal Chain Analysis for RF ~ 2.1GHz Full Scale Input = -10dBm (At RF In SMA connector)

87

ADL5380 AD8366 AD9643

RF In ADC

14-bit 250MSPS



π -9dB

1.5 GHz input into LO 1.5GHz + 8.12345MHz into RF


88


89

Network Processor + DSP SoC + FPGA/ASSP

Xilinx Zynq EPP + Network Processor

Zynq: A new paradigm of integration

Integration

Perf Cost Power

Productivity

- 20% - 50% + 1.5x

3 processing devices →2

Existing Solution

Xilinx 7-series Solution

Radio, Baseband, Connectivity and Higher

Layer IP

Wireless Application: Small Cell


90 Small Cell Application - Benefits

High Level Block Diagram

BOM Cost reduction • Zynq integrates digital radio , baseband and lower layer MAC,

resulting in cost savings of 20% Accelerated Design Productivity & TTM • Productivity increased by using Xilinx IP for DUC/DDC, CFR,

DPD, OBSAI/CPRI and JESD204 Total Power Reduction • Reduction in number of devices, removal of CPRI interface and

7-Series power efficiency vs multi-core SoCs results in power savings of 50%

Success Example:

– Picocell • Fabric based co-processors allow

processing intensive tasks to be offloaded from processors (Robust Header Compression, Ciphering and scheduling acceleration).

• Co-locating MAC with Layer1 reduces end to end latency and allows greater system efficiency.

• Network processor may be removed in low-end picocells and enterprise femtocells, resulting in even greater cost and power savings.


91

A Powerful Embedded Processor Subsystem Some tasks are best done in software. Dual Cortex A9M processors provide the processing power needed to get some serious real time processing done. One Cortex-A9 takes care of control of the Layer1 control, DPD coefficient calculation, and runs the RTOS. The other Cortex-A9 runs part (or all) of the higher layer functions, depending on system requirements.

The performance of 7-Series Fabric The heavy lifting user-plane processing required by 4G basestations is best done in hardware. Coupled with Xilinx’s extensive, optimized suite of Layer1 functions, 7-Series fabric provides superior real-time performance at reduced power dissipation as compared to multi-core SoCs. In this example, fabric is also used to accelerate Layer2 user plane functions, offloading the processors.

Removal of CPRI link, integration of digital radio and baseband Contributes to 50% reduction in power reduction. Helps reduce overall end to end latency, crucial for 4G basestations.

Small Cell Application


92 Mobile Backhaul – Microwave Equipment


BOM Cost reduction • A single Zynq device (7045) can implement Mobile backhaul –

microwave functionality reducing 7 device to 1 Accelerated Design Productivity & TTM • A tight coupling between software and hardware in EPP and

Xilinx signal processing and packet processing reduce time to market

Total Power Reduction • 7 devices are replaced by Zynq 7045 device (-50%) Programmable Systems Integration • Highly integrated system in a single chip

Success Example:

– Mobile Backhaul • FPGA ideal for integrating DSP

intensive Modem and LUT/BRAM centric packet processing functions

• Multi-core extensible processing with Zynq provides path to system on a chip

• FPGA platform offers much needed scalability and extensibility to fit varied network installations and support legacy interfaces

Customer Testimonial – “Xilinx FPGA technology provides a

unique coexistence of high performance computing, packet , and signal processing – it offers a new level of system integration with maximum flexibility and scalability.”

(Tier 1 Communications account)


93

Accelerated Design Productivity & TTM Xilinx multi-core extensible processing Zynq platform uniquely integrates with Xilinx packet and signal processing IP to reduce time to market.

Increased System Performance Closely couple hardware- software co-design with flexible and high performance packet and signal processing in a single chip delivers high performance design.

Programmable System Integration Xilinx multi-core extensible processing combines with programmable packet and signal processing cores to deliver highly scalable and extensible designs

Total Power Reduction Higher integration and less number of devices on board bring reduction in total system power.

BOM Cost Reduction Zynq 7045 device or Kintex + external processor can reduce the 7 devices to 1 or 2 respectively on the board.

Mobile Backhaul – Microwave Equipment


94 Xilinx Connectivity in Base Station Chassis


BOM Cost reduction • Single FPGA integrates co-processor and connectivity reducing

complexity and extending functionality Accelerated Design Productivity & TTM • Xilinx CPRI, OBSAI, and SRIO IP provides fully tested & verified

scalable and extensible interconnect. Total Power Reduction • Minimizes number of devices and back & forth data transfer (-30%) Programmable Systems Integration • Xilinx IP & FPGA allows fine grain traffic forwarding from any channel

card to any radio

Success Example:

– WCDMA/LTE RRU • FPGA integrates high performance

baseband co-processor and connectivity to minimize devices and high speed data transfers.

• FPGA based connectivity provides scalability and extensibility allowing legacy systems to coexist with new

• FPGA based implementation provides fine grain traffic forwarding & switching of traffic between any channel card to/ from any Radio.

Customer Testimonial – “Xilinx FPGA technology provides a

unique coexistence of high performance baseband accelerators and system connectivity– it offers a new level of system integration with maximum flexibility and scalability.”

(Tier 1 Communications account)


95

Minimizes system complexity, improves system performance and flexibility Accelerated Design Productivity & TTM Xilinx LTE Physical Layer baseband IP and fully verified and tested connectivity IP (Gen 2 SRIO, CPRI up to 9.8G, OBSAI, and JESD204B IP) gives jump start to customer designs for building baseband accelerator/ coprocessor and flexible baseband system interconnect.

Increased System Performance Integration of baseband coprocessor and connectivity provides higher performance, streamlines the data flow by reducing high speed back & forth data transfers, and reduces system latency - a vital requirement for an overall improvement in system performance.

Programmable System Integration Xilinx CPRI, OBSAI, SRIO and JESD204 IP allows flexible, and extensible system interfaces to quickly adapt to varied system configurations and needs

BOM Cost Reduction Integration of Connectivity with baseband co-processor and Radio DFE functions (marked squares) reduces the number of devices while improving system functionality

Total Power Reduction Integration reduces number of devices and minimizes high speed data transfers on the baseband and radio boards.

Xilinx Connectivity in Base Station Designs


96


97 AFE7222/25 12-bit Dual ADC/DAC

• Optimized balance of low power and high performance • ADCs achieve 70dB SNR • DACs achieve 76dBc SFDR

• Lowers System Cost and Improves Ease of Use • Lowers digital interface rates, eases analog filtering

requirements • Simpler board clocking solution

• Long battery life in portable applications • Small footprint • Optimization of power savings versus radio type • Potentially removes need for additional control chips

• Dual 12-bit Converters • 65/125MSPS RX ADCs • 130/250MSPS TX DACs

• Integration • Interpolation/Decimation/NCO • Clock Multiplier/Divider

• 120/215mW light sleep with 5us wakeup • 9x9mm 64 pin QFN • Half/Full-Duplex Support • Auxiliary ADC/DACs

Low Power, Small Footprint • Portable Software-Defined Radio • Wireless Infrastructure • Wireless Backhaul, Point-to-Point


98

4-1MUX

SPI Interface, Registers and Control

QM

C O

ffset

±Fs/

4C

oars

e M

ixer

±Fs/

4C

oars

e M

ixer

RX RMS / Peak

Power MeterClockDivide/Multiply

INP_A_ADC

Seria

l LVD

S or

Pa

ralle

l CM

OS

Seria

l LVD

S or

Par

alle

l CM

OS

(8 d

eep

FIFO

)

12b RX ADC B

12b TX DAC A

12b TX DAC B

TempSensor

IOUTP_A_DAC

QM

C G

ain/

Phas

e

InternalReference

12b Aux DAC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

12b RX ADC A

2x H

BF

Inte

rpol

atio

n

2x H

BF

Inte

rpol

atio

n

/2 H

BF

Dec

imat

ion

INN_A_ADC

INP_B_ADCINN_B_ADC

CLKINPCLKINN

IOUTN_A_DAC

IOUTP_B_DAC

IOUTN_B_DAC

AUXDAC_A

VCM AVDD3_DAC = 3.3 V

12b Aux DAC

12b Aux ADC

AUXDAC_B

AUXADC_AAUXADC_B

PDN

SYNC

SENSCLKSDATASDOUT

BIASJ

RESET

DVDD18_DAC = 1.8 V

AVDD18_ADC = 1.8 V

DVDD18 = 1.8 V

AVDD3_AUX = 3.3 V

DVDD18_CLK = 1.8 V

SYNC

SYNC

FUSE_VDD = 1.8V

SYNC

QM

C O

ffset

SYNC

Inve

rse

SIN

C

QM

C G

ain/

Phas

eSYNC

12-bit ADC Outputs

12-bit DAC Inputs

ADC CLK

DAC CLK

Fine

Mix

er

SYNC

NCO

SYNC

Fine

Mix

er

NCO

SYNC

Thermal Pad = Ground

SYNC

Overview AFE722x


99

• Wide range of operation: 300MHz - 4.8GHz • Low Noise Floor: -163 dBm/Hz @ 2140 MHz • OIP3 of 26.5 dBm @ 2140 MHz • P1dB of 12 dBm @ 2140 MHz • Unadjusted Carrier Suppression of -40dBm • Unadjusted Side-Band Suppression of -40dBc • Integrated PLL/VCO to support 300MHz - 4.8GHz • Integer or Fractional mode PLL functionality • LO Synthesizer output with 1/2/4/8 frequency dividers • Baseband Inputs Common Mode Voltage: 1.7 V • Single Supply: 4.5 V – 5.5 V Operation

• Cellular Base Station Transceiver • CDMA: IS95, UMTS, CDMA2000, TD-SCDMA • TDMA: GSM, IS-136, EDGE/UWC-136 • Multicarrier GSM • WiMAX: 802.16d/e • 3GPP: LTE • Point-to-Point (P2P) Microwave • Wideband Software-Defined Radio • Public Safety: TETRA/APC025 • Communication-System Testers TRF3720EVM

EVM

• Flexible solution supports all frequency bands for GSM, UMTS, CDMA2000, LTE, TD-SCDMA, and WiMAX.

• Cuts down on heat dissipation and eliminates the need for additional filtering.

• High linearity is ideal for multi-mode, multi-carrier wireless applications

• Flexibility to support a wide range of operating frequencies and RF step sizes.

• Option to drive Rx chain to reduce BOM costs • Passive interface with DAC5688, forms a highly

linear wideband transmitter with reduced BOM.

TRF372017 300 MHz to 4.8 GHz IQ Modulator with integrated LO Synthesizer


100

• Supports a wide range of frequency bands with optimum receiver performance

• Excellent receiver linearity and sensitivity • High level of integration significantly simplifies

design implementation • Software programmability gives flexibility • Integrated ADC driver allows for direct connection

to ADC • Reduced complexity and BOM • Reduced space requirements • Ideal for WiMAX and LTE Receivers • Significantly reduces power consumption when

not active (ICC = 2mA)

• Family of devices for wideband RF receivers • TRF3711-25 (optimized 1.7 - 2.7 GHz) • TRF3711-35 (optimized 3.3 - 3.8 GHz) • TRF3711-09 (optimized 0.7 - 1.0 GHz)

• Noise Figure of 12 dB (Max Gain, fLO = 1950 MHz) • IIP3 of 24 dBm (Max Gain, fLO = 2400 MHz) • IIP2 of 60 dBm (Max Gain, fLO = 2400 MHz) • Baseband PGA with 24dB of Gain range in 1dB steps • Software programmable Baseband filter (1dB corner) • Integrated ADC driver amplifiers • DC Offset Correction capability • Receives signal bandwidths up to 30MHz • Hardware and Software Power Down • Single Supply: 4.5V – 5.5V Operation • 7mm x 7mm 48-pin QFN Package

• BTS Rx: 3G, WiMAX, LTE Wideband Receivers • BTS Rx: Wideband Multi-Carrier Receivers • RF Test Equipment • High Linearity Direct Down Conversion Receiver

TRF3711-25EVM

ADC

ADC

PLL VCO

TRF3711 ADS5232 ADS62P42 ADS528x

Local Oscillator

Duplexer

TRF3711 Wide Bandwidth Integrated Direct Down Conversion Receiver family


101

Fully integrated synthesizer including PLL, VCO, and partially integrated loop filter;Output frequencies from 11MHz to 1.175GHz

Integrated RMS jitter <500fs (10KHz~20MHz)

One Universal (LVPECL/LVDS/LVCMOS) Inputs, One Auxiliary Input

2/4 Outputs (2 differential LVPECL/LVDS) or 4 single-ended)

On-chip EEPROM determines default state at power up; Fully programmable via SPI port.

Offered in a 32 pin QFN 5mmx5mm

• Wireless BTS (Pico cell, WiMax, Macro Base band) • Data Communications • Medical • Test Equipment • Jitter Cleaners

• Fully Integrated twin VCOs support wide output frequency range and replace costly VCXO

• 20% lower jitter improves Bit-Error-Rate • Selectable input/output standards reduces

translation logic • EEPROM saves default start-up settings • SPI interface provides in-system programming • Small package saves board space

LVPECL/LVCMOS/LVDS

3.3V

Input Divider

VCO2

LVDS/LVPECL/LVCMOS

PFD Charge Pump

Feedback Divider SPI

EEPROM

Loop Filter

VCO1

Pre

scal

er

Crystal/LVCMOS

2 In

divi

dual

Div

ider

In

tege

r

FBIN

CDCE62002 2:2 Frequency Synthesizer/Jitter Cleaner


102

Single device covering 300MHz to 4.8GHz Multiple VCOs covering 2.4GHz to 4.8GHz Fractional-N PLL based on SD modulator with

25 bits resolution (sub-Hz precision) 4 separate differential LO outputs Programmable Integer-N/Fractional-N PLL

– Programmable Σ∆ order (1-4) with up to 25 bit resolution allowing sub-Hz frequency steps

– PLL-Integer mode: 16-bit N divider; 14-bit R divider VCO phase noise: -130dBc/Hz @ 1MHz offset

– Fout=2.8GHz PFD Noise floor of -221 dBc/Hz Power consumption: ~100mA, 3.3V power

supply Packaged in a 32-pin 5x5mm QFN

• Wireless Infrastructure (TX/RX): -WCDMA/CDMA/GSM - TD-SCDMA - LTE/WiMAX

• Software-Defined Radio (SDR) • Military Communications • Satellite Communications • Test and Measurement • Radar • Digital Video Broadcast (DVB)

R DivPFD Charge

Pump

RF Divider

Prescalerdiv p/p+1

From

SP

I

Lock det

SerialInterface

LD

Clock

Data

LE

REFinCPout

Vcntl

VCCs

GNDs

Div1/2/4/8

From SPI

N-Divider

From

SP

I

( ôcontrol

RF1out

RF2out

EXTVCO_in

RF3out

RF4out

TRF3765 Wideband Integer/Fractional-N PLL/VCO


103

Spectrum before/after IQ Correction Before IQ Correction

After IQ Correction

ACLR:

-64.9dBc after correction

Actual signal BW

IQ Correction with single-tap of complex equalizer


104 IQ Correction Licensing

TI can provide a compiled, encoded image of the IQ correction algorithm • One copy will be licensed with each FMC-30RF • Price per copy is $0.50

For customers wishing to purchase IP for production, TI pricing will be provided as follows with TRF3711:

Volume Per Instantiation Cost 0 - 25K $ 0.50 25K - 50K $ 0.40 50K - 100K $ 0.36 > 100K $ 0.30


105


106 Microwave Backhaul – Narrow Band

Direct high IF architecture advantage – synthesize high order modulation with accurate I/Q

matching – excellent carrier and LO suppression – software defined radio frequency planning – programmable channel BW= 7MHz,14MHz, 28MHz,

56MHz, 112MHz FPGA + MAX19681 high IF architecture example

– IF=350MHz, common TX-IF from IDU to ODU – Modulation=QAM256, SR=43.255MS/s, Data

Rate=346Mbps – DAC clock Frequency same as LO

C/Ka/Ku-band transmitter


107 High IF Transmitter

IF-Strip microwave (1st IF=350MHz, 2nd IF=1835MHz)

4:1 MUX

DAC Core

Clock Divider

CLK

MAX19681

MAX2870 PLL/Synth

IF PLVLSET

38dB MAX2091

+

-

X2

Alarm THRESH

IF RMS Out

+

-

RF PLVLSET

LO=1485MHz

RFOUT 1835MHz

Filter

RF RMS Out

40dB

MAX2092

X2

RF Alarm Out +

-

LO

IF 350MHz

CLK=1485MHz

LVDS 12-bit

Bus X4

Voltage REF

Xilinx FPGA Digital

Up Converter

Indoor Unit (IDU) Outdoor Unit (IDU)

MAX2870 PLL/Synth


108 MAX19681 high IF generation at 350MHz

FS = 1.47067Gsps, Symbol rate = 43.255MHz, RRC Filter alpha = 0.3

65dBc ACLR


109 MAX2121 and MAX105


110

fDAC = 2.304 GHz fOUT = 2.64 GHz

ACLR = 64.5 dB

MAX5879: Two 10MHz LTE Carriers @ 2.65GHz


111 SATCOM

Direct conversion receiver-transmit example – L-band IF strip 925MHz-2175MHz – programmable baseband (RX) filter I/Q BW=4MHz-

40MHz, MOD=8PSK – fractional-n synthesizer with VCO bank – 3.3V single supply operation at low power 1W total (RX

and TX) Direct conversion receiver-transmitter advantages

– eliminate IF mixer, image reject filter, VCO and synthesizer

– low cost base band I/Q high-speed ADC and DAC – enable programmable channel bandwidth (RX)

L-band VSAT receiver and transmitter


112 VSAT Modem/Gateway

Maxim Integrated Products, Inc. Company Confidential

Direct conversion L-band transceiver


113

Direct digital synthesis of MC-GSM, WCDMA, LTE Direct digital synthesis of the full DOCSIS band > Reduces power 10X relative to analog solutions Simplifies RF design and reduces time-to-market

Benefits

-165dBc/Hz noise density 9.4dBm output power 2:1 or 4:1 multiplexed LVDS inputs 50Ω differential output termination 2.4W power dissipation NRZ, RZ, RF, and RFZ modes ACP fully tested and guaranteed High-Speed Data Converter Evaluation Platform

(HSDCEP) and Evaluation Kit Available Xilinx 7/6/5-Series FPGA Board FMC Adapter†

Features

Wireless communications DRFI compliant edge QAM generation Wideband direct digital synthesis

Applications

MAX5879

† Future Product – Contact factory for availability

Multi-Nyquist 14-Bit, 2.3Gsps DAC

MAX5879


114

NRZ RF RZ

RFZ

Impulse response -T/2 T/2 -T/2 T/2 -T/2

T/2

(a) (b) (c)

-T/2T/2

(d)

NRZ Mode RZ Mode RFZ Mode RF Mode

Signal synthesis up to 2.8GHz using RF and RFZ modes

Ideal frequency response

(excludes DAC output bandwidth effects)

Selectable Frequency Response MAX5879 Multi-Nyquist DAC


115

April 28, 2012

Pulse 4G LTE Blade Antenna

Product Showcase of SPDA24700/2700


117 PRODUCT INTRODUCTION

Pulse is proud to announce the launch of the SPDA24700/2700 in order to provide a true 4G LTE antenna solution. The antenna has a 3-position swivel-type articulating knuckle and utilizes high efficiency PCB materials. Ideal for access points, routers and small base station applications or integration into other cellular-based OEM packages.

Features - 4G Swivel Blade Antenna - Performance across the LTE frequency

bands - 698-960/1710-2170/2500-2700 MHz

- Up to 2 dBi Gain - SMA connector - RoHS Compliant Product

Applications - 4G Router, Hub or Access point - Small Base Station / Femto Cell - SOHO / MIMO / Diversity

Frequency bands / WIRELESS STANDARDS: GSM Band I-IV, UMTS, W-CDMA, EDGE 3GPP, 4G LTE, WIMAX


118 PRODUCT SPECIFICS

Overview Electrical Specifications Frequency [MHz] 698-960/1710-2170/2500-2700 Nominal Impedance [Ω] 50 VSWR 2.5:1 Gain [dBi] 0 Min-2 Max Polarization Linear Vertical Radiation Pattern Omni Power Rating [W] 3

Mechanical Specifications Radome Material PC/ABS Color Black Weight [oz/g] 1.66 / 47 Dimensions [In/mm] See image Flammability Rating UL94 V-0

Environmental Specifications Operating Temperature [°C] -30 to +70 Storage Temperature [°C] -40 to +85


119 VSWR

1

1.5

2

2.5

365

070

075

080

085

090

095

010

0010

5011

0011

5012

0012

5013

0013

5014

0014

5015

0015

5016

0016

5017

0017

5018

0018

5019

0019

5020

0020

5021

0021

5022

0022

5023

0023

5024

0024

5025

0025

5026

0026

5027

0027

5028

00

VSW

R

Freq (MHz)

S11 Parameter


120 RADIATION PATTERNS

Horizontal Plane (698-960 MHz) Vertical Plane (698-960 MHz)


121


RADIATION PATTERNS


122


RADIATION PATTERNS


123 PEAK GAIN VS. FREQUENCY


124 EFFICIENCY VS. FREQUENCY

0

10

20

30

40

50

60

70

80

700

800

900

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

Effic

ienc

y

Frequency, MHz

700-960 1710-2170 2500-2700

designing wireless communication systems in xilinx...

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