5-1

Designing Stable Control LoopsBy Dan Mitchell and Bob Mammano

ABSTRACT

The objective of this topic is to provide the designer with a practical review of loop compensationtechniques applied to switching power supply feedback control. A top-down system approach is takenstarting with basic feedback control concepts and leading to step-by-step design procedures, initiallyapplied to a simple buck regulator and then expanded to other topologies and control algorithms.Sample designs are demonstrated with Mathcad simulations to illustrate gain and phase margins andtheir impact on performance analysis.

I. INTRODUCTION

Insuring stability of a proposed power supplysolution is often one of the more challengingaspects of the design process. Nothing is moredisconcerting than to have your lovingly craftedbreadboard break into wild oscillations just as itis being demonstrated to the boss or customer,but insuring against this unfortunate event takessome analysis which many designers view asformidable. Paths taken by design engineers oftenemphasize either cut-and-try empirical testing inthe laboratory or computer simulations lookingfor numerical solutions based on complexmathematical models. While both of theseapproaches have a place in circuit design, a basicunderstanding of feedback theory will usuallyallow the definition of an acceptablecompensation network with a minimum ofcomputational effort.

II. STABILITY DEFINED

Fig. 1 gives a quick illustration of at least onedefinition of stability. In its simplest terms, asystem is stable if, when subjected to aperturbation from some source, its response tothat perturbation eventually dies out. Note that inany practical system, instability cannot result in acompletely unbounded response as the systemwill either reach a saturation level – or fail.Oscillation in a switching regulator can, at most,vary the duty cycle between zero and 100% andwhile that may not prevent failure, it will ultimatelimit the response of an unstable system.

Perturbation

Perturbation

StableSystem

UnstableSystem

t

t

Response

Response

Fig. 1. Definition of stability.Another way of visualizing stability is shown

in Fig. 2. While this graphically illustrates theconcept of system stability, it also points out thatwe must make a further distinction betweenlarge-signal and small-signal stability. Whilesmall-signal stability is an important andnecessary criterion, a system could satisfy thisrequirement and yet still become unstable with alarge-signal perturbation. It is important thatdesigners remember that all the gain and phasecalculations we might perform are only to insuresmall-signal stability. These calculations arebased upon – and only applicable to - linearsystems, and a switching regulator is – bydefinition – a non-linear system. We solve thisconundrum by performing our analysis usingsmall-signal perturbations around a large-signaloperating point, a distinction which will befurther clarified in our design procedurediscussion.

5-2

UnconditionallyStable Unstable

Small-SignalStable

Large-SignalUnstable

Fig. 2. Large-signal vs. small-signal stability.

III. FEEDBACK CONTROL PRINCIPLES

The basic regulator is shown in Fig. 3 wherean uncontrolled source of voltage (or current, orpower) is applied to the input of our system withthe expectation that the voltage (or current, orpower) at the output will be very well controlled.The basis of our control is some form ofreference, and any deviation between the outputand the reference becomes an error. In afeedback-controlled system, negative feedback isused to reduce this error to an acceptable value –as close to zero as we want to spend the effort toachieve. Typically, however, we also want toreduce the error quickly, but inherent withfeedback control is the tradeoff between systemresponse and system stability. The moreresponsive the feedback network is, the greaterbecomes the risk of instability.

Output

Feedforward

Feedback

System

Input

Reference

Fig. 3. The basic regulator.

At this point we should also mention thatthere is another method of control – feedforward.With feedforward control, a control signal isdeveloped directly in response to an inputvariation or perturbation. Feedforward is lessaccurate than feedback since output sensing is notinvolved, however, there is no delay waiting foran output error signal to be developed, andfeedforward control cannot cause instability. Itshould be clear that feedforward control willtypically not be adequate as the only controlmethod for a voltage regulator, but it is oftenused together with feedback to improve aregulator’s response to dynamic input variations.

The basis for feedback control is illustratedwith the flow diagram of Fig. 4 where the goal isfor the output to follow the reference predictablyand for the effects of external perturbations, suchas input voltage variations, to be reduced totolerable levels at the output.

G

H

u y+

_NegativeFeedback

Reference Output

Inputs

GH1G

uy

GuGH)1y(GHyGuy

+=

=+−=

Fig. 4. Flow graph of feedback control.Without feedback, the reference-to-output

transfer function y/u is equal to G, and we canexpress the output as

Guy =With the addition of feedback (actually the

subtraction of the feedback signal)yHGGuy −=

and the reference-to-output transfer functionbecomes

GH1G

uy

+=

If we assume that 1GH , then the overalltransfer function simplifies to

H1

uy =

5-3

Not only is this result now independent of G,it is also independent of all the parameters of thesystem which might impact G (supply voltage,temperature, component tolerances, etc.) and isdetermined instead solely by the feedbacknetwork H (and, of course, by the reference).Note that the accuracy of H (usually resistortolerances) and in the summing circuit (erroramplifier offset voltage) will still contribute to anoutput error. In practice, the feedback controlsystem, as modeled in Fig. 4, is designed so that

HG and 1GH over as wide a frequencyrange as possible without incurring instability.

We can make a further refinement to ourgeneralized power regulator with the blockdiagram shown in Fig. 5. Here we have separatedthe power system into two blocks – the powersection and the control circuitry. The powersection handles the load current and is typicallylarge, heavy, and subject to wide temperaturefluctuations. Its switching functions are bydefinition, large-signal phenomenon, normallysimulated in most stability analyses as just a two-state switch with a duty cycle. The output filter isalso considered as a part of the power section butcan be considered as a linear block. The controlcircuitry will normally be made up of a gainblock – the error amplifier – and the pulse-widthmodulator, used to define the duty cycle for thepower switches.

SourcePower

CircuitryLoad

ControlCircuitry

Reference

Feedforward Feedback

Control

Power System

Fig. 5. The general power regulator.

IV. THE BUCK CONVERTER

The simplest form of the above general powerregulator is the buck – or stepdown – topologywhose power stage is shown in Fig. 6. In thisconfiguration, a DC input voltage is switched atsome repetitive rate as it is applied to an outputfilter. The filter averages the duty cyclemodulation of the input voltage to establish anoutput DC voltage lower than the input value.The transfer function for this stage is defined by

:where,dVVT

tV iiON

O =⋅

=

timeonswitchtON −=periodrepetitiveT = (1/fs)

cycledutyd =

Vi

VO

VS2

ttON 1/fS

dVftVVV iSONiO)DC(O ===

R

L

C

S1

S2VS2

+

_VO

+

_Vi

+

_ PWMControl

Fig. 6. The buck converter.Since we assume that the switch and the filter

components are lossless, the ideal efficiency ofthis conversion process is 100%, and regulationof the output voltage level is achieved bycontrolling the duty cycle. The waveforms of Fig.6 assume a continuous conduction mode (CCM)meaning that current is always flowing throughthe inductor – from the switch when it is closed,and from the diode when the switch is open. Theanalysis presented in this topic will emphasizeCCM operation because it is in this mode thatsmall-signal stability is generally more difficultto achieve. In the discontinuous conduction mode(DCM), there is a third switch condition in whichthe inductor, switch, and diode currents are all

5-4

zero. Each switching period starts from the samestate (with zero inductor current), thus effectivelyreducing the system order by one and makingsmall-signal stable performance much easier toachieve. Although beyond the scope of this topic,there may be specialized instances where thelarge-signal stability of a DCM system is ofgreater concern than small-signal stability.

There are several forms of PWM control forthe buck regulator including,• Fixed frequency (fS) with variable tON and

variable tOFF• Fixed tON with variable tOFF and variable fS• Fixed tOFF with variable tON and variable fS• Hysteretic (or “bang-bang”) with tON, tOFF,

and fS all variableEach of these forms have their own set of

advantages and limitations and all have beensuccessfully used, but since all switch moderegulators generate a switching frequencycomponent and its associated harmonics as wellas the intended DC output, electromagneticinterference and noise considerations have madefixed frequency operation by far the mostpopular.

With the exception of hysteretic, all otherforms of PWM control have essentially the samesmall-signal behavior. Thus, without much lossin generality, fixed fS will be the basis for ourdiscussion of classical, small-signal stability.

Hysteretic control is fundamentally differentin that the duty factor is not controlled, per se.Switch turn-off occurs when the output ripplevoltage reaches an upper trip point and turn-onoccurs at a lower threshold. By definition, this isa large-signal controller to which small-signalstability considerations do not apply. In a small-signal sense, it is already unstable and, in amathematical sense, its fast response is due moreto feedforward than feedback.

V. CONTROLLING PULSE-WIDTH MODULATION

A typical implementation for PWM control(in a form which we now call “voltage-modecontrol”) is illustrated in Fig. 7. From the blockdiagram it can be seen that the “width” of thePWM signal is determined by the point in timewhere the sawtooth, or ramp waveform (VR)crosses the voltage level at the output of the error

amplifier (VE). Since VR traverses from zero toVP within a switching period, it follows thatwhen VE = zero, the width of the output pulsewill be zero, and it will increase linearly reaching100% when VE = VP. Therefore the duty cycle ofthe modulator will be VE / VP and since, in abuck converter, the duty cycle has already beendetermined to be VO /Vi, the control gain of themodulator is:

P

i

E

OVV

VV =

SawtoothReference

Amplified ErrorVoltage, VE

Comp+

_

DC Reference

FeedbackSignal

Error Amp

+

_ PWMControl

d = tONfS = VE/VP

VE

PWM

VP

t

ttON T = 1/fS

Fig. 7. Typical PWM control implementation.Note that if VP is made proportional to VI, a

feature which can be accomplished withfeedforward, then the duty cycle will varyinversely proportional to the input voltage andinput-to-output voltage regulation can ideally beachieved with no change in VE.

In this analysis we have assumed completelinearity and that the output of the error amplifier,VE, is a DC voltage. If, in addition to theintended DC component, VE contains excessive“ripple”, due to error amplifier gain at theswitching frequency, then those switchingfrequency components can mix with the sawtoothfrequency components causing the regulator toexhibit large-signal “switching instability”, evenif it has excellent small-signal stability. This typeof instability can cause the regulator to produceeven more ripple, usually at a subharmonic of theswitching frequency, although it may stillregulate at the proper output voltage.

5-5

VI. CHARACTERISTICS OF A LOADED L-CFILTER

The schematic of Fig. 8 shows an L-C filterwith a load, R, where the components have beenconverted to impedances in the frequency domainthrough the use of Laplace transforms. Theoverall transfer function of this network isdescribed by the use of Kirchhoff’s law as

)ps)(ps(LC1

LC1

RCss

LC1

LsCs1R

Cs1R

)s(V)s(V

21

2i

O

−−=

++=

+

=

LS

R VO(s)+

_Vi(s)

+

_1

CS

Fig. 8. Frequency response of a loaded LC filter.By setting the transfer function numerator

and denominator each equal to zero, we canderive the roots of both the numerator, which arethe zeros of the system (none in this equation),and the denominator which gives us the poles.This second-order expression contains two poles,

d2d1 jpandjp ω−α−=ω+α−=where:

1jand,LC1,

RC21 2

d −=α−=ω=α

For lightly damped filters (typical ofswitching regulators), we can often use theapproximation of:

LC1

d =ω≈ω

With ω= js , we see that transfer functionsare complex numbers containing a real part andan imaginary part. The amplitude of a complexnumber is the square root of the sum of thesquares of the real and imaginary parts. Thephase is the inverse tangent (arctan) of the ratioof the imaginary part to the real part. Byevaluating the transfer functions as a function offrequency, we can determine the point whereboth the magnitude and the phase maketransitions. The most common way of doing thisis to plot the gain in dB (20 times the log ofgain), and the phase in degrees, against the log offrequency. These are called Bode plots and alloweasy visualization of the characteristics that wewill use to help define system stability. From thetransfer function equations for Fig. 8, we candetermine that:• The gain = 1 and the phase = 0 for

LC1

ω .

• The gain = LCR and the phase = 90 for

LC1=ω .

• The gain slope = LC1

2ω− and the phase

= 180 for LC1

ω .

For this example of a loaded L-C filter,Mathcad was used to draw the plots shown inFig. 9, with the assumption of an arbitrarilyassigned set of numerical values (which we willlater use for our buck converter example):

Ω=µ=µ= 5.0Rand,F540C,H16L

from which 31085.1 ⋅=α and 41006.1 ⋅=ω .

5-6

From Fig. 9 we substantiate that the gain ofthis filter is unity at low frequencies, experiencesa resonant peak (determined by R) at the second-order pole frequency, and then falls with a slopeof 12 dB/octive (20 dB/decade) at higherfrequencies; while the phase goes through a shiftfrom zero to a 180o lag. This higher frequencyslope is sometimes called a –2 slope since, in thisregion, the function is proportional to 21 ω , or

2−ω .

180

135

90

45

0

-45

-90

-135

-180

Ph

ase

in D

egre

es

10 100 103 104 105

Frequency

40

30

20

10

0

-10

-20

-30

-40

Gai

n in

dB

10 100 103 104 105

Frequency

4d

3 1006.11085.1

5.0RF540CH16L

•=ω•=α

Ω=µ=µ=

Fig. 9. Bode plot of a sample loaded LC filter.

It is worth reinforcing that a system must belinear before frequency-domain techniques, suchas Laplace transforms and Bode plots, apply. Aswitching regulator is not even continuous, letalone linear. Therefore, approximations will haveto be made – first, to average the switchingeffects so that we have a continuous system, andsecondly, to apply a small-signal approximationin order to assume linearity. And, of course, allthis is done under the additional assumptions oflinear passive components and ideal switches.

VII. LINEARIZING THE BUCK CONVERTER

With ideal components, a switching regulatoris a linear circuit for any given switch condition.The concept of averaging can be applied whenthe switching rate is fast with respect to the rateof change of any other parameters of interest. Toquantify this, we can say that the accuracy of theapproximations is excellent up to one-tenth theswitching frequency, “pretty good” for one-third,and one-half is the theoretical limit based on theNyquist sampling criterion.

Fig. 10 shows the process of averaging theoperation of the circuit by combining thecondition when the active switch is closed withthat when it is open. The relationship betweenthese two conditions is the duty cycle of theswitching and its effect is accounted for throughthe use of a hypothetical DC transformer with aturns ratio of the duty cycle, d. With this model,the primary current is now ILd and the secondaryvoltage is Vid. This DC transformer is an artifactfrom Dave Middlebrook at Caltech. It is not areal component but it is valid for your Spicelibrary. We now have a continuous system but itis nonlinear because the transformer turns-ratio,d, is a variable - namely the control variable - andnot a constant.

5-7

Vi VC

+ +

_ _R

Ii

L

C

IL

VO

+

_

VC

+

_R

L

C

IL

VO

+

_

Vi VC

+ +

_ _R

Ii = ILd

L

C

IL

VO

+

_

1:d

Vid+

_

Switch Condition II [(1-d)th of the time]

Switch Condition I [d th of the time]

Circuit Model Using DC Transformer Concept.ILd and Vid are nonlinear terms.

Fig. 10. Averaged buck converter.With an averaged, continuous model, the next

step is to linearize it. We do this exactly the sameway we would linearize any nonlinear,continuous system, namely we define the small-signal parameters based on a large-signaloperating point. This is shown in Fig. 11.Mathematically, the linearization processinvolves separating each variable into its DC (incapitals) and signal frequency ac (with a “hat”)components, and neglecting the products of twohat terms. For the example calculation shown inFig. 11, the product Vid is linearized about theoperating point, ViD.

Vi VC

+ +

_ _R

Ii = ILd

L

C

IL

VO

+

_

1:d

Vid+

_

Vi VC

+ +

_ _R

Ii

L

C

IL

VO

+

_

1:D

ViD+

_dIL

+_ dVi

ILD

0dVwheredVdv)dD)(vV(dv,exampleFor

products"hat"NeglectdDdiIivVv

iiiiii

LLLiii

≈+=++≈

+=+=+=

Fig. 11. Linearized buck converter.The advantage of linearization is that Laplace

transforms (i.e. impedance concepts) apply sothat closed-form algebraic solutions can be foundand plotted (e.g. Bode plots). The range overwhich the linear approximations are validdepends upon the accuracy desired. In general, aslong as the signals are small enough so that theduty factor is not clamped either full on or fulloff for several switching cycles, the linearapproximation works very well. And in any case,small-signal stability as evidenced using Bodeplots is still a necessary condition for overallstability.

VIII. APPLYING THE LINEARIZED MODEL

The flow diagram of the closed-looplinearized buck regulator can be derived byapplying the generalized control law to thelinearized power circuit described above, asshown in Fig. 12. This control law determineshow d(s), the Laplace transformed controlvariable, varies as a function of key circuitparameters. For a second-order system, such asthe buck regulator with one input voltage, it canbe expressed as:

)s(V)s(Q)s(V)s(F)s(I)s(F)s(d i1C2L1 +−−=

5-8

That is, the inductor current variable, theoutput voltage variable, and the input voltagevariable, can each individually contribute to thesystem control variable. As it pertains toswitching regulators, the expression “voltage-mode control” implies that there is no currentfeedback, i.e. F1(s) = 0. “Current-mode control”means that there is a current loop as well as avoltage loop. In either case, there may or may notbe feedforward control, Q1(s). And finally, notethat in this case, F2(s) includes the reference andfeedback summing components.

This generalized control law can then bemade specific to our voltage-mode controlled,buck regulator as shown in Fig. 13, where thefeedback summing point is the differential inputto the Error Amplifier.

ΣΣΣΣ

D

Negative Feedback

)s(V)s(Q)s(V)s(F)s(I)s(F)s(d

VariableControl)s(d

:LawControldGeneralize

i1C2L1 +−−=

≡

ΣΣΣΣvI(s)

Q1(s) Vi

d(s)

F1(s)

IL(s)

Ls VC(s) R

F2(s)

–

+

1/Cs

Fig. 12. Flow graph / schematic of linearizedbuck converter with general control law.

ΣΣΣΣ

DVE(s)

VO(s)Ref

Err Amp

Vi(s)

1/LC

s2+s/RC+1/LCK(s)

,0)s(Q

,V

)s(K)s(F

,0)s(F

1

P2

1

=

=

=

d(s)

Modulator

Vi1VP

LC1

RCss

LCV)s(KV

)s(H)s(G2

P

i

++

=

Fig. 13. Flow graph of linearized buck converterwith voltage-mode control.

The overall open-loop gain is equal to theproduct of the individual gains of the erroramplifier, the modulator, and the output filter,and is shown as:

LC1

RCss

LCV)s(KV

)s(H)s(G2

P

i

++=

There are several points which could be maderelative to the above equation: First, note that thisexpression is independent of the DC duty factorD but is dependent upon the DC input voltage Vi.Hence, as would be expected, the open-loop gainfunction is dependent upon the DC operatingpoint. Secondly, the second term in thedenominator contains the load resistance, R. If Rwere to go to infinity, this term would go to zeroindicating an unstable system, however, thereality is that the circuit would first go to DCMwhere its small-signal operation becomesessentially first order. Finally, the expressionabove also assumes that the output voltage levelis equal to the reference (H = 1). If this is not thecase, the appropriate scale factor would be addedto either the reference or the output voltage priorto the error amplifier input.

Note that we have assumed that G(s)H(s) ispositive in this expression. This is just asimplification in that we are assuming negativefeedback, so the first 180o is implicit andinstability will occur at 180o rather than the 360o

which some control theory texts describe.With Mathcad as a simulation tool, and

utilizing the parameters of our earlier example,the above general transfer equation can be solvedas a function of frequency to yield the Bode plotsshown in Fig. 14.

This example again uses:Ω0.5RµF,540CµH,16L ===

and additionally,

f2jsand,6.5K,kHz100f

V2V,V5V,V12V

s

POi

π===

===

5-9

40

30

20

10

0

-10

-20

60

50

Gai

n in

dB

10 100 103 104 105

Frequency

F540CH16Lp–mVp50RipplekHz100f

V2V5.0RV5VV12V

f2jSLCV)f2(

V)f(H)f(GII

VKV)f(H)f(GI

S

P

Oi

P2

i

P

i

µ=µ=<=

=Ω===

π=π

≈

≈

I II

180

135

90

45

0

-45

-90

-135

-180

Ph

ase

in D

egre

es

10 100 103 104 105

Frequency

6.5Kfor

kHz71.1atdB40LCR

VKVPeakP

i

=

=•=

Fig. 14. Bode plot of a 100 W, 12 V-to-5 V, buckconverter open loop gain with DC error ampgain [K(s) = K].

From these values, the Bode plots give us thegain and the phase of the open-loop transferfunction from which we can see that at lowfrequencies,

dB30V

KV)f(H)f(GP

i =≈

and at the higher frequencies,

octave/dB12ofslopenegativeaLCV)f2(

V)f(H)f(GP

2i

π≈

The peak gain at resonance is:

kHz71.1atdB40LCR

VKV)f(H)f(GP

i ≈⋅≈

At this point we should define some termsimportant to our stability analysis:

A. Gain MarginThe difference between unity gain (zero dB)

and the actual gain when the phase reaches 180o.(In this case it is a positive number.) Therecommended value is -6 dB to –12 dB.

B. Phase MarginThe difference between 180o and the actual

phase when the gain reaches unity gain. (In thiscase it is approaching zero.) The recommendedvalue is 45o to 60o.

C. Stability CriteriaA commonly used derivative from the above

two definitions is that if the slope of the gainresponse as it crosses the unity-gain axis is notmore than -6 dB / octave, the phase margin willbe greater than 45o and the system will be stable.

5-10

These simulations have made noapproximations other than those required forlinearizing the system. It should be understood,however, that phase shift is caused not only byreactive components but also by time delay, suchas transistor storage time or hold time in asampling system. Switch delays normally havelittle effect as long as there is no explicit sample-and-hold function, and the frequencies of interestare well below the switching frequency. Forexample, the effect of a 1 µs delay in a 100 kHzsystem is a phase shift of less than 4o. There willalso be potential phase lags due to the op ampand parasitic components. Thus, althoughtechnically a second-order system couldpotentially be stable since 180o phase lag is onlyasymptotically approached, we can expect thatthis system, as currently defined, will be unstablein practice and, in any case, would suffer seriousringing under any external disturbance. In fact,the plots of Fig. 14 show a system withessentially negative gain margin and zero phasemargin. We had assumed a value for theamplifier gain of 5.6 only because we will usethis value later, but even if it were unity, the gainof the modulator alone could be enough forinstability since we already have 180o phase shiftjust from the output filter.

IX. FREQUENCY COMPENSATION

Recognizing that we have thus far definedwhat amounts to an unstable system, we will nowconsider techniques to shape the open-loop gainfunction to provide adequate gain and phasemargins. Our first approach will be to reduce thegain at a lower frequency such that the unity-gainpoint will be reached with positive phase margin.This is done by rolling off the gain of the erroramplifier with local feedback as shown in Fig.15. With the addition of C2 (R1 and R2 are whatgave us the amplifier gain of 5.6), we now havean amplifier gain of:

)sCR1(RR

)s(V)s(V)s(K

221

2

IN

OUT+

=−=

This amounts to our original DC gain with an

added pole at 22

p CR1=ω .

K(j)

K(j)(deg)

(dB)

0

0-45-90

P = 1/R2C2

log

log10PP/10

20 log(R2/R1)

R2 = infinityProportional Integral (PI) Control

K(s) = 1/R1C2s

1/R1C2

)sCR1(RR

)s(V)s(V)s(K

221

2

IN

OUT

+=−=

R2

R1

C2

VR+

_ VINVOUT

Error Amplifier

Fig. 15. Lag compensation.This single-pole compensation is called lag

compensation and from the asymptoticapproximated plots above, the phase shiftchanges from zero at 1/10 the corner frequency to90o at 10 times the corner frequency. Right at thecorner frequency, the phase is 45o since thedenominator is 1 + j , where the real andimaginary parts are equal. Since the amplitude of1 + j is 2 , the actual gain amplitude at thecorner frequency is reduced by 3 dB (commonlycalled the half-power point).

Remember: The product/division of twocomplex numbers is equal to the sum/differenceof their amplitudes in dB and the sum/differenceof their phase angles.

5-11

The amplitude of the compensated erroramplifier gain in dB adds directly to theamplitude of the other elements in the controlloop, as the amplifier’s phase adds to the overallphase lag.

The Bode plots for lag compensation(implemented in this form as a proportionalintegrator without R2) are shown in Fig. 16. Theasymptotic transfer function equations nowbecome:

At low frequencies,

21P

I

CRfV2V)f(H)f(G

π≈

At high frequencies,

LCCRV)f2(V)f(H)f(G

21P3

I

π≈

f2js π=

The resonant peak = LCR

CRfV2V

21P

I ⋅π

For a 6 dB gain margin at f = 1.71 kHz, weset the peak gain equal to ½ which yields an R1C2product equal to 299. From this we have set R1 =167 kΩ and C2 = 0.02 µF. Note that the gain-bandwidth (the unity gain crossover frequency) isnow less than 300 Hz, an order of magnitudebelow the resonant frequency. Another point ofinterest is that the gain margin of 6 dB was basedon the resonant peak, which in turn is dependentupon the output loading, R, meaning thatdecreasing the regulator’s load could alsodecrease the gain margin. In practice, one woulduse the smallest load (largest R) for which theconverter is still in CCM. While the phase marginis now 90o, the dominant pole has reduced thebandwidth to the point where dynamic responsewill be very poor. (Note that in the complexplane, +90o is the same as –270o. The lagcompensator contributes –90o from the DC value,and above resonance, the LC output filtercontributes another –180o.)

40

30

20

10

0

-10

-20

60

50

Gai

n in

dB

10 100 103 104 105

Frequency

I II

F02.0C,k167R:valuesSample

299CR21

LCR

CRfV2V

,kHz71.1fatinargmgaindB6forLCR

CRfV2VPeak

21

2121P

i

21P

i

µ=Ω=

==⋅π

=

⋅π

=

180

135

90

45

0

-45

-90

-135

-180

Ph

ase

in D

egre

es

10 100 103 104 105

Frequency

Fig. 16. Bode plot of lag-compensated samplebuck converter open-loop gain function.

5-12

A second alternative is lead compensationwhich is described in Fig. 17. Here, instead ofdecreasing the gain we will increase the phase byadding a lead capacitor, C1, to the error amplifier,introducing a network zero (the opposite of apole). Of course, this also increases the gain butif we make the break frequency of this zero, Zω ,the same as the unity gain frequency of theuncompensated buck regulator, we have provideda phase margin of 45o.

The gain equation for the error amplifier withlead compensation is:

1

112

IN

OUT

R)sCR1(R

)s(V)s(V)s(K +=−=

This amounts to the original DC gain with an

added zero at 11

Z CR1=ω

K(j)

K(jω)(deg)

(dB)

0

90450

Z = 1/R1C1log

log10ZZ/10

20 log(R2/R1)

Valid only forK(s) << Op Amp Gain

1

112

IN

OUTR

)sCR1(R)s(V

)s(V)s(K +=−=

Error Amplifier

R2

R1

C1

VR+

_ VINVOUT

Fig. 17. Lead compensation.In practice, pure lead compensation is

physically unrealizable since the gain cannotcontinue to rise indefinitely due to limitations inthe open loop gain-bandwidth of the amplifier.Naturally, the gain-bandwidth of the operationalamplifier used with lead compensation must be

much higher than that required for lagcompensation.

It should be noted that the error amplifier isnot the only place in a switching regulator toexperience a compensating zero. The parasiticequivalent series resistance (ESR) inherent innon-ideal capacitors selected for use as an outputfilter will react with the output capacitance valueto introduce a circuit zero to the system. Manydesigners have relied on this as a “free” (but alsorelatively uncontrolled) method for achievingsome added positive phase margin. (Try to getyour favorite capacitor supplier to guarantee aminimum ESR!)

The circuit of Fig. 18 combines both a leadand a lag in an attempt to gain the best features ofboth – namely low DC error as well as higherbandwidth. In this circuit, a zero capacitor isplaced in parallel with the input resistor while apole capacitor is added in series with thefeedback resistor. The intent here is to provide ahigh gain at low frequencies while still achievingacceptable phase margin at crossover. The gainequation for the error amplifier now becomes:

sCR)sCR1)(sCR1(

)s(V)s(V)s(K

21

1122

IN

OUT ++=−=

K(j)

K(jω)(deg)

(dB)

0

0-45-90

log

log

20 log(R2/R1)

1/R2C2

10/R2C20.1/R2C2

1/R1C1

( )( )sCR

sCR1sCR1)s(V

)s(V)s(K21

1122

IN

OUT ++=−=

R2

R1

C2

VR+

_ VINVOUT

Error Amplifier

C1

Fig. 18. Achieving “zero” DC error.

5-13

The phase lead associated with R2C2 cannotcompletely cancel out the initial 90o phase lagcaused by the integrating capacitor until the

frequency 22CR

10 is reached. Therefore, in order

to ensure that the phase margin due to the zero

associated with R1C1 is not degraded, 22CR

1

must be at least an order of magnitude below theresonant frequency of the system. That is, thephase shift due to the zero caused by R2C2 shouldbe “over” before any other phase shift in thesystem “starts” so that the system is otherwisetransparent to the effects of integrating out theDC error.

X. LARGE-SIGNAL CONSIDERATIONS

We have made several references to the factthat while small-signal stability is a necessaryrequirement for a stable regulator, large-signaleffects cannot be ignored. To illustrate thepotential for a large-signal problem, Fig. 19demonstrates how the amplified output ripplewaveform can interfere with the PWM operation.For simplicity, this illustration assumes aconstant error amplifier gain. Although this is notvery realistic, since we have alreadydemonstrated that a buck converter with constantfeedback gain is likely to be small-signalunstable, it will still serve to demonstrate theconcept that there is a limit to the amount of gainthat the system can have at the switchingfrequency. Beyond this limit, the system willexhibit large-signal instability, regardless of themargins shown in the Bode plot.

VE

PWM

VP

t

t

tRipple

Voltage

m1

m2

TT/2

Fig. 19. Large-signal stability considerations forvoltage-mode control.

In this example, the output ripple voltage(assumed as being largely caused by the outputcapacitor ESR) is amplified by the error amplifiergain to appear in inverted form as VE, the voltagewhich is compared in the PWM modulator to theramp waveform. A necessary condition for large-signal stability is that the slope of VE, designatedm2, must be less that the slope of the ramp, m1. Asample problem can demonstrate the impact ofthis requirement. If we assume that the duty cycleD = 0.5, output ripple = 0.05 volts p-to-p, andVP = 2 volts, then:

TK1.0

2TK05.0mand

T2m 21 ===

Therefore, K must be less than 20.In reality, the problem can be more severe if

there is an unbounded lead network which wouldthen act as a differentiator at the switchingfrequency such that the output from the erroramplifier might approximate a square wave morethan a triangular shape shown in this illustration.While there is no widely accepted designcriterion to define a solution, an empirical rule ofthumb is to insure that that the total system gainis –20 dB or below at the switching frequency. Inany case, this issue is highly application specificand designers should make this determination foreach individual system in the course of theirevaluation.

5-14

XI. DESIGN PROCEDURE

To summarize the design procedure for the lead-compensated, voltage-mode, buck regulator, thestep-by-step approach is demonstrated in the accompanying box.

Design Procedure for Lead-Compensated Voltage-Mode Controlled Buck Converter

R2

R1VR+

_ VOVE

C1C2

C3

For EXAMPLE, Using the Following Parameter Values:

ESR. ofeffect lead cancel toCESRCR Choose :5 Step

error. dc zero"" andgain frequency -low increasedfor LC11.0

CR1 Choose :4 Step

.ffat gain unity for V

LCV)f2(KRR Choose :3 Step

margin. phase 45for f CR2

1 frequency zero Choose :2 Step

).fat n attenuatio dB (20stability signal-largefor 10f f bandwidth -gain Choose :1 Step

32

22

Ci

P2

C

1

2

C11

SS

C

⋅=

=

=π==

°=π

=

V2V 5.0RF540CH16LkHz100fV5VV12V PSOi =Ω=µ=µ====

( )

pF200R

CESRC ..022ESR sheet, data From :5 Step

F02.1058.1R

10C758,10LC1 :4 Step

6.5RRKk59

VLCRVf2R :3 Step

pF1500C,k5.10R amp. op of input Z R 1059.1f2

1CR :2 Step

kHz101010f :1 Step

23

8

2n2n

1

2

i

1P2

C2

1115

C11

5

C

=⋅=Ω=

µ⋅=ω

>==ω

==Ω=π=

=Ω=<<⋅=π

=

==

−

−

log f

fS

20 dB

fC

G(f )H(f ) (dB)

20logVIK

VP

VIK

(2 π f)2VPLC

2 π R2C2

12 π LC

12 π R1C1

1

5-15

In this example, we have added C3 for a high-frequency roll-off, chosen so that the pole

frequency,32CR

1 , cancels the zero frequency at

C)ESR(1 . This reduction in nominal gain-

bandwidth is required to ensure both small-signalstability - with 45o phase margin – and at least20 dB rejection at the switching frequency inapplications where the ESR can vary widely. Ourexample uses three paralleled 180 µF solidtantalum capacitors where the total capacitance is3X and the ESR is 1/3 of a single unit. Note thatthe value of K is much less than the maximum of20 calculated for large-signal stability.

The calculated Bode plots for this exampleare shown in Fig. 20 from which we can see thatthe gain bandwidth of this lead-compensatedcircuit is nearly an order of magnitude greaterthat the resonant frequency of the uncompensatedsystem. This is particularly significant inremembering that the lag-compensated solutionrequired a gain-bandwidth an order of magnitudelower than resonance. The approximate equationswhich are active in defining the gain within thevarious regions of operating frequency are givenbelow:

21P

iCRVf2

V)f(H)f(GIπ

≈

1P

2iRVRV)f(H)f(GII ≈

LCRV)f2(RV)f(H)f(GIII

1P2

2iπ

≈

LCVf2CRV)f(H)f(GIVP

12iπ

≈ .kHz10thangreaterisbandwidthgainTheF02.0C

pF1500Ck59R

k5.10R:for45thangreaterisinargmphaseThe

2

1

2

1

−µ=

=Ω=Ω=

180

135

90

45

0

-45

-90

-135

-180

Ph

ase

in D

egre

es

10 100 103 104 105

Frequency

40

30

20

10

0

-10

-20

60

50

Gai

n in

dB

10 100 103 104 105

Frequency

III III IV

Fig. 20. Bode plot of lead-compensated samplebuck converter open-loop gain function with“zero” DC error.

The final value for gain-bandwidth is12.7 kHz while the phase margin is nearly 55o.The gain margin is well over -20 dB and anyhigher frequency phase lag (as, for example,operational amplifier limitations) would cause thegain to be further reduced.

5-16

We can use Mathcad to plot othercharacteristics of our demonstration example asshown in Fig. 21. These plots show outputimpedance (a measure of load regulation) andaudiosusceptibility (line regulation) as a functionof frequency. The benefits of feedback todynamic performance are graphically illustratedby the comparative curves in these plots.

VO

/ V

i

10 100 103 104 105

Frequency

0.01

10-3

0.1

VO

/ I O

10 100 103 104 105

Frequency

1

-40

-60

-20

0

Output Impedance

Audiosusceptibility

WithoutFeedback

WithFeedback

WithoutFeedback

WithFeedback

Fig. 21. Output impedance andaudiosusceptibility for the lead-compensatedsample buck converter.

XII. PEAK CURRENT-MODE CONTROL

The voltage-mode algorithm which we havebeen using as a model for the preceding analysisachieves its PWM control by comparing the erroramplifier command signal with an artificially-generated sawtooth, or ramp waveform. Withpeak current-mode (C/M) control, thiscomparison ramp is derived from the outputinductor current waveform and thus forms aninner current feedback loop. While there is stillan outer voltage loop, its function is to programthe output inductor current rather than the dutycycle directly. With the open loop characteristicsof a programmable current source, current-modecontrol effectively hides the inductor within theinner loop, changing the resonant two-pole outputfilter to a single lower frequency dominant pole,plus a higher frequency pole at or beyond thegain-bandwidth of the system. In so doing, thetask of compensation is significantly eased. Asimplified block diagram of this topology isshown in Fig. 22 and its operation is described asfollows:

A fixed-frequency oscillator initially sets thelatch which turns on the power switch, causinginductor current to rise according to:

L)VV(

dtdi oi −= .

This current is sensed and converted to avoltage ramp which is compared to the errorsignal from the voltage error amplifier.

When the current ramp crosses the errorsignal, the comparator resets the latch turning offthe power switch, allowing the inductor current

to decay according to L

Vdtdi o−= . While both

DCM and CCM operation are possible, thisexample assumes CCM.

The power switch is held off by the latch untilthe clock initiates the next cycle.

5-17

ViVC

+ +

_ _R

L

CS2Drive

VE

PWM

K(s)

_

RS

Comp

+

_

1:Nt

RSIS1/Nt

VOLatchClock

IS1

IS2

Clock controls turn-onPeak current controls turnoffDuring the on time, IS1 = IL

S1 IL

Ref+

i1

Si

tS2

i

S1

VD)s(Q

R)D1(V)s(KNLf2)s(F

)D1(VLf2)s(F

−=

−=

−=

PWM

VE

RSIS1/Nt RSIS2/Nt

t

t

1/fSd/fS

CLK

t

Fig. 22. Peak current-mode controlimplementation for buck converter.

Current sensing can be accomplished witheither a sensing resistor or a current sensetransformer (as used in this example) but, ineither case, a proportionate voltage waveform isderived for the comparator. One problem withcurrent-mode control is that this waveform oftenalso contains leading-edge noise spikes caused byparasitic capacitance and diode recovery. Thesespikes need to be controlled by either blanking orfiltering or else the comparator may reset thelatch right at the beginning of the power pulse.

Note that this example actually measuresswitch current rather than inductor current sincethe only information needed for control is thepeak value of the inductor current and this isusually more conveniently done in series with thepower switch. What happens to the inductorcurrent after the switch opens is, in principle,unimportant.

However, in CCM applications where theduty cycle may extend beyond 50%, a large-signal, sub-harmonic instability can occur whichis described in Fig. 23.

m1

vE

-m2

VE

d

Actual analog waveform for m1 < m2(D > 0.5) Any perturbation δ will result in switching

instabilitly (switching frequency subharmonics) Need to add external ramp m3 for stabilization

Ideal analog waveform

Effective analog waveform with stabilizing ramp m3

m3

m1+m3

VE m3-m2

m1IL-m2

Fig. 23. Peak current-mode switching instability.The waveforms in the upper portion of this

illustration show the switch current in a CCMapplication with a rising inductor current slopeequal to m1 and a falling slope (when the switchis off) of –m2. Under stable operating conditions,the end of m2 has to match the beginning of m1.With less than 50% duty cycle, |-m2| < m1 andany small perturbation (δ) which might occurduring the switch on-time will be reduced by thetime the next period starts and eventually die outwith successive switching cycles. But with morethan 50% duty cycle, |-m2| > m1 and δ will be

5-18

larger at the start of the next period, resulting inregenerative oscillation.

The cure for this is the addition of anadditional ramp (m3) on top of the currentwaveform so that the controller sees an up-slopeof )mm( 31 + and a downslope of )mm( 32 +− .

If m3 is chosen so that 2

)mm(m 123

−> , then

3123 mmmm +<− and the system will bestable. The minimum value of m3 for the buckconverter (for the impractical condition of justborderline stability) is then

LN2)1D2(RV

2)m-(mm

t

Si123

−==

To determine a more practical value for m3,we first need to determine the overall closed loopgain of the system because this added ramp alsohas the effect of reducing the gain of both thevoltage and current loops by a factor of:

31

1m2m

m+

=γ

With the constraint that 2

)mm(m 123

−> ,

then it is also implied that ( )D

D1−<γ . (This

expression is true for any of the three basicswitching regulator topologies.)

As shown in Fig. 24, the generalized controllaw first presented back in Fig. 12 can be used todevelop individual expressions for the small-signal gains for both the current and voltageloops. This stems from the fact that, inaccordance with basic flow graph theory, thetotal loop gain )s(H)s(G of a system with twotouching loops can be expressed as the sum of theindividual open-loop gains, namely

)s(2H)s(2G)s(1H)s(1G + . Note that the s term inthe numerator of )s(1H)s(1G provides theopportunity for lead compensation, which is whythe inner current loop in current-mode controlcan be thought to compensate the outer voltageloop.

Any transfer function can be expressed

as)]s(H)s(G1[

)s(T+

where T(s) is the transfer

function without feedback and 0)s(H)s(G1 =+ isthe feedback related characteristic equation of thesystem.

40

20

0

-20

60

Gai

n in

dB

10 100 103 104 105

Frequency

f2jsLC1

RCss

RC1s

D1f2

)s(H)s(G2

S

11

π=

++

+

−γ

=

80

100

LC1

RCss

CR)s(NtK

D1f2

)s(H)s(G2

S

S

22++

−γ

=

Gai

n in

dB

10 100 103 104 105

Frequency

40

20

0

-20

60

80

100

Voltage Loop:

Current Loop:

Fig. 24. Individual loop gains for linearized buckconverter with peak current-mode control.

5-19

For our two-loop system, the feedback relatedcharacteristic equation becomes

0)s(H)s(G)s(H)s(G1 2211 =++ . However, aslong as )s(H)s(G 11 is never –1 (in this case thecurrent loop phase shift is never greater than 90o),we can divide both sides of the characteristicequation by 1+ )s(H)s(G 11 to form a new “single-loop” characteristic equation

0)s(H)s(G1)s(H)s(G1

11

22 =++

where the new “single-

loop” open-loop gain function is:

[ ])s(H)s(G1)s(H)s(G)s(H)s(G

11

22

+=

This single-loop representation is illustratedwith the flow graph shown in Fig. 25 and resultsin a new open-loop voltage gain equation:

+

−γ+

−γ

=

RC1s

D1f2s

CR)s(KN

D1f2

)s(H)s(GS

S

tS

ΣΣΣΣ

(D/LC)(1-γ / (1–D))

vE(s) VO(s)Ref

Err Amp

VI(s)

1

(s + 2fSγ/ (1 – D))(s+1/RC)

2fSγ Nt

RSC(1–D)K(s)

Fig. 25. Single-loop flow graph of linearizedbuck converter with peak current-mode control.

for the original circuit with the current-loopclosed. In other words, instead of a resonant

circuit with a double-pole at

LC1 , we now

have a new power circuit with a dominant low

frequency pole at

LC1

RC1 , and another

higher frequency pole at

−γ

LC1

)D1(f2 s .

If we make the assumption that1)s(H)s(G 11 (which is the case with

)D1(ff s−πγ

) the single-loop gain can now be

reduced to simply:

RC1s

CR)s(KN

)s(H)s(G)s(H)s(G)s(H)s(G S

t

11

22

+≈=

and the system is essentially first order.An additional feature achieved with the

combination of the voltage and current loops intothe single-loop flow graph of Fig. 25, we can seethat the gain block associated with the inputvoltage Vi(s) goes to zero for γ = 1 – D,corresponding to, theoretically, zeroaudiosusceptibility. Thus, γ = 1 – D implies an“optimum” ramp for m3 = (VO/L)(RS/2Nt), whichis independent of D and is greater than theminimum requirement previously discussed. Ifwe assume that we have applied this optimumamount of slope compensation such that γ = 1-D,then the generalized equation given in the Fig.reverts to the same simplified form that we havecalculated earlier for all f << fS / π.

5-20

ESR. ofeffect lead cancel toCESRCR Choose :5 Step

error. dc zero"" andgain frequency -low increasedfor RC1

CR1 Choose :4 Step

. fffat gain unity for N

CRf2RRK Choose :3 Step

.dB 20 belly automatica willfat n Attenuatio margin. phase 45for frequency crossover gain unity tocorrespond to/f pole second Choose :2 Step

volts.5.0 e.g. level, noise theabove wellis LfN

)2/VV(DR

ramp) (including analogcurrent peak -to-peak effective that theso /NR Choose :1 Step

32

22

SC

t

SS

1

2

S

S

St

OiS

tS

⋅=

=

π====

°π

+

LN2RV m12/5DF540CH16L

5.0RkHz100fV5VV12V

t

SO3

SOi

==µ=µ=

Ω====

pF100101.1R

CESRC ,.0220ESR sheet, data From :5 Step

pF27001052.2RRCC :4 Step

k107R,k10R amp. op of input ZR8.10N

CRf2RR

K :3 Step

estimate)ion approximat c(asymptoti kHz8.31/ff :2 Step

Turns100N,10R103.0)2/VV(D2

LfNR

:1 Step

10

23

9

22

211t

SS

1

2

SC

tSOi

S

t

S

⋅=⋅=Ω=

⋅==

Ω=Ω=<<===

=π=

=Ω==+

=

−

−

R2

R1

VR+

_ VOVE

C2

C3

For EXAMPLE, Using the Following Parameter Values:

Design Procedure for Peak Current-ModeControlled Buck Converter

log ffS

20 dB

fC

G(f )H(f) (dB)

2 RC1

20log

fS

NtK

2 fRSC

For OptimumRamp

NtKRRS

π

π π

5-21

XIII. DESIGN PROCEDURE FOR PEAK CURRENT-MODE BUCK REGULATOR

To illustrate the design procedure for a buckregulator using a single-loop peak current-modecontrol algorithm, a typical example using acurrent sense transformer and slopecompensation is presented in the accompanyingsidebar box and the results are shown in the BodePlots of Fig. 26.

This example assumes transformer currentsensing and slope compensation, the latterbecause, even though the nominal input-to-outputvoltage ratio predicts a duty cycle of less that50%, operating extremes and circuit tolerancescould potentially push the duty cycle higher and,of course, we have also seen the benefit ofimproved audio susceptability. The designcriterion here is to achieve at least 45o of phasemargin, which corresponds to setting the higherfrequency pole at the unity gain crossoverfrequency, with a gain of -20 dB at the switchingfrequency. This corresponds to an asymptoticallypredicted gain-bandwidth of fS/ 10 , orapproximately fS/π, as compared to the gain-bandwidth of approximately fS/10 for our leadcompensated voltage-mode control example.Note that in push-pull applications, where thepossibility of signal reinforcement at fS/2 exists,additional attenuation at the switching frequencymay be necessary to prevent subharmonicoscillations. More sophisticated analyses,simulations and/or empirical studies could help toadequately address these large-signal issues fornonlinear systems.

180

135

90

45

0

-45

-90

-135

-180

Ph

ase

in D

egre

es

10 100 103 104 105

Frequency

40

20

0

-20

60

Gai

n in

dB

10 100 103 104 105

Frequency

.kHz25thangreaterisbandwidthgainThe −

80

100

pF100Ck10RpF2700Cturns100N

k107R10R

31

2t

2S

=Ω===

Ω=Ω=

The Phase Margin is 45o for:

Fig. 26. Bode plot of peak current-modecontrolled sample buck converter open-loop gainfunction with optimum ramp.

The compensation-related benefits of current-mode control are seen in the plots of Fig. 26,which shows what is essentially a first-ordersystem within the gain-bandwidth. The actualgain-bandwidth of 25 kHz (fS/4) is less than theasymptotic prediction (fS/π) because the curvesare actually rounded at the break points.

5-22

XIV. THE BOOST CONVERTER

The basic boost converter topology is shownin Fig. 27 operating in the continuous conductionmode, (CCM). The operation of this circuit is atwo-step process where, with the switch on,energy is added to the inductor as current

increases according to LV

dtdi i= . When the switch

is opened, the current is shunted to the diode andthe inductor discharges with a decreasing current

according to L

)VV(dtdi io −−= . For steady-state

operation, the average current in the inductormust equal the DC current in the load and theaverage dc voltage across the inductor must equalzero. As distinguished from the buck regulatorwhere the filter inductor and capacitorcontinuously work together as a “team”, in aboost (and flyback) topology they essentiallyalternate in a “bucket-brigade” mode. Whileenergy is being stored in the inductor, thecapacitor is working alone to deliver energy tothe load, and then with the switch open, theinductor replenishes the delivered energy byrecharging the capacitor to prepare it for the nextcycle. Since the average (DC) voltage across theinductor must be zero, we can then write (forCCM)

( )d1vVusgiveswhich

,0)d1)(vV(dv

io

ioi

−=

=−−−

Vi

0

VL

ttON 1/fS

Vi - VO

EqualAreas

R

L

CS1

S2

VO

+

_Vi

+

_PWM

Control

vL+ _

Fig. 27. The boost converter.An important characteristic of both the boost

and the flyback topologies in CCM is thepresence of a “right-half-plane” zero, acharacteristic which gives a gain increase butwith a phase lag. This RHP zero is caused by thedelay between controlling and delivering energyto the load. For example, a sudden increase inload current causes a droop in the output voltage,upon which the controller calls for an increase inthe switch duty cycle to store more energy in theinductor. Increasing the switch on-time, however,causes a decrease in the off-time, meaning thatless energy is going into the capacitor and theoutput voltage thus falls further. Eventually anew balance is reached to regulate at the newload but this RHP delay is almost impossible tocompensate and usually requires a relatively lowfrequency system gain rolloff for simple voltage-mode control.

5-23

XV. DEVELOPING THE SMALL-SIGNAL BOOSTMODEL

As we did with the buck topology, a small-signal model for analysis needs to be developedfrom the equivalent circuit by a process ofaveraging and linearizing. Fig. 28 shows thedevelopment of the average model by the processof first deriving an equivalent circuit for eachstate. Switch condition I corresponds to S1 on andS2 off while switch condition II has S1 off and S2on. Then using the duty cycle relationships, onecan determine the average voltage across theswitch branches of the loops involving inductors,and the average currents through the switchbranches into the nodes involving capacitors.These relationships are then connected using aDC transformer with the appropriate turns ratio.

Vi

+

_

Ii

L

C

IL

VC

+

_R VO

+

_

Vi VC

+ +

_ _R

Ii

L

C

IL

VO

+

_

Vi

+

_

Ii

L

VC

+

_

RCVO

+

_

IL(1 - d)

(1- d):1

VO(1 - d)+

_

IL

Circuit model using DC transformer concept

Switch condition II [(1-d)th of the time]

Switch condition I [(d)th of the time]

Fig. 28. Averaged boost converter.

Fig. 29 then shows the linearization processwhich also follows as it did for the buck but,unlike the buck, the open loop gain function isdependent upon the DC duty factor.

Vi

+

_

Ii

L

VC

+

_

RCVO

+

_

IL(1 - d)

(1- d):1

VO(1 - d)+

_

IL

Vi VC

+ +

_ _

R

Ii

L

CVO

+

_

(1 - D):1

VO(1 - D)+

_

IL(1 - D)IL+_VOd

ILd

Fig. 29. Linearized boost converter.The closed loop flow graph for the resultant

linearized boost converter, using voltage-modecontrol, is presented in Fig. 30. From this flowgraph, we can derive the overall closed loop gainequation as:

LC)D1(

RCss

sL

)D1(R

)D1(RCV)s(KV)s(H)s(G 2

2

2

2P

i

−++

−−

⋅−

=

ΣΣΣΣ

(1 - D)/LC

vE(s) VO(s)

Ref

Modulator & RHP ZeroErr Amp

Vi(s)

1s2 + s/RC + (1 - D)2/LC

Vi(R(1 - D)2/L - s)

VPRC(1 - D)2K(s)

Fig. 30. Flow graph of linearized boost converterwith voltage-mode control.

5-24

Note that due to the duty factor dependency,the term (1 – D) appears in the terms relating toboth the resonant frequency and the RHP zero.The duty factor dependent pole is easy torationalize as the L and C are only connectedduring the (1 – d) portion of the period. There isalso no question about the circuit’suncompensated instability since the RHP zerocontributes an added 90o of phase shift beyondresonance, for a total of 270o. As we have alreadydetermined, this phase lag is related to the extratime delay (as compared to the buck) in gettingenergy from the source out to the load, however,it is also a function of the load. The lighter theload (larger R), the further the RHP pole movesout in frequency and the less it will impact circuitbehavior.

In stabilizing the voltage-mode controlledboost converter, generally only lag compensationis applicable because a set of fixed-frequencylead networks would work for only a very narrowrange of input voltage and output loading. Thus,the typical voltage-mode boost converter exhibitsvery low gain-bandwidth and a poor dynamicresponse. In particular, any sudden line or loadperturbation will result in a damped oscillation atthe effective resonant frequency of the converter.The lag network must be designed for the lowestresonant frequency, corresponding to themaximum D, and at the lightest load for whichthe circuit is still in CCM operation.

These arguments apply to virtually all non-buck topologies. The similarities are evident incomparing the boost flow diagram above with theflyback shown in Fig. 31. The gain equation foran equivalent flyback topology is:

LCN)D1(

RCss

sLDN

)D1(R

)D1(RCV)s(KNDV)s(H)s(G

2

22

2

2

2P

i−++

−−

⋅−

=

ΣΣΣΣ

D(1 - D)/NLC

vE(s) VO(s)Ref

Modulator & RHP ZeroErr Amp

Vi(s)

1

s2 + s/RC + (1 - D)2/N2LC

NDVi(R(1 - D)2/N2LD - s)

VPRC(1 - D)2K(s)

Fig. 31. Flow graph of flyback converter withvoltage-mode control.

In this equation, L is the transformerinductance reflected to the primary, and N is thesecondary-to-primary turns ratio. With stabilityissues and closed-loop dynamics virtually thesame as the boost converter, the designprocedures are effectively the same and, byextension, can also be applied to the Cuk andSEPIC topologies. As we shall see, the use ofcurrent-mode control will significantly improveperformance, allowing these topologies tooperate with a much higher gain-bandwidth.

XVI. CURRENT-MODE CONTROL FOR THEBOOST CONVERTER

The boost converter with current/modecontrol is shown schematically in Fig. 32 and 33– Fig. 32 with peak C/M, and Fig. 33 withaverage C/M implementation. As we havealready mentioned, these circuits are shownassuming the use of current transformers forcurrent sensing. If a resistor was used for sensing,RS still applies but Nt in the equations becomesunity. Peak C/M control allows sensing switchcurrent in place of inductor current and theswitch off-time allows time for the current sensetransformer to reset. With average C/M, we usethe entire inductor waveform, which contains aDC component that would saturate a singlecurrent transformer. Therefore, two are shown inthe schematic, alternating in measuring switchand diode current. These two signals are thensummed to reconstruct the total equivalentinductor current. A current sense resistor in theinput or return line may be a more practicalsolution in all except higher power applicationsbut, again, this just means that Nt = 1 and wehave kept the equations consistent.

5-25

ViVC

+ +

_ _R

L

CS1

S2

Drive

vE

PWM

K2(s)_

RS

Comp+

_

1:Nt

IL

RSIS1/Nt

VO

LatchClock

PWM

VE

IS1

IS2

RSIS1/Nt RSIS2/Nt

t

t

1/fSd/fS

CLK

t

Clock controls turn-on

Peak current controls turn-off

IS1 = IL during on time

Fig. 32. Peak current-mode control for boostconverter.

Vi VC

+ +

_ _R

L

CS1

S2

Drive

VCC

CLK

Gnd

RC

Rd

CC

vE2

Sawtooth

PWM

K2(s)_

RS

K1(s)+

_Comp

+

_

vE1

1:Nt

1:NtIL

RSIL/Nt

VP

0

d = vE1/VP

IS2

IS1

IL = IS1+IS2

Fig. 33. Average current-mode control for boostconverter.

While there are distinct differences betweenpeak and average current-mode control, they areprimarily large-signal characteristics, such as:• Peak C/M often requires slope compensation

where average C/M does not.• Average C/M requires an additional error

amplifier.• Peak C/M offers some input voltage feed

forward (but not generally as effective as inthe buck).

• There is a peak-to-average control error withpeak C/M.

• Average C/M often allows painless crossingof the CCM / DCM mode boundary.

• Peak C/M is highly subject to noisetriggering.Naturally, these differences cause some

applications to be inherently better suited to oneor the other and, in practice, differentapplications may impose significantly differentdesign criteria (e.g., a slow voltage loop in a PFCapplication vs. a high-speed voltage regulator).However, while these distinctions between peakand average control can influence individuallarge-signal design criteria, their small-signalperformance and closed-loop requirements can bevirtually identical for the same application.

Fig. 34 illustrates the large-signal differencesbetween peak and average C/M control for theboost converter. With average C/M, the inductorcurrent ripple creates an opposite-phased signalat the output of the added current error amplifier(K1), amplified by its closed-loop gain. Again,large-signal criterion demands that m2 < m1 butdynamic current loop response is improved as m2approaches m1. With average C/M control, slopecompensation is unnecessary so the slopeequations are:

SPP

1 fVT

Vm ==

LNDVRK

LN)VV(RKm

t

os1

t

ios12 =−=

DVRLNfV

KOS

tSP1 <

With peak C/M control, we need to considerslope compensation in the same manner as withthe buck converter. Here the external rampcriterion is:

L2)1D2(RV

m SO3

−>

which corresponds to γ < (1-D)/D wheregamma is the gain reduction factor introducedearlier. Although adding an externalcompensating ramp improves line regulation forthe boost topology, it is not possible to null outinput voltage sensitivity completely as it waswith the buck regulator. Therefore, there is no“optimum” ramp slope for the boost converterbut setting γ = (1 – D) as we did for the buck isstill a reasonable decision since (1-D) < (1-D)/D.

5-26

vE1

VP

t

t

IL

m1

m2

TT/2

ViL

Vi-VOL

Average:

Peak:DVRLNfVK

LNDVRK

LN)VV(RKm

fVT

Vm

os

tsP1

t

os1

t

ios12

sPP

1

<

=−=

==

.factorreductiongaintheiswhere

,D

D1toingcorrespond

,L2

)1D2(RVm

:iscriterionrampexternalthe,converterboosttheofcasetheIn

SO3

γ

−<γ

−>

R4

R5

RS

IL/NtOp AmpVE1

VE2+

_

K1 = R4/R5

m2 < m1 for large-signal stability

Fig. 34. Large-signal stability considerations forcurrent-mode boost converter.

The overall closed-loop gain equation for thelinearized, C/M controlled, boost converter isderived from the flow graph in Fig. 35 as:

+

+

−−

−=

LFVs

RC2s

sL

)D1(R)D1(RC

)s(FV

)s(H)s(G12

22O

ΣΣΣΣVO(s)

Ref

Vi(s)

VO

RC(1-D)F2(s)

R(1-D)2

Ls

+

+LFV

sRC2s

1

1O

F1

L

Valid for either peakor average control

Fig. 35. Flow graph of single-loop linearized c/mcontrolled boost converter.

The generalized control terms, F1 and F2(s),allow this equation to be used for either peak oraverage current-mode control by defining themas:Peak:

I

S1 V

Lf2F γ=S

122 R

F)s(K)s(F =

Average:

tP

1S1 NV

KRF +

P

122 V

)K1)(s(K)s(F +=

Remember that F1 represents the dependencyof the control variable, d, upon the inductorcurrent while F2(s) relates d to the output voltage.Note that the conditions for equal gain betweenpeak and average control can be determined fromthe values of the terms that make F1 and F2(s)(peak) equal to F1 and F2(s) (average). As it didwith the buck topology, the two resonant poles ofthe output filter have been transformed into twofirst-order poles: a dominate low-frequency poleand a second pole at a much higher frequency.Note that the RHP zero is included in thenumerator.

5-27

XVII. COMPENSATING THE BOOST CONVERTER

The basic boost circuit gain equations andtheir effect are shown in Fig. 36. Note that thegain amplitude characteristic appears to be a first-order system which, in theory, should not needcompensation of the voltage error amplifier toachieve stability. One could say either that thecurrent loop compensates the voltage loop or thatC/M control reduces the second-order system to afirst-order, at least up to the cutoff frequency, fC.Nevertheless, we still do have a second-orderpower system with a right-half-plane zero, sothere is still the potential for a total of 270o ofphase shift. Remember that the pole or zero phaseshift shows up an order of magnitude lower infrequency than a change in amplitude.

log f

fX

6 dBfC

G(f)H(f)

πRC1

(dB) R(1 - D)F2

2F1

(1 - D)F2

2πF1Cf

Valid for either peakor average control22

1OP

2Z

P

Z2O

K)s(K

,L2FV

f

,L2

)D1(Rf

;)f2s(

RC2s

)sf2()D1(RC

FV

)s(H)s(G

=π

=

π−=

π+

+

−π

−=

Fig. 36. Open-loop gain considerations for C/Mcontrolled boost converter.

Since F1 is limited by the large-signalstability criterion, one should avoid thetemptation to assume that the high-frequencypole is beyond the frequency range of interest.While that pole and the RHP zero tend to cancelin terms of magnitude, their phase shifts add.However, it can be shown that if XPZ fff == ,and there is a 6 dB gain margin, (i.e., where thephase shift is 180o) then the phase shift at

crossover is 12731tan180290 1 =

π+ − ,

corresponding to a 53o phase margin. Thus,meeting a 6 dB gain margin should automaticallyinsure at least a 45o phase margin. With this, adesign strategy could be the following:• If fZ < fP, then set fX = fZ• If fP < fZ, then set fx = fP• Worst case when fZ = fP• Set the gain of K2 for an open-loop gain

magnitude < 0.5 at f = fX for at least 6 dBgain margin.As an example of this overall procedure, the

design steps for a hypothetical average C/Mboost converter are outlined in the accompanyingsidebar box. This example, of course, assumes100% efficiency with ideal switches. The choiceof L = 3.2 times critical inductance for DCM issomewhat arbitrary since increasing L in theboost topology does not result in a correspondingreduction in C as it does with the buck topology,however, it does reduce the peak currents that theswitches must accommodate. In this case, theadditional motivation is to show that one can godeep into CCM with the boost topology (and, infact, any non-buck topology) and still achieve awide-band stable system using current-modecontrol.

5-28

ratio.divider output proper for R Choose :7 Step.ESR ofeffect lead cancel toCESRCR Choose :6 Step

error. dc zero"" andgain frequency -low increasedfor RC/2CR1/ Choose :5 Step

. NVKR

)D1(L2CVK choose , ffFor .

)K1(LN2)D1(RCKRK choose , ffFor :4 Step

. LNV2

KRVf and L2

)D1(Rf Calculate :3 Step

stability. signal-largefor DRVLNfVK Choose :2 Step

volts.5.0N/RI e.g. level, noise theabove wellisit that so N/RI Choose :1 Step

3

21

11

2

tP

1SO2ZP

1t

1S2PZ

tP

1SOP

2Z

SO

tSP1

tSp)L(ptSp)L(p

⋅==

−<<

+−<<

π=

π−=

<

=−−

(1%). ripple p-p mV 240 than lessfor chosen is CA52.3

i2iA8i

load. fullat inductance critical times3.2 is L5.0DV5VV2VW96P 6RF110CH12LkHz100fV24VV12V

)DC(L)pp(L)DC(L

RP

SOi

===

====Ω=µ=µ====

−

kHz 25.5)100)(2)(1012(2

)24(10)(1.6

LNV2

KRVf

kHz 19.9)1012(2

6(.5)

L2

)D1(Rf :3 Step

k2.16Rk10R

marginfor 6.12)10)(5(.24

)100)(1012)(2(10

DRV

LNfVK :2 Step

T100N10R101

55.0

i5.0

N

R :1 Step

6tP

1SOP

6

22

Z

45

65

SO

tSP1

tSP)L(Pt

S

=⋅π

=π

=

=⋅π

=π

−=

Ω=Ω=

=⋅

=<

=Ω====

−

−

−

−

Ω+Ω=⋅=−⋅=

−=

=⋅=Ω=

µ=

⋅=

⋅==

Ω=Ω=

=⋅

⋅=+

−<<

−

−

−

2.43k22.4R102632.4524

)102.16(5VV

RVR :7 Step

pF470R/CESRC .032 ESR sheet, data From :6 Step

F05.C103301

)106(1102

RC2

CR1 :5 Step

k10Rk50.7R

75.845.)6.2)(1012)(100(2

)5)(.6.1)(10110(10(6))K1(LN2)D1(RCKRK , ff Since :4 Step

33

3

RO

2R3

12

166-11

21

6

6

1t

1S2PZ

Design Procedure for Average Current-Mode ControlledBoost Converter Control Circuit

R4 R5

RS

IL/Nt

IAmp

VE1 VE

2+

_

K1 = R4 / R5

R1 R2

R3

C1

VAmp

VE2

VR+

_ VO

K2 = R1 / R2R3 = VRR2 / (VO - VR)

C2

For EXAMPLE, Using the Following Parameter Values:

5-29

The gain and phase plots for this example areshown in Fig. 37. Note that this circuit behaves asa first-order system until the RHP zero andhigher frequency poles take over; and then thephase changes doubly fast. This result shows again-bandwidth of > 9 kHz. By comparison, thegain-bandwidth of an equivalent, lag-compensated, voltage-mode control design wouldbe in the range of only 130 Hz.

Again, it should be emphasized thatessentially identical small-signal performancecan be achieved with either peak or average C/Mcontrol, regardless of whether one places theintegrating capacitor in the voltage erroramplifier (as described above), or in the currentamplifier (as it might be in power-factorcorrection circuits).

Obviously, there is much more which couldbe included on this subject but it is hoped thatwith the description and examples presentedherein, the reader will be able to extrapolate toapplications specific to the design problems athand. Additional information on other circuittopologies may be found in the references givenbelow.

XVIII. FOR FURTHER STUDY

Dan Mitchell teaches a two-day coursecovering an in-depth presentation of design,stability, and performance analyses of DC/DCconverters entitled “Switching Regulator Designand Analysis”. This course is a part of theModern Power Conversion Design Techniquesprogram offered by e/j BLOOM associates, Inc.For additional information, Dan may be reachedby phone at (319) 363-8066, or by e-mail atdmmitch@home.com

40

30

20

10

0

-10

-20

80

50

Gai

n in

dB

10 100 103 104 105

Frequency

kHz9BandwidthGaindB7inargMGain

>−=

46inargMPhase =

180

135

90

45

0

-45

-90

-135

-180

Ph

ase

in D

egre

es

10 100 103 104 105

Frequency

60

70

Fig. 37. Open-loop gain function for averagecurrent-controlled sample boost converter.

5-30

REFERENCES

[1] D. M. Mitchell, “DC-DC SwitchingRegulator Analysis”, McGraw-Hill, 1988,DMMitchell Consultants, Cedar Rapids, IA, 1992(reprint version).

[2] D. M. Mitchell, “Small-Signal MathcadDesign Aids”, (Windows 95 / 98 version), e/jBLOOM Associates, Inc., 1999.

[3] George Chryssis, “High-FrequencySwitching Power Supplies”, McGraw-Hill BookCompany, 1984.

[4] Ray Ridley, “A More Accurate Current-Mode Control Model”, Unitrode SeminarHandbook, SEM-1300, Appendix A2.

[5] Lloyd Dixon, “Control Loop Design”,Unitrode Seminar Handbook, SEM-800.

[6] Lloyd Dixon, “Control Loop Design –SEPIC Preregulator Design”, Unitrode SeminarHandbook, SEM-900, Topic 7.

[7] Lloyd Dixon, “Closing the FeedbackLoop”, Unitrode Seminar Handbook, SEM-300,Topic 2.

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third–party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Mailing Address:

Texas InstrumentsPost Office Box 655303Dallas, Texas 75265

Copyright 2002, Texas Instruments Incorporated