designing serdes applications-- 82545/82546, … designing serdes applications— 82545/82546,...

Designing SERDES Applications--82545/82546, 82571/82572 & 631xESB/632xESBApplication Note--AN498

August 2006

AN498 August 20062

Legal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Copyright © 2007, Intel Corporation. All Rights Reserved.

http://www.intel.com

August 2006 AN4983

Designing SERDES Applications—82545/82546, 82571/82572 & 631xESB/632xESB

Contents

1.0 Introduction ..............................................................................................................51.1 Scope ................................................................................................................5

2.0 Basic Circuit Design ...................................................................................................72.1 Design and Layout Considerations .........................................................................9

2.1.1 Board Layout Recommendations.................................................................92.1.2 Board Layout Recommendations for Software Compatibility ...........................92.1.3 Impedance Matching............................................................................... 102.1.4 Gigabit Ethernet Controller Dependencies .................................................. 10

3.0 SERDES Specifications ............................................................................................. 133.1 Transmit and Receive Specifications..................................................................... 133.2 Device ID Specifications ..................................................................................... 13

4.0 Testing for PICMG 3.1 Compliance ........................................................................... 154.1 PICMG Test Setup and Specifications ................................................................... 15

5.0 Component/Material Selection ................................................................................ 21

6.0 References .............................................................................................................. 21

7.0 Reference Schematics ............................................................................................. 23

82545/82546, 82571/82572 & 631xESB/632xESB—Designing SERDES Applications

AN498 August 20064

Revision History

Date Revision Description

August 2006 1.0 Initial release

5


1.0 Introduction

The goal of this document is to enable customers to construct a board layout design using the Serializer-Deserializer (SERDES) interface on Intel Gigabit Ethernet (GbE) controllers. A typical application using the SERDES interface is a GbE fiber design where the electrical interface connects to an optical module. However, another possible application would use the SERDES interface to drive and receive electrical signals over a backplane for board-to-board communication such as in modular servers. The benefit of using the internal SERDES for a backplane is that it reduces the cost, power, and board-size real estate of a design since neither optical module with associated fiber connectors nor copper PHY-related components, such as magnetics and cable connectors, are required. Instead, the electrical signals are sent from the internal SERDES to traces that go to a backplane connection, then over a backplane and another backplane connector to the SERDES-capable link partner for communication.

The use of SERDES is called out in many industry specifications. For example:

• IEEE 802.3z: Gigabit for fiber

• 1000BaseCX: Gigabit over 30 meters of 75 Ω coax cable

• 1000BaseX

• PICMG 3.1: Gigabit over 100 Ω differential backplane

This document was created for use in aiding the design of modular servers or embedded designs that are based on GbE as the protocol for onboard and board-to-board communications. Additionally, it is anticipated that many designs will require compliance with the PICMG 3.1 specification. However, since different Local Area Network (LAN) devices with a SERDES interface might use different DC-biasing and have different signaling voltage levels, there is no single SERDES-SERDES circuit that allows the LAN to work properly with every different possible pair of LAN components. This document is intended to provide basic circuit information; design considerations and testing for PICMG 3.1 compliance that should help a designer overcome many of these issues.

1.1 Scope

This document covers SERDES information for the 82545/82546, 82571/82572, and 631xESB/632xESB. All testing results were performed on modified Intel Network Interface Cards (NICs) using the Intel LAN controller. Similar devices with a SERDES can benefit from this document; however, if using a GbE controller other than the ones described here, designers should verify all device specifications to ensure they meet the requirements of the design.


6

7


2.0 Basic Circuit Design

SERDES is short for a dedicated SERializer / DESerializer pair where typical inputs enter the serializer in a parallel fashion and are then serially aligned so that in one clock period one set of parallel bits (one word) is transmitted.

Figure 1. SERDES Functional Block Diagram

A SERDES design must be treated similar to a typical data transmission network design. The goal is to send data across some distance and have enough S/N (Signal to Noise) ratio at the receive end so that an acceptable level of errors are observed.


8

Figure 2. Basic SERDES-SERDES Backplane Circuit

Designers must consider the signal strength of the transmitter (differential output voltage), the loss due to the transmission media (trace size, shape, length) and receiver sensitivity level (minimum signal level) that detects when a 1 or 0 is being sent. The basic equation is as follows:

Transmitter Output - Physical Medium Induced Loss =Receiver Sensitivity

Ideally, the higher the transmit voltage output level on a SERDES device, the better the design performs. However, most SERDES devices are specified with an output performance range so designers should always design with the minimum, worst-case differential output level to ensure a robust design. Figure 3 shows examples of various devices and the range of their signaling levels.

Figure 3. Peak-to-Peak Voltage Signaling Level of Various Devices

Another factor is the trace shape and length which can be a challenge to a successful design. This is mainly due to the I2R losses of the transmission trace and it determines the loss in signal strength that the transmitted signal is exposed to prior to reaching the receive device. Mechanical connectors can come into play as they disturb the impedance match between the transmitter and receiver which can degrade the signal strength.

The 1000Base-BX GbE backplane specification requires the transmit device and receive device be 100 Ω differentially terminated. Therefore connectors that might distort this impedance generate more loss or noise distortion due to standing waves or Voltage Standing Wave Ratio (VSWR), also termed “insertion loss”. A 1:1 VSWR implies a perfect impedance match between the SERDES device and electrical trace. Any difference or mismatch of these impedances can degrade an optimal power transfer.

Finally, the receive device must be chosen so that when the data signal reaches the end of the line that enough voltage amplitude remains to determine if a 1 or 0 has been sent. The receiver component should be carefully chosen to include adequate design margin above the receive sensitivity. For example, a receiver with the lowest input sensitivity level provides the best margin for a design as it helps make up for the variability of the transmitter, connector, and medium losses.

OOUUTTPPUUTT

DDRRIIVVEE

00 mmVV 2200000011000000 1155000055000000

LV-PECL (1200-2000mV)

LV-PECL (200-2000mV)

82546GB (750 -1350mV)

PicoLight PL-XSL-00513-03 (300-2000mV)

PICMG 3.1 Spec at TP-R (200-1350mV)

PicoLight PL-XSL-00513-03 (600 -1200mV)

PICMG 3.1 Spec at TP-1 (750 -1350mV)

MMeeddiiaa//CCoonnnneeccttoorr LLoossss BBuuddggeett

82546GB (200-2000mV)IINNPPUUTT

SSEENNSSIITTIIVVIITTYY

9


2.1 Design and Layout Considerations

2.1.1 Board Layout Recommendations

In Gigabit SERDES-SERDES systems, the main design elements are the GbE controllers, the backplane connectors, and the backplane. Since the transmission line medium extends onto the Printed Circuit Board (PCB), special attention must be paid to layout and routing of the differential signal pairs, as well as to the choice of the connectors. This section discusses the most critical aspects of optimizing and maintaining a usable, valid signal in a SERDES-SERDES design in both directions over the backplane.

The differential pairs should be routed to be as short and symmetrical as possible. The overall length of differential pairs is dependent on meeting Bit Error Rate (BER) requirements which in turn is dependent on material characteristics, S21 loss in the channel, the maximum transmitter output and the minimum receiver input voltage (Rx sensitivity). The general formula used to calculate the minimum received signal for successful reception is:

Rxmin = Txmax - (Connector S21 attenuation + Backplane Trace S21 attenuation)

The lengths of the differential traces (within each pair) should be equal within 50 mils (1.25 mm) and as symmetrical as possible. Asymmetrical and unequal length traces in differential pairs contribute to common mode noise. Strip line is best to use, routed as close to connectors' layer as possible, edge coupled with 100 Ω differential trace pairs. Traces should have at minimum 100 mils spacing between differential pairs with greater than 300 mils recommended to minimize crosstalk between differential pairs. To help minimize EMI problems do not route differential traces near board edges. Within pairs keep traces close as possible to meet 100 Ω differential (<10 mils).

Keep traces as symmetrical as possible when laying out such things as components, pads, and test points keeping components as small as possible. It is critical to minimize stubs which attenuate the signal negatively. Use standard, good trace routing such as avoiding 90 degree bends; instead use two 45 degree bends with beveled corners to obtain 90 degree turns. Avoid routing differential traces near digital signal traces on the same layer and ensure that digital signal traces on adjacent layers cross at 90 degree angles to the differential traces. Keep vias to a minimum, if used at all, using no more than two per trace.

Avoid highly resistive traces by making traces as wide as possible and as thick as possible while maintaining the 100 Ω differential trace impedance. Trace width greater than 8-10 mils width is desirable. Keep transmit traces to the backplane as short as possible with two to four inches being desirable to reduce S21 loss. Additionally, trace routes of long distances should be routed at an off-angle at the x-y axis of the PCB, to distribute the effects of fiberglass bundle weaves and resin rich areas of the dielectric.

2.1.2 Board Layout Recommendations for Software Compatibility

It is recommended that all fiber-based implementations connect the energy sense output of the attached optics to Software Defined Pin (SDP) 1. This allows the software to detect a valid cable much more accurately than possible without it. Intel NIC implementations follow this recommendation and by choosing to include this in the design allows better software re-use and compatibility without requiring significant driver changes. The device EEPROM must be modified to reflect the nature of the pin being a Input pin. Please consult the appropriate EEPROM documentation for details.

For pure SERDES implementations, it is also recommended that an EEPROM be used in order to store driver-needed data for SERDES amplitude attenuation values. This allows for environmental tuning without significant modifications from the Intel driver baseline.


10

These recommendations are based on Intel’s own experience with cost savings and higher product quality via a more refined end-user experience. The marginal cost increase of adding these extra hardware resources can be justified by the savings of software resources to overcome the lack of these recommendations.

2.1.3 Impedance Matching

Maintain 100 Ω +10% differential impedance by choosing the appropriate backplane connector and PCB layout. Match the connectors' impedance as closely as possible. Transmit and receive pairs should be AC coupled through a 0.01uF capacitor to overcome differences in DC levels between the different logic types such as PECL, LVDL and etc. Place capacitors shown in the termination networks as close as possible to the receiver pins. Keep the connectors as close to the GbE controller as possible.

Connectors must be impedance-matched and specified for 1.25 GHz first harmonic of the data rate and 625 MHz fundamental frequency. Pairs must be separated from adjacent pairs by having grounds between them on the connectors. The Tyco® HM-Zd or equivalent connector is a valid reference for performance when selecting a connector for your design.

2.1.4 Gigabit Ethernet Controller Dependencies

2.1.4.1 Output Voltage Adjustment

82545 and 82546

The differential output amplitude can be adjusted by changing the value of the Extended PHY Specific Control 2 Register (Address: 26) bits 3:0. Each bit set increases the amplitude as listed in Table 1.

Table 1. SERDES Typical Output Peak-to-Peak Differential Voltage vs. Bit Setting (82545 & 82546)

A driver, including Intel's, can be used to set the above register during initialization by placing the values desired in bits 3:0 of Word 06h in the EEPROM. For customer developed drivers, design the driver to read these bits and transfer the values to the Extended PHY Specific Control 2 Register.

82571 and 82572

For the 82571 and 82572, the differential output amplitude is controlled in the EEPROM image. Besides the default amplitude, there are Low and High Amplitude settings.

Bits 3:0 Register Setting Typical P-P Voltage Output at TP-1

008h 980 mV

009h 1020 mV

00Ah 1160 mV

00Bh 1270 mV

00Ch (default) 1370 mV

00Dh 1450 mV

00Eh 1530 mV

00Fh 1590 mV

11


The chosen configuration for the low-range amplitude is 0x29:

The chosen configuration for the high-range amplitude is 0x67:

The middle range (Average) is unchanged (0x49 by default EEPROM).

To obtain an EEPROM image that sets an amplitude other than the default, contact your Intel representative.

2.1.4.2 Signal Detect

82545/46

The signal detect pin on the GbE controller should be pulled up if no optical module exists to control link detection. When not using auto-negotiation, such as when the link partner does not support it, software should check for link before transmitting. This can be done by verifying that the MAC is synchronized by checking that bit 30 in the Receive Configuration Word Register [RXCW (00180h; R)] is set (1) and that there are no symbol errors by checking that bit 27 of RXCW is clear (0). If both partners support auto-negotiation this software check is not necessary as that process resolves the link process. However, in both cases link detect should be pulled up to 3.3 V dc.

Some devices might be capable of looking at the incoming stream of Rx symbols and determining link/synchronization status solely from the symbol content. However, when in internal SERDES mode, the Ethernet controller uses SIGDET as the primary indication of link up/down status.

Link status is a direct function of SIGDET regardless of whether HW auto-negotiation is enabled or not. Therefore, even if HW auto-negotiation is enabled, if SIGDET is not asserted, link up is not indicated.

In circumstances where SIGDET is connected to VCC and HW auto-negotiation is disabled, the Ethernet controller always reports that link is up.

82571/72

In a SERDES backplane application, Signal Detect is not used. SRDSA_SIG_DET and SRDSB_SIG_DET should be pulled up, either by floating them using the internal pull-ups or using external resistors to pull them up on the board.

631xESB/632xESB

Besides copper, the SerDes port can also work with fiber (1G transceiver). In this case, the LINK_0 and LINK_1 pins are used as SIG_DET (signal detect) signals.

When high, SIG_DET indicates that a signal is detected; when low, it indicates that no signal is detected.

For non-optical connection in backplane applications, these signals must be pulled up.

Average (mv) Minimum (mv) Maximum (mv)

852.7222846 752.344 966.406

Average (mv) Minimum (mv) Maximum (mv)

1175.490504 1024.22 1322.66


12

2.1.4.3 Signal Reception (All)

The receiver on the GbE controller must be able to receive any signal transmitted by a compliant transmitter through a compliant channel. For example, the GbE controller’s link partner’s transmitter must transmit signals that the GbE controller is capable of successfully receiving and deciphering through the backplane traces that meet the layout, length and other specifications as described in the PICMG 3.1 specification. Conversely, the link partner of the GbE controller must be capable of receiving and correctly understanding signals transmitted from the GbE controller. This requires verifying that the SERDES output and input of the GbE controller is compatible with its link partner's SERDES input and output respectively by carefully reviewing both parts' receiver and transmitter specifications.

Rigorous testing should then be performed on a prototype to verify that both parts and the signals transmitted minus losses are able to meet this receiver requirement. This testing should again be repeated on multiple finished product boards over all conditions that the finished product is subjected to such as supply voltage variations, ambient temperature variations, humidity, and etc. Failing to do this testing can result in failures of the product at a customer's site.

2.1.4.4 Pre-Emphasis

82545/46

Pre-emphasis control is available in the Extended PHY Specific Control 2 Register (Address: 26), bit 13 in GbE controllers. With the default setting of (0) the transmitted differential output amplitude includes 7% pre-emphasis value and can be increased to 15% by setting bit 13 to (1). The benefits of pre-emphasis are in high-speed data rate applications across longer (>30 inches) backplane lengths with multiple connectors (> 2). When a high-speed signal is traveling through a long PCB trace, the signal is degraded due the electrical properties of the PCB trace. The higher the frequency and the longer the PCB trace, the higher the degradation due to the bandwidth limitation of the PCB trace. When the data rate is higher than the bandwidth of the PCB trace, degradation of the signal occurs.

Although the simple resolution might seem to be to increase the amplitude of the signal, this does not address the problem of signal roll off or pattern dependent jitter and tends to increase noise and power consumption. The pre-emphasis technique has been proven to be an effective way to reduce such effects, especially in backplane designs, because it boosts the high frequency energy whenever there is a transition in the data which is when most problems occur.

Since high frequency components are attenuated more than low frequency components this results in a more equalized eye pattern at the receiver making it easier for the receiver to decipher the signal. A combination of both adjusting the output voltage level and the pre-emphasis bit setting is useful when problems arise with receiving transmitted information assuming that the design meets the layout requirements in this document. With improper layout it is quite likely that it will not be possible to overcome the problem without correcting the layout.

82571/72

By default, pre-emphasis is not enabled for the 82571/72. It can be enabled with the EEPROM image. When pre-emphasis is enabled, it is approximately 3.5dB. To obtain an EEPROM image that enables pre-emphasis for the 82571/72, contact your Intel representative.

631xESB/632xESB

13


Pre-emphasis is not supported.


14

3.0 SERDES Specifications

3.1 Transmit and Receive Specifications

Table 2. SERDES Specifications

3.2 Device ID Specifications

The Device ID must be set (forced) for SERDES-SERDES interface operation.

This ensures proper functionality with Intel drivers and the boot agent.

Parameter Value

Transmit Measured at TP-T

Data Rate 1000 Mb/s

Nominal Signal Speed 1250 MBd

Clock Tolerance +/-100 ppm

Differential Output Amplitude (peak-to-peak) 750 - 1350 mV (Adjustable)

Return Loss 15 dB Maximum (at TP-1)

Impedance 100 +/- 10% Ωs

Total Jitter (Random and Deterministic) <223 pS

Receive Measured at TP-R

Data Rate 1000 Mb/s

Nominal Signal Speed 1250 MBd

Clock Tolerance +/-100 ppm

Input Sensitivity 200 - 2000 mV

Differential Skew 175 pS Maximum

Differential Return Loss 15 dB Maximum

Common Mode Return Loss 6 dB Maximum (200 MHz to 2.5 GHz)

Impedance 100 +/- 10% Ωs

Fastest Rise Time 85 pS Maximum

Total Jitter (Random and Deterministic) <528 pS

Device Device ID (SERDES)

82545GM 1028h

82546GB 107Bh

82571EB (SERDES) 1060h

82572EI (SERDES) 107Fh

82571EB (Fiber) 105Fh

82572EI (Fiber) 107Eh

631xESB/632xESB (SERDES) 1098h

15



16

4.0 Testing for PICMG 3.1 Compliance

Thorough testing of the circuit is a fundamental requirement for all backplane designs. If resources are not available to perform these tests, outside contractors with these capabilities will be able to assist. While full PICMG 3.1 testing is optimal, the crucial tests for SERDES-SERDES backplane designs are listed here and in the PICMG 3.1 specification:

1. Insertion loss: Use a Vector Network Analyzer (VNA) to check insertion loss. It is also very useful to provide frequency domain measurements, measure impedance characteristics, transfer functions and various other losses in the channel.

2. Jitter: Jitter is tested as described in the PICMG specification using an eye pattern and a Signal Integrity Analyzer. Backplane jitter is specified in terms of both total jitter (TJ) and deterministic jitter (DJ):

a. TJ = sum of the peak-to-peak DJ and RJ (random jitter)

b. RJ = jitter generation from the several random processes

3. DJ = jitter from a variety of systematic effects (Duty Cycle Distortion, Inter Symbol Interference, periodic jitter).

The analyzers acquire signals and perform statistical analysis to separate DJ & RJ from TJ. Some scopes can also be used for eye diagram and jitter analysis. Such scopes provide the masks for Eye Diagrams.

4. Bit Error Rate (BER): The BER provides a good indication of real world network performance. BER testing should be performed with the length of backplane desired and several link partners. The test limit is 10-12 for any size of frame. BER is measured with a Bit Error Ratio Tester (BERT) available from several manufacturer of network test equipment. A BERT is used to create the “stressed eye” or worst-case packet waveform as seen by the receiver. Stressed eye includes both worst-case waveform amplitude and edge variation. BER can also be measured using the Intel® gigabit IEEE conformance test kit which includes the software, pattern files and suggested test setups to perform BER testing. Contact your Intel FAE to obtain this kit.

5. Return loss: Use a vector network analyzer to check return loss.

4.1 PICMG Test Setup and Specifications

1000BASE-BX is the PICMG electrical specification for transmission of 1000BASE-X encoded data over a 100-Ω backplane. The test points TP-T and TP-R are mandatory compliant points. All specifications are differential (see Figure 4).

Figure 4. SERDES Ethernet Electrical Environment and Test Points

Confirm that the input impedance at connection TP-1 in Figure 4 is 100 ± 30 Ω and at connection TP-1 is 100 ± 10 Ω and 100 ± 30 Ω at TP-T.

17


Transmitted Electrical Specification at TP-T

• The output driver is assumed to have output levels supporting the PIMG 3.1 test point (TP-T).

• The test point is the backplane side of the mated HM-ZD connector as shown in Figure 5.

Figure 5. Transmit Test Point at TP-T

Note: Capacitor and resistor tolerance is +/- 1%.

Transmitter Testing at TP-T

1. Differential output amplitude (peak-to-peak)

2. Rise/Fall time (20%-80%)

3. Differential skew

4. Normalized eye diagram mask at TP-T

5. Absolute eye diagram mask at TP-T

6. Transmitted total jitter and deterministic jitter

Note: Maximum drive amplitude of any PICMG 3.1 driver must not exceed 1600 mV peak-to-peak.

Table 3. Transmitter Specifications at TP-T

Test Parameter PICMG 3.1 Value

Differential Output Amplitude (peak-to-peak) 750 - 1350 mV

Rise Time (20% - 80%) 85 - 327 pS

Fall Time (20% - 80%) 85 - 327 pS

Differential Skew (Maximum) 25 pS


18

Table 4. Transmitted Eye Diagram Mask Specification at TP-T

Figure 6. Absolute Transmit Eye Diagram Mask at TP-T

Table 5. Transmitted Jitter Specifications at TP-T

Test Parameter PICMG 3.1 Eye Diagram Mask Requirement

Normalized Eye Diagram MaskNormalized Amplitude Normalized Time (UI)

0.2 - 0.8 X1 (0.14), X2 (0.34)

Absolute Eye Diagram MaskDifferential Amplitude (mV) Normalized Time (UI)

325 ~(-325) X1 (0.14), X2 (0.34)

PICMG 3.1 Transmit Jitter Budget

Parameter Total Jitter Deterministic Jitter

UI PS UI PS

Data TIE 0.279 223 0.14 112

19


Receiver Electrical Specifications at TP-R

The receiver is AC-coupled to the media through a receiver network. The receive network terminates the Tx/Rx connection by an equivalent impedance of 100 Ω, as specified in Figure 7.

Figure 7. Receiver Testing

1. Received differential skew (max) at TP-R

2. Received input sensitivity at TP-R

3. Received eye diagram mask at TP-R

4. Bit error rate (BER) testing at TP-R

5. Received total jitter and deterministic jitter

Table 6. Received Eye Diagram Mask Specification at TP-R

Data PLL TIE 0.279 223 0.14 112

Clock TIE 0.279 223 0.14 112

Clock PLL TIE 0.279 223 0.14 112

PICMG 3.1 Transmit Jitter Budget

PICMG 3.1 Receive Eye Diagram Mask Requirement

Backplane Eye Mask TestDifferential Amp (mV) Normalized Time (UI)

100~(-100) 0.3, 0.5, and 0.7


20

Figure 8. Received Eye Mask at TP-R After 25-Inch Backplane

Table 7. Received Input Specifications at TP-R

Anasoft® provides a complete signal integrity simulation package, linking mechanical drawings to electrical simulation packages to board layouts for 3-D field solver analysis.

PICMG 3.1 Receive Specifications

Sensitivity 200 to 1350 mV

Differential Skew 175 pS

Jitter Budget Total Jitter Differential Jitter

UI PS UI PS

Data TIE 0.66 528 0.4 320

Data PLL TIE 0.66 528 0.4 320

21



22

5.0 Component/Material Selection

There are a variety of applications that use GbE SERDES for its cost saving benefits. However, designers must carefully select components that provide the required performance. The GbE controllers were designed to be compliant with the PICMG 3.1 specifications and thus minimize risk of an improper backplane design. As a general rule, backplane designs should be kept as short as possible due to signal degradation in long traces, especially when using FR4 fabric for the PCB.

Other less “lossy” PCB materials, such as “Rogers”, are available but these can be more costly than FR4. When making design trade-offs to save costs, designers need to understand the impact on the performance and overall back plane design. This means careful attention to layout to maintain the 100 Ω differential impedance and testing thoroughly both on the prototype and the final production boards. Should the backplane exceed 30 inches there is much more likelihood that signal degradation may be too great to compensate, even with amplitude adjustment--especially on FR4 PCB material.

Also, using connectors of a lower quality than HM-Zd type can increase signal distortion. With shorter backplanes, there should be less trace signal degradation and the design might be able to afford slightly more signal degradation at the connector. In all cases, customers should perform thorough testing to ensure the critical components on multiple boards thorough all the conditions meet the requirements in their final application(s). The PICMG 3.1 specification is a valid reference for this compliance testing.

6.0 References

It is assumed that the designer is acquainted with high-speed design and board layout techniques. Documents that can provide additional information are:

• 82546 Gigabit Ethernet Controller Datasheet.

• 82546 Gigabit Ethernet Controller Design Guide.

• 82571EB/82572EI Gigabit Ethernet Controller Datasheet.

• 82571EB/82572EI Gigabit Ethernet Controller Design Guide.

• 631xESB/632xESB Gigabit Ethernet Controller Datasheet

• PICMG® 3.1 Ethernet/Fibre Channel Over PICMG 3.0 Specification.

23



24

7.0 Reference Schematics

This section contains SERDES reference schematics for the 82545/82546 & 82571/82572.

25


8/1

7/2

004

01

R

A

RE

V

SH

EE

TD

AT

E

DW

G. N

O.

SC

ALE

CSIZ

E

TIT

LE

AP

PR

OV

ALS

PB

A N

O.

DR

AW

N

CH

EC

KE

D

EN

GR

AP

VD

AP

VD

AP

VD

2

DA

TE

1

BCD

DA

TE

DE

SC

RIP

TIO

NRE

VIS

ION

S1

23

4

RE

V

56

78

D C B A

87

65

43

Rev. 1

.0

08/1

7/0

4PA

GE IN

DEX

-

1 - T

itle P

age

2 - B

lock

Dia

gra

m

3 - 8

2546G

B LA

N C

ontr

olle

r (1

/2)

4 - 8

2546G

B L

AN

Controlle

r (2/2

), E

EPRO

M, F

lash

5 - F

IBER

Lase

r co

nnect

ions

6 - V

olta

ge R

egula

tors

7 - S

ER

DES

Back

pla

ne C

onnect

ions

8 - D

ecouplin

g1

.0

82

54

6G

BR

EFER

EN

CE D

ES

IG

N(S

ER

DES

/FIB

ER

)

82546G

B R

efe

rence D

esig

n


26

8/1

7/2

004

02

R

A

RE

V

SH

EE

TD

AT

E

DW

G. N

O.

SC

ALE

CSIZ

E

TIT

LE

AP

PR

OV

ALS

PB

A N

O.

DR

AW

N

CH

EC

KE

D

EN

GR

AP

VD

AP

VD

AP

VD

2

DA

TE

1

BCD

DA

TE

DE

SC

RIP

TIO

NRE

VIS

ION

S1

23

4

RE

V

56

78

D C B A

87

65

43

PO

WE

R B

LO

CK

DIA

GR

AM

FU

NC

TIO

NA

L B

LO

CK

DIA

GR

AM

1.0

82546G

B R

efere

nce

Des

ign

PC

I /

PC

I-X

Inte

l 8

25

46

GB

:D

ua

l P

ort

LA

N C

on

tro

lle

rE

EP

RO

M

Fla

sh

Bo

ot

RO

M

Ad

dre

ss

/ D

ata

Ad

dre

ss

/ D

ata

Op

tic

al

Tra

ns

ce

ive

r "

B"

or S

erD

es

Ba

ck

pla

ne

Ch

an

ne

l "B

"

1.2

5 G

Bd

Op

tic

al

Tra

ns

ce

ive

r "

A"

or S

erD

es

Ba

ck

pla

ne

Ch

an

ne

l "

A"

1.2

5 G

Bd

PCI Address / Data

25

MH

z X

tal

Inte

l 8

25

46

GB

:D

ua

l P

ort

LA

N C

on

tro

lle

r

1.5

V

Re

gu

lato

r

2.5

V

Re

gu

lato

r

CT

RL

_2

5A

CT

RL

_1

5

27


64 528tib agi

G la uD

rellortnoC t enrehtEsp b

M0001/ 00 1/0 1

mm12 x

mm1 2

4 fo 1

mm1 2 x

mm12

64528t ibagi

G lauD

rellortnoC tenrehtEspb

M0001/001/01

4 fo 2

letnI

R

.g

nits

et e

cn

amr

ofn

oc

EE

EI rof

yln

o et

alu

po

P :et

oN

htiw yrav lli

w seulav pac daol lat sy rClatsyrc tsu jda p ukcats dna ez is dap

ediv o rp ot spac gnidaol eter csid.)

mpp 03 -/+( zH

M 000.52

0.1

ngi

se

D e

cn

eref

eR

BG

64

52

8

re

da

eH t

nio

P ts

eT

wei

V k

col

C

ro xu A_V 3.3 ot O IV tcen noC

eht ot gnidrocca BSV5 ICP.e su ni g nill ang is


28

8/1

7/2

004

04

R

A

RE

V

SH

EE

TD

AT

E

DW

G. N

O.

SC

ALE

CSIZ

E

TIT

LE

AP

PR

OV

ALS

PB

A N

O.

DR

AW

N

CH

EC

KE

D

EN

GR

AP

VD

AP

VD

AP

VD

2

DA

TE

1

BCD

DA

TE

DE

SC

RIP

TIO

NRE

VIS

ION

S1

23

4

RE

V

56

78

D C B A

87

65

43

82

54

6

Du

al

Gig

ab

it

Eth

ern

et C

on

tro

lle

r

10

/1

00

/1

00

0M

bp

s

21

mm

x 2

1m

m

3 o

f 4

4 o

f 4

21

mm

x 2

1m

m

82

54

6

Du

al

Gig

ab

it

Eth

ern

et C

on

tro

lle

r

10

/1

00

/1

00

0M

bp

s

93C

66

82546G

B R

efe

rence

Des

ign

Seri

al EEPR

OM

OP

TIO

NA

L: F

LA

SH

No

te:

Do

No

t S

tuff

un

less r

eq

uir

ed

by E

EP

RO

M v

en

do

r

1.0

Pla

ce c

aps c

lose

to p

art

in p

lane

No

te:

Th

is c

on

ne

ctio

n a

llow

s c

om

pa

tib

ility

with

fla

sh

pa

rts h

avin

g g

rea

ter

me

mo

ry c

ap

acity.

29


8/1

7/2

004

05

R

A

RE

V

SH

EE

TD

AT

E

DW

G. N

O.

SC

ALE

CSIZ

E

TIT

LE

AP

PR

OV

ALS

PB

A N

O.

DR

AW

N

CH

EC

KE

D

EN

GR

AP

VD

AP

VD

AP

VD

2

DA

TE

1

BCD

DA

TE

DE

SC

RIP

TIO

NRE

VIS

ION

S1

23

4

RE

V

56

78

D C B A

87

65

43

LC

- O

ptical

Tra

nsceiv

er

LC

- O

ptical

Tra

nsceiv

er

Insta

ll t

he

se

co

mp

on

en

ts o

nly

if

usin

g t

he 8

25

46

wit

h a

fib

er m

odu

le.

Fo

r S

erD

es b

ackp

lan

e m

od

e -

See S

erD

es b

ackp

lan

e o

ptio

n.

OPTIO

N:

FIBER

MO

DU

LE C

ON

NECTIO

N

No

te

:

Re

fe

re

nce

op

tic

al m

od

ule

s c

on

ta

in

AC

co

up

lin

g c

ap

s o

n S

erD

es P

ins.

No

te

:

Re

fe

re

nce

op

tic

al

mo

du

les c

on

ta

in

AC

co

up

lin

g c

ap

s o

n S

erD

es P

ins.

1.0

82546G

B R

efe

rence D

esig

n

TO

PO

RT B

TO

PO

RT A

No

te:

Stu

ff f

or

fib

er

mo

de

on

ly -

em

pty

fo

r b

ackp

lan

e m

od

e.


30

8/1

7/2

004

06

R

A

RE

V

SH

EE

TD

AT

E

DW

G. N

O.

SC

ALE

CSIZ

E

TIT

LE

AP

PR

OV

ALS

PB

A N

O.

DR

AW

N

CH

EC

KE

D

EN

GR

AP

VD

AP

VD

AP

VD

2

DA

TE

1

BCD

DA

TE

DE

SC

RIP

TIO

NRE

VIS

ION

S1

23

4

RE

V

56

78

D C B A

87

65

43

1.0

82546G

B R

efere

nce D

esig

n

No

te:

Stu

ff f

or

Ba

ckp

lan

e m

od

e o

nly

- e

mp

ty f

or

Fib

er

mo

de

.

OPTIO

N:

SER

DES B

AC

KP

LA

NE C

ON

NECTIO

N SER

DES

PO

RT B

SER

DES

PO

RT A

Backp

lan

e C

on

necto

r(G

en

eri

c)

Insta

ll t

he

se

co

mp

on

en

ts o

nly

if

usin

g t

he 8

25

46

wit

h a

backp

lan

e c

on

necto

r

For F

IB

ER

mod

e -

See f

iber o

ptio

n.

31


8/1

7/2

004

07

R

A

RE

V

SH

EE

TD

AT

E

DW

G. N

O.

SC

ALE

CSIZ

E

TIT

LE

AP

PR

OV

ALS

PB

A N

O.

DR

AW

N

CH

EC

KE

D

EN

GR

AP

VD

AP

VD

AP

VD

2

DA

TE

1

BCD

DA

TE

DE

SC

RIP

TIO

NRE

VIS

ION

S1

23

4

RE

V

56

78

D C B A

87

65

43

1.0

82546G

B R

efere

nce

Des

ign

PO

WE

R R

EG

UL

AT

IO

N

1.5

V I

nte

rg

ra

te

d L

ine

ar R

eg

ula

to

r

2.5

V I

nte

rg

ra

te

d L

ine

ar R

eg

ula

to

r

RE

SE

T S

up

ervis

or

Op

tio

na

l C

ap

Op

tio

na

l C

ap


32

8/1

7/2

004

08

R

A

RE

V

SH

EE

TD

AT

E

DW

G. N

O.

SC

ALE

CSIZ

E

TIT

LE

AP

PR

OV

ALS

PB

A N

O.

DR

AW

N

CH

EC

KE

D

EN

GR

AP

VD

AP

VD

AP

VD

2

DA

TE

1

BCD

DA

TE

DE

SC

RIP

TIO

NRE

VIS

ION

S1

23

4

RE

V

56

78

D C B A

87

65

43

Op

tio

na

l C

ap

acito

r site

s w

ill p

rovid

e b

ett

er

de

co

up

ling

fo

r th

e d

esig

n.

Op

tio

na

l C

ap

s

Op

tio

na

l C

ap

s

82546G

B R

efere

nce

Des

ign 1

.0

Byp

ass C

ap

s f

or

LA

N c

on

tro

ller

- P

lace

Clo

se

To

Th

e D

evic

e I

n P

lan

e

DECO

UPLIN

G

Op

tio

na

l C

ap

s

33


DN

P -

Do

No

t P

op

ula

te s

ym

bo

l.T

his

is a

co

mp

on

en

t stu

ffin

g o

pti

on

fo

r an

op

tio

nal

featu

re,

sp

ecia

l d

eb

ug

or

testi

ng

pu

rpo

ses.

82571E

B R

efe

ren

ce D

esig

n -

SE

RD

ES

.

PA

GE I

ND

EX

1

- T

itle

Page

2

- F

unctional Blo

cks

3

- 8

2571EB M

DI,

SERD

ES,

EEPRO

M,

Fla

sh &

SM

Bus

inte

rfaces.

4

- 8

2571EB V

CC,

VD

D a

nd V

SS C

onnections.

5

- 8

2571EB P

CI

Expre

ss

JTA

G a

nd o

ther

inte

rfaces.

6

- F

LA

SH

and E

Epro

m d

evic

es.

7.

- S

ERD

ES L

ase

r connecti

ons.

8.

- S

ERD

ES b

ackpla

ne c

onnecto

r

For

pow

er

deliv

ery

solu

tions

refe

r to

the

"82571EB/8

2572EI

Gig

abit

Eth

ern

et

Contr

olle

r D

esi

gn G

uid

e"

Applic

ati

on N

ote

(A

P-4

47)

Rev. 6

.0

11/2

005

82

57

1E

BR

EFE

RE

NC

E D

ES

IGN

(SE

RD

ES

/FIB

ER

)


34

8257

1EB

Ref

. Des

ign

2

Fun

ctio

na

l Blo

ck

Op

tio

n A

SE

RD

ES

Las

er.

Op

tio

n B

SE

RD

ES

Bac

kpla

ne.

SE

RD

ES

Port

B

Port

A

SPI

FLA

SH

SPI

EE

PRO

M

Pag

es 7

-8P

ages

3,4

,5

Not

sho

wn

for

SE

RD

ES

Des

ign

Pag

e 6

Pag

e 5

JTA

G

CO

PPE

R P

HY

8257

1EB

LA

NC

ON

TR

OL

LE

R

Pag

e 6

Pag

es 3

SM

Bus

/ FM

L

Pag

es 5

PCI-E

xpre

ss -

x4

35


SDP I/F

LEDs PORT A

SMBus

Serial FLASHEEPromEthernet Port A

SERDES PORTS A & B

1m

m P

itch

16

mm

x 1

6m

m B

GA

82

57

1E

B

PC

I -

E1

0/1

00

/10

00

Mb

ps

Eth

ern

et C

on

tro

ller

1 O

F 3

Ethernet Port BLEDs PORT B

Ref

ere

to d

esig

n gu

ide

for

SMBu

s pu

ll-up

val

ues.

Mak

e lo

ad c

aps

5% C

OG

.Ca

n be

040

2, 0

603

or08

05.

8257

1EB

Ref

. Des

ign

Crys

tal l

oad

cap

valu

es w

ill v

ary

with

pad

size

and

sta

ckup

adj

ust

crys

tal

disc

rete

load

ing

caps

to

prov

ide

25.0

00 M

Hz

(+/-

30

ppm

).

Ro

ute

as

dif

fere

nti

alp

airs

to

tes

t p

oin

tsp

lace

d n

ear

the

825

71E

B.

TO S

ER

DE

SP

OR

TS A

& B

3In

stal

l on

ly f

or

spec

ial d

ebu

g o

r te

stin

g p

urp

ose

s

8257

1EB

MD

I, S

ERD

ES, F

LASH

AND

EEP

RO

MIN

TER

FACE

S

No

te:

Pin

R11

C

on

nec

tio

nD

epen

ds

on

m

anag

abil

ity

mo

de

des

ired

-

Co

nsu

lt D

esig

nG

uid

e.

Th

e P

HY

is p

ow

ered

do

wn

wh

en in

SE

RD

ES

mo

de.

Th

eref

ore

, th

ese

pin

s d

o n

ot

req

uir

e p

ull-

up

o

r p

ull-

do

wn

res

isto

rs.

Th

e P

HY

is p

ow

ered

do

wn

wh

en in

SE

RD

ES

mo

de.

Th

eref

ore

, th

ese

pin

s d

o n

ot

req

uir

e p

ull

-up

o

r p

ull-

do

wn

res

isto

rs.


36

82

57

1E

BP

CI-

E1

0/1

00

/10

00

Mb

ps

Eth

ern

et C

on

tro

ller

1m

m P

itch

16

mm

x 1

6m

m B

GA

2 o

f 3

VSS Pins

VDD/VCC Pins

4

8257

1EB

VCC

, VD

D &

VSS

CO

NNEC

TIO

NS

Op

tio

nal

: C

on

nec

t to

sys

tem

th

erm

alm

anag

emen

t co

ntr

olle

r.

8257

1EB

Ref

. Des

ign

NO

TE

: P

ow

er d

eliv

ery

for

8257

1EB

.T

he

1.1V

an

d 1

.8V

su

pp

lies

mu

st

be

sep

arat

e su

pp

lies

for

the

Eth

ern

et C

on

tro

ller

on

ly.

Co

nsu

lt D

esig

n G

uid

e.

37


3 O

F 3

82

57

1E

B

PC

I -

E1

0/1

00

/10

00

Mb

ps

Eth

ern

et C

on

tro

ller

16

mm

x 1

6m

m B

GA

1m

m P

itch

PCI Express RECEIVE

PCI Express TRANSMITJTAG

Pla

ce c

aps

wit

hin

25

0 m

ils o

f th

e P

CI-

E T

ran

smit

ters

.

Pla

tfo

rm S

MB

us

pu

ll-u

p

dic

tate

s s

tuff

ing

op

tio

ns

for

this

pu

ll-u

p r

esis

tor.

Co

nn

ect

to G

P p

ort

pin

so

n S

up

er

IO t

hat

ret

ain

va

lue d

uri

ng

res

et.

No

rmal

ly n

ot

con

nect

ed.

See

des

ign

gu

ide

for

det

ails

.

If u

sin

g s

yste

m le

vel

JTA

G, d

o n

ot

po

pu

late

thes

e re

sist

ors

.

B0

and

Su

bse

qu

ent

Ste

pp

ing

s O

nly

PC

I-E

X R

eset

Gen

erat

ed b

yP

latf

orm

Co

nn

ect

to G

P P

ort

on

Su

per

I/O

th

at r

etai

ns

its

valu

e d

uri

ng

res

et.

Inst

all

on

ly f

or

spec

ial

deb

ug

or

test

ing

pu

rpo

ses

Rec

eiver

inp

uts

sh

ou

ld b

eA

C c

ou

ple

d f

rom

tra

nsm

itte

rso

urc

e (n

ot

sh

ow

n)

per

PC

IEX

sp

ec.

Ro

ute

as

dif

fere

nti

al p

airs

.T

race

len

gth

s sh

ou

ld b

eeq

ual

wit

hin

0.0

05".

Fo

ra

pai

r.

Ro

ute

as

dif

fere

nti

al p

air

s.T

race

len

gth

s s

ho

uld

be

equ

al w

ith

in 0

.005

". F

or

a p

air

in e

ach

seg

men

t.

5

PC

I Exp

ress

Tra

nsm

itte

rd

iffe

ren

tial

pair

s fr

om

th

esy

stem

bo

ard

.

PC

I Exp

ress

Rec

eive

r d

iffe

ren

tial

pai

rs t

o t

he

syst

em b

oar

d.

8257

1EB

PCI

EXPR

ESS,

JTA

GA

ND S

MBU

S IN

TER

FACE

S

Ro

ute

to

ICH

wak

e p

in

8257

1EB

Ref

. Des

ign

See

Des

ign

Gu

ide

for

FL

B f

un

ctio

nal

ity.

If t

he

8257

1EB

is

tosu

pp

ort

au

x w

ake

R50

m

ust

be

inst

alle

d.

LA

N P

OW

ER

GO

OD

:S

ee D

esig

n G

uid

e.D

o n

ot

con

nec

t an

yth

ing

to

th

is p

in.

Th

ese

pin

s ar

e re

serv

ed.

Pu

ll-u

ps

are

req

uir

ed

as

thes

e p

ins

def

ine

test

mo

des

in o

ther

sta

tes.

Th

ese

can

be

sin

gle

04

02 p

art

per

pin

or

a R

pac

k. D

o n

ot

use

a

sin

gle

res

isto

r fo

r al

l pin

s.


38

Byp

ass

Cap

s fo

r 1.

1V C

OR

EV

DD

Pla

ce C

lose

To

LAN

sili

con

Byp

ass

Cap

s fo

r 1.

8V V

DD

Pla

ce C

lose

To

LAN

sili

con

DEC

OUP

LING

Fla

sh o

ptio

nal

SP

I E

EP

RO

M

6

Se

ria

l FL

AS

H

FLA

SH A

ND E

EPR

OM

8257

1EB

Ref

. Des

ign

Opt

ion

al c

aps:

Pla

ce c

lose

to

silic

on

as p

ossi

ble

OR

pla

ce o

n se

cond

ary

side

dir

ectl

y o

n th

e B

GA

po

wer

pin

s.D

NP

unl

ess

need

ed.

Op

tiona

l cap

s:P

lace

clo

se to

sili

con

as

pos

sib

leO

R p

lace

on

sec

onda

ry s

ide

dire

ctly

on

the

BG

A p

ower

pin

s.D

NP

unl

ess

need

ed. O

ptio

nal c

aps:

Pla

ce c

lose

to

sili

con

as

poss

ible

OR

pla

ce o

n s

econ

dary

sid

edi

rect

ly o

n th

e B

GA

pow

er p

ins.

DN

P u

nle

ss n

eede

d.

39


LC -

Opt

ical

T

rans

ceiv

er

LC -

Opt

ical

T

rans

ceiv

er

SE

RD

ES

PO

RT

A

SE

RD

ES

PO

RT

B

Pla

ce c

lose

toT

rans

ceiv

er

Pla

ce fi

lter

as c

lose

as

pos

sib

le to

lase

r.P

lace

sm

alle

st v

alu

ed c

aps

clos

est

to la

ser

VC

C.

Pla

ce c

lose

toT

rans

ceiv

er

OPT

ION

A:

SER

DES

/LA

SER

CO

NNEC

TIO

N 7

Pla

ce f

ilte

r as

clo

se a

s po

ssib

le t

o la

ser.

Pla

ce s

mal

lest

val

ued

ca

ps c

lose

st t

o la

ser

VC

C.

8257

1EB

Ref

. Des

ign


40

8

Bac

kpla

ne

Co

nn

ecto

r(G

ener

ic)

SER

DES

POR

T A

SER

DES

POR

T B

OPT

ION

B: S

ERD

ES B

ACK

PLA

NE C

ONN

ECTI

ON

8257

1EB

Ref

. Des

ign

41


DN

P -

Do

No

t P

op

ula

te s

ym

bo

l.T

his

is a

co

mp

on

en

t stu

ffin

g o

pti

on

fo

r an

op

tio

nal

featu

re,

sp

ecia

l d

eb

ug

or

testi

ng

pu

rpo

ses.

82572E

I R

efe

ren

ce D

esig

n -

SE

RD

ES

Rev. 3

.0

11/2

005

82

57

2E

IR

EFE

RE

NC

E D

ES

IGN

(SE

RD

ES

/FIB

ER

)

PA

GE I

ND

EX

1

- T

itle

Page

2

- F

uncti

onal Blo

cks

3

- 8

2572EI

MD

I, S

ERD

ES,

EEPRO

M,

Fla

sh &

SM

Bus

inte

rfaces.

4

- 8

2572EI

VCC,

VD

D a

nd

VSS C

onnecti

ons.

5

- 8

2572EI

PCI

Expre

ss

JTA

G a

nd o

ther

inte

rfaces.

6

- F

LA

SH

and E

Ep

rom

devic

es.

7.

- S

ERD

ES L

ase

r connecti

ons.

8.

- S

ERD

ES b

ackp

lane c

onnecto

r

For

pow

er

deliv

ery

solu

tions

refe

r to

the

"82571EB/8

2572EI

Gig

abit E

thern

et

Con

trolle

r D

esign G

uid

e"

Applic

ati

on N

ote

(A

P-4

47)


42

Page

s 3

Pag

es 5

SM

Bus

/ FM

L

PC

I-Exp

ress

- x

4

Page

6

Op

tio

n A

SE

RD

ES

- F

IBE

RO

pti

on

B S

ER

DE

S -

BA

CK

PL

AN

E

SE

RD

ES

Port

A Pag

es 7

- 8

Fun

ctio

na

l Blo

ck

8257

2EI

LA

NC

ON

TR

OL

LE

R

CO

PPE

R A

FE

Page

6

Not

show

n fo

r S

ER

DE

S D

esi

gn

Page

s 3,4

,5

SPI

EE

PR

OM

SPI

FLA

SH

JTA

G Pag

e 5

2

8257

2EI R

ef. D

esig

n

43


1 O

F 3

82

57

2E

I

PC

I -

E1

0/1

00

/10

00

Mb

ps

Eth

ern

et

Co

ntr

oll

er

16

mm

x 1

6m

m B

GA

1m

m P

itch

SERDES PORTS A

Ethernet Port A EEProm Serial FLASH

SMBus

LEDs PORT A

SDP I/F

Th

e P

HY

is

po

were

d d

ow

nw

hen

in

SE

RD

ES

mo

de.

Th

eref

ore

, th

ese

pin

s d

o n

ot

req

uir

e p

ull

-up

o

r p

ull-d

ow

n r

esi

sto

rs.

Th

ese

pin

s a

re d

isab

led

an

d d

o n

ot

req

uir

e p

ull

-up

o

r p

ull-d

ow

n r

esi

sto

rs.

Th

ese

pin

s are

dis

able

d

and

do

no

t re

qu

ire

pu

ll-u

p

or

pu

ll-d

ow

n r

esis

tors

.

Th

ese

pin

s ar

e d

isb

aled

a

nd

do

no

t re

qu

ire

pu

ll-u

p

or

pu

ll-d

ow

n r

esis

tors

.

No

te:

Pin

R11

C

on

nec

tio

nD

epen

ds

on

m

anag

ab

ilit

ym

od

e d

esir

ed -

C

on

sult

Des

ign

Gu

ide.

82

57

2EI

MD

I, S

ERD

ES,

FLA

SH A

ND

EEP

RO

MIN

TER

FACE

S

Insta

ll o

nly

fo

r sp

ecia

l d

ebu

g o

r te

stin

g p

urp

ose

s3

8257

2EI R

ef. D

esig

n

TO

SE

RD

ES

LA

NP

OR

T A

Ro

ute

as

dif

fere

nti

al

pair

s to

tes

t p

oin

tsp

lace

d n

ear

the

825

71E

B.

Crys

tal l

oad

cap

valu

es w

ill v

ary

with

pad

size

and

sta

ckup

adj

ust

crys

tal

disc

rete

load

ing

caps

to

prov

ide

25.0

00 M

Hz

(+/-

30

ppm

)

Mak

e lo

ad c

aps

5% C

OG

.Ca

n be

040

2, 0

603

or08

05.

Ref

ere

to d

esig

n gu

ide

for

SMBu

s pu

ll-up

val

ues.


44

VDD/VCC Pins

VSS Pins

2 o

f 3

16

mm

x 1

6m

m B

GA

1m

m P

itch

82

57

2E

I

PC

I-E

10

/10

0/1

00

0 M

bp

sE

the

rne

t C

on

tro

lle

r

4

8257

2EI R

ef. D

esig

n

VC

C,

VD

D &

VS

S C

ON

NEC

TIO

NS

Op

tio

nal

: C

on

nec

t to

sys

tem

th

erm

alm

anag

emen

t co

ntr

oller

.

NO

TE

: P

ow

er d

eliv

ery f

or

8257

2EI.

Th

e 1

.1V

an

d 1

.8V

su

pp

lies

mu

st

be s

epara

te s

up

plies

fo

r th

e E

ther

net

Co

ntr

oller

on

ly.

Co

nsu

lt D

esig

n G

uid

e.

45


3 O

F 3

82

57

2E

I

PC

I -

E1

0/1

00

/1

00

0 M

bp

sE

the

rnet

Co

ntr

oll

er

16

mm

x 1

6m

m B

GA

1m

m P

itch

PCI Express RECEIVE

PCI Express TRANSMITJTAG

Pla

ce c

ap

s w

ith

in

250 m

ils o

f th

e

PC

I-E

Tra

nsm

itte

rs.

Pla

tfo

rm S

MB

us p

ull-u

p

dic

tate

s s

tuff

ing

op

tio

ns

for

this

pu

ll-u

p r

es

isto

r.

LA

N P

OW

ER

GO

OD

:S

ee D

esig

n G

uid

e.

Do

no

t co

nn

ect

an

yth

ing

to

th

is p

in.

PC

I-E

X R

eset

Gen

era

ted

by

Pla

tfo

rm

Co

nn

ect

to G

P P

ort

on

Su

per

I/O

th

at r

etai

ns

its

valu

e d

uri

ng

res

et.

Insta

ll o

nly

fo

r sp

ecia

l d

eb

ug

or

testi

ng

pu

rpo

ses

Receiv

er

inp

uts

sh

ou

ld b

eA

C c

ou

ple

d f

rom

tra

nm

itte

rso

urc

e (

no

t sh

ow

n)

per

PC

IEX

sp

ec.

82572E

I R

ef.

Desig

n

Ro

ute

as d

iffe

ren

tial

pair

s.

Tra

ce l

en

gth

s s

ho

uld

be

eq

ual w

ith

in 0

.005".

Fo

ra p

air

.

Ro

ute

as d

iffe

ren

tial

pair

s.

Tra

ce l

en

gth

s s

ho

uld

be

eq

ual w

ith

in 0

.005".

Fo

ra p

air

in

each

seg

men

t.

5

PC

I E

xp

ress T

ran

sm

itte

rd

iffe

ren

tial p

air

s f

rom

th

esyste

m b

oard

.

PC

I E

xp

ress R

eceiv

er

dif

fere

nti

al

pair

s t

o t

he s

yste

m b

oard

.

82

57

2EI

PC

I EX

PR

ESS

, JT

AG

AN

D S

MB

US

IN

TER

FAC

ES

Co

nn

ec

t to

GP

po

rt p

ins

on

Su

per

IO t

ha

t re

tain

valu

e d

uri

ng

res

et.

Ro

ute

to

ICH

wak

e in

pu

t

See D

esig

n G

uid

e

for

FL

B f

un

cti

on

ali

ty.

If t

he 8

2572E

I is

to

su

pp

ort

au

x w

ake R

50

mu

st

be in

sta

lled

.

If u

sin

g s

yste

m le

vel

JTA

G, d

o n

ot

po

pu

late

thes

e re

sist

ors

.

Th

ese p

ins a

re r

eserv

ed

.P

ull

-up

s a

re r

eq

uir

ed

as

these p

ins d

efi

ne t

est

mo

des i

n o

ther

sta

tes.

Th

ese c

an

be s

ing

le

0402 p

art

per

pin

or

a

Rp

ack. D

o n

ot

use a

sin

gle

resis

tor

for

all p

ins.


46

Byp

ass

Cap

s fo

r 1.

1V C

OR

EV

DD

Pla

ce C

lose

To

LAN

sili

con

Byp

ass

Cap

s fo

r 1.

8V V

DD

Pla

ce C

lose

To

LAN

sili

con

DEC

OUP

LING

Flas

h o

ptio

nal

SP

I E

EP

RO

M

8257

2EI R

ef. D

esig

n6

Se

ria

l FL

AS

H

FLA

SH A

ND E

EPR

OM

Opt

ion

al c

aps:

Pla

ce c

lose

to

silic

on

as p

ossi

ble

OR

pla

ce o

n se

cond

ary

side

dir

ectl

y o

n th

e B

GA

po

wer

pin

s.D

NP

un

less

nee

ded

.

Opt

iona

l cap

s:P

lace

clo

se t

o si

lico

n a

s po

ssib

leO

R p

lace

on

sec

on

dary

sid

ed

irec

tly

on th

e B

GA

po

wer

pin

s.D

NP

un

less

nee

ded

. Opt

ion

al c

aps:

Pla

ce c

lose

to

silic

on

as p

oss

ible

OR

pla

ce o

n se

cond

ary

side

dir

ectl

y o

n th

e B

GA

po

wer

pin

s.D

NP

un

less

nee

ded

.

47


LC

- O

ptic

al

Tra

nsce

iver

LC

- O

ptic

al

Tra

nsce

iver

SE

RD

ES

PO

RT

A

SE

RD

ES

PO

RT

B

Pla

ce c

lose

to

Tra

nsc

eiv

er

Pla

ce filt

er

as

close

as

poss

ible

to la

ser.

Pla

ce s

ma

llest

va

lued

cap

s cl

ose

st to la

ser

VC

C.

Pla

ce c

lose

to

Tra

nsc

eiv

er

OP

TIO

N A

: S

ERD

ES/

LAS

ER C

ON

NEC

TIO

N 7

Pla

ce f

ilte

r as

clo

se a

s po

ssib

le t

o la

ser.

Pla

ce s

malle

st v

alu

ed c

aps

close

st t

o la

ser

VC

C.

8257

1EB

Ref

. Des

ign


48

OPT

ION

B: S

ERD

ES B

ACK

PLA

NE C

ONN

ECTI

ON

8

Bac

kpla

ne

Co

nn

ecto

r(G

ener

ic)

SER

DES

POR

T A