designing a fast and reliable memory with memristor technology manjunath shevgoor, rajeev...
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Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Manjunath Shevgoor, Rajeev Balasubramonian, Naveen Muralimanohar
University of Utah, HP Labs
Designing a Fast and Reliable Memory with Memristor Technology 2
Background
Store data in the form of resistance
Metal oxide sandwiched between two electrodes
Inherently non conducting Creation of conductive
Filaments of oxygen vacancies reduces resistance Source: Cong Xu et al., Modeling and Design Analysis of
3D Vertical Resistive Memory - A Low Cost Cross-Point Architecture, ASPDAC 2014
Designing a Fast and Reliable Memory with Memristor Technology 3
Voltage Dependent Resistance
R(V/p) and R(V ) are the equivalent resistance of the cell biased at V/p and V
Kr is the non-linearity. Eg: if Kr=20, resistance increases 10x when voltage is halved
Resistance decreases with increasing voltage
The resistance of a ReRAM cell is not constant but varies with the applied voltage
Kr(p, V ) = p * R(V/p)/R(V )
Designing a Fast and Reliable Memory with Memristor Technology
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BitLine
Word
Line
DRAM Cell
BitLine
Word
Line
PCM Cell
Word
Line
BitLine
Memristor Cell
Cell Size of 4F2
Cross Point Structure
Designing a Fast and Reliable Memory with Memristor Technology
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Because of non-linearity, it is possible to select a cell without an access
transistor.
Arrays can be layered vertically without resorting to 3D stacking.
Mem-
ristor
Selecto
r
Driver Transistors
Selected Cell
Memristor Cell
Reading and Writing
Designing a Fast and Reliable Memory with Memristor Technology
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Driver Transistors
Half Selected Cells
Selected Cell
Sneak Current
0VVdd/2Vdd/2Vdd/2
Vdd/2
Vdd/2Vdd/2
Vdd
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RW RW RW
RW RW RW
RW RW RW
RW RW RW
0
V/2
V/2 V/2
V
Bit Lines
Word LinesVW1 VW2 VWN
VWN1
VWNM
Bit Line Mux
Bit line and word line resistances eat into the cell Voltage
Designing a Fast and Reliable Memory with Memristor Technology 8
Effects of Ileak
Effects of Ileak
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Decreases Voltage at selected cell Increases Write Latency Can cause Write Failure
Distorts bit line current Increases read complexity Decreases read margin
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Sneak path currents can distort Iread
Vread
0
Iread
Ileak
Ileak
Ileak
Vread/2
Vread/2
Vread/2
Vread/2 Vread/2 Vread/2
Designing a Fast and Reliable Memory with Memristor Technology 11
Step 1: Read background current (Ileak)
Vread/2
0
Ileak
Ileak
Ileak
Ileak
Vread/2
Vread/2
Vread/2
Vread/2 Vread/2 Vread/2
Designing a Fast and Reliable Memory with Memristor Technology 12
Step 2: Read total Vread current (Iread)
Vread
0
Iread
Ileak
Ileak
Ileak
Vread/2
Vread/2
Vread/2
Vread/2 Vread/2 Vread/2
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State of selected cell determines
Iread ~ Ileak
tBG_READ tREAD
Read Latency
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Proposal 1: Re-use value in sample and hold circuit
Vread
Vread/2
Vread/2
Vread/2
Vread/2 Vread/2Vread/2
Vr
Pacc
Pprech
S1Sensing Circuit
S2
Sample and HoldSneak Current
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Reusing Sneak Current Read
Snea
k Cu
rren
t uA
Columns
Row
s
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Re-Use Sneak Current Reading for the same Column
tBG_READ tREAD
Read Latency1
tREAD
Read Latency2
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Impact of Cell Location
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Bit Line Mux
Word Line
Drivers
Longer write latencies Increased error rates
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64 Byte Cache line
Array 1
Array 2
Array 3
Array 512
Bit 1 Bit 2 Bit 3 Bit 512
Default Mapping Leads to some lines with high error rate
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Proposal 2: Stagger the array mapping
Cacheline 1 Cacheline 2 Cacheline 3 Cacheline 4
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3Nth bit in cacheline
Array 0
Array 1
Array 2
Array 3
Default Mapping
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
ProposedMapping
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Proposal 2: Impact on Write Latency
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3Nth bit in cacheline
Array 0
Array 1
Array 2
Array 3
Default Mapping
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2ProposedMapping
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Proposal 3: Compress to reduce write latency
64 Byte Cache line
Array 1
Array 2
Array 3
Array 512
Bit 1 Bit 2 Bit 3 Bit 512
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
Proposed MappingWith 50%
Compression
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Conclusions
With great density come a few challenges Sneak Currents limit array size, complicate reads, and delay
writes Affect reliability
Background current can be reused Reliability can be improved at the cost of write latency Compression can reduce write latency 13% performance improvement 30X reduction in multi bit error probability Work in progress
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Thank You