designcon 2013 - si and emi impact of ac coupling...
TRANSCRIPT
DesignCon 2013
SI and EMI Impact of AC
Coupling Capacitors on 25Gbps+
Systems
Xin Wu, Molex Inc. [email protected] Casey Morrison, Texas Instruments Inc. [email protected] Bhavesh Patel, Dell Corp. [email protected] Raghav Nallan Chakravarthi, Molex Inc. [email protected] Peerouz Amleshi, Molex Inc. [email protected]
Abstract
Moving forward to systems with data rates of 25Gbps and beyond, the small impairments in a high-speed channel may no longer be ignored as they can contribute significantly to impedance mismatch, crosstalk, mode conversion, and other adverse effects. From a system perspective, these effects may increase the risk of system failure due to signal
integrity, radiated EMI or both. AC coupling capacitors, historically considered to have little impact on system failure, but have been the focus of increasing concern by the industry, especially when migrating from 10Gbps to 25Gbps and beyond.
The purpose of this work is to identify critical system signal integrity and radiated EMI impact factors when implementing AC coupling capacitors in a 25Gbps+ system through 3D modeling, channel simulation and measurement. By identifying these factors they can be more easily managed through a carefully-selected AC coupling implementation, one
which preserves the system SI and EMI goals.
Authors Biography
Xin Wu is a senior electrical engineer in the Connector Product Division at Molex Inc.
His industry experiences include electromagnetic simulation/EDA software development, EMC/EMI engineering, Signal Integrity analysis, RF system/Antenna engineering, and wireless networking technology development. At Molex, his focus is on the high-speed interconnects signal integrity engineering and high-speed interconnects EMC/EMI. He
received his Ph.D in the area of computational electromagnetics from the University of Maryland, College Park. He also received his entrepreneurial training certificate from Haas Business School, UC Berkeley.
Casey Morrison is an applications engineer in the Data Path Solutions product line at Texas Instruments Inc. His primary role at TI for the past five years has been architectural definition, system simulation, and test of high-speed SerDes and signal conditioning products from 2.5Gbps to 25+Gbps. His industry experience is in the area of high-speed serial communications and signal integrity spanning numerous interface
standards including Ethernet, Fibrechannel, SAS/SATA, PCI-Express, SRIO, CPRI, and others. He received his Masters of Science in Electrical Engineering from the University of Florida.
Bhavesh Patel is a Principal System Engineer at Dell Corp. He has over 17 years of industry experience in hardware, signal integrity and system design at various companies in the field of modems, telecom and servers. Over the last 8 years at Dell, he has worked on different blade server designs as signal integrity & system engineer. His main focus is
on backplane architecture, design and simulations and also evaluating various PHY, equalizers for backplane applications. He holds BS degree in Electronic Engineering from Bangalore, India.
Raghav Nallan is an electrical project engineer in the Connector Produce Division at Molex Inc. At Molex, his focus is on the high-speed IO interconnects, signal integrity design, analysis and measurement characterization. His industry experience has been in
system level, chip level and connector level signal integrity. He received his M.S in EE from University of South Carolina, Columbia.
Peerouz Amleshi is an electrical engineering director in Connector Product Division at Molex Inc. His team’s primary focus is in design and characterization of next generation high-speed backplane components and systems. In his previous position as Senior Optical Engineer at Molex Fiber Optics Division, he was involved in design and characterization
of planar polymeric and dielectric optical integrated devices and interconnects. Dr. Amleshi holds eleven issued and two pending US patents in the fields of optical and electrical interconnects. He received his Ph.D. in the area of electromagnetics within the Electrical Engineering discipline from the University of Illinois at Chicago.
1. Introduction
As we move from 10Gbps per differential pair to 25Gbps and beyond, channel effects, which were insignificant enough to ignore, now become important. There are several channel components that can degrade the transmission quality starting from the Transmitter in a SerDes to the Receiver, but most of these impairments have been studied
well and quantified in published literature. There are solutions available to mitigate some of these impairments like skin effect, dielectric loss, and impedance mismatch [1]-[4]. Some of these solutions like lower loss dielectric, high-speed connectors, smoother copper profile and back drilling improve the channel significantly to support 25Gbps
signaling; but to improve overall margin, there are still effects that need to be studied and analyzed. One such parameter is the AC coupling capacitor. Generally, the placement and value of these capacitors are specified by the SerDes vendors, but ultimately, the system designers have to take the responsibility for the signal integrity and EMI effects of
the AC coupling capacitor. Some of the AC coupling capacitor parasitic effects such as pad size, cutout/antipad size etc. have been investigated for optical-electrical high speed serial link [5].
This paper is intended to help develop an understanding of the AC coupling capacitor and
its impact on a 25Gbps+ high-speed channel. Modeling techniques which capture both parasitic and capacitor value effects are developed and analyzed. By using the validated modeling method, the parasitic effects of the AC coupling capacitor, specifically related to its placement, are analyzed. AC coupling capacitor implementation on a device level
(on-package or on-die) is also investigated. Finally, a full channel analysis is conducted by taking a few representative AC coupling capacitor cases from the board-level and device-level analysis to understand the signal integrity and EMI impact on the 25Gbps reference channel.
The paper is organized as following:
Section 2 reviews the modeling and simulation methods for AC coupling capacitors and validates these methods from both circuit simulation and 3D high frequency modeling viewpoint. The validated modeling method will form the basis of the 3D
high-frequency modeling of the implementation of AC coupling capacitor in the following sections.
Section 3 investigates a few variations of board-level AC coupling capacitor
implementations from packaging parasitic perspective. The modeling technique discussed in section 2 is adopted, combining both the physical implementation effects and the capacitors characteristics, to illustrate the pros and cons of different implementation techniques. For the board-level implementation, the via-in-pad with
extended connection to AC coupling capacitors placed side-by-side and staggered are investigated using 3D high-frequency simulation.
Section 4 expands the scope of the analysis to include device-level AC coupling capacitor implementations, including on-package as well as on-die AC coupling.
Section 5 uses a 25Gbps reference backplane channel to further analyze the effects of AC coupling capacitor implementation on a realistic system. The backplane channel
simulation is correlated with the measurements. In this section, the implementation techniques discussed in section 4 and section 5 will be incorporated in the reference channel to study the SI impact on the complete channel.
Finally, section 6 summarizes the observations and conclusions from this work in the
context of 25Gbps+ systems.
2. AC coupling capacitor modeling and simulation
The modeling and simulation of the channel with a non-ideal and real-world physical implementation of AC coupling capacitors are not trivial. To avoid large s-parameter
files, the analysis of the components included in channel simulations are limited to a starting frequency point of MHz with DC extrapolation and 10~20MHz frequency step size for a wideband S-parameter model. To the max frequency of 25GHz and beyond, the direct consideration of AC coupling capacitors is challenging given that the lowest
non-DC frequency point is typically around 10~20MHz. The frequency behavior of the AC coupling capacitors is just neglected in such s-parameter models and channel simulation setups.
To investigate the impact from the AC coupling capacitors, we would have to
Extend the starting frequency point from 10~20MHz to KHz
Adopt a frequency sweep stepping of KHz
Consequently, the S-parameter model for the components or the channel will become too big to handle.
When considering the PCB implementation of the AC coupling capacitor, one needs to characterized the parasitic effects of vias, stubs, pads, antipads, and traces. The parasitic effects may be modeled by a 3D full-wave simulator accurately, however, adding a lumped ideal capacitor in the structure and obtaining a ultra-wide band frequency
response without losing the low frequency response will make the 3D full-wave analysis not practical. An improved modeling technique is required to accommodate both the parasitic effects modeling and the circuit modeling.
2.1. Equivalent model and its circuit model validation
Recently, an equivalent model has been proposed by Yosuo Hidaka [6]. In the proposed method, a short perfect conducting strip is employed to replace the AC coupling
capacitor in its physical location and an ideal capacitor is added to the receiver end of the channel (after the channel block) for channel simulation. It has been reported that this approach will not result in any difference in the S21 or S11/S22 characteristics since the capacitor has nearly zero loss at high frequencies (MHz and beyond).
Figure 1: A depiction of an equivalent model proposed by [6] in a time-domain channel simulation
To validate the approach of considering the placement of the capacitor at different locations in the channel, we take a simple model constructed from an ideal transmission
line with an electrical length specified at 2GHz and a few lumped elements to model the parasitic inductance. To include the via inductance for the AC coupling capacitors, a 0.5nH ideal inductor is added on both ends of the capacitor which contributes 1nH total to the channel. The circuit representation of the validation model includes a coupled
transmission line with the following properties:
Coupling: coupling factor = 0 (zero coupling)
The electrical length of the transmission line for the study
o Electrical length: half wavelength@2GHz on both TX and RX side
o 10dB/half-wavelength loss has been added to model the transmission line loss
The validation circuitry is illustrated in Figure 2 below:
Figure 2: Circuit model used to validate the equivalent AC coupling model with an ideal transmission line
(electrical length half wavelength@2GHz on both TX and RX ends); Top: equivalent model; Bottom: equivalent
model with ideal circuitry representation.
Channel
Channel0 ohm
Via & Footprint
Via & Footprint
CapActual System
Equivalent Model
Cap
The return loss, insertion loss, and phase response for the circuits in Figure 2 in a spectrum of DC to 1GHz are plotted in Figure 3, Figure 4, and Figure 5.
Figure 3: Return loss for circuit model
Figure 4: Insertion loss for circuit model (Left Y-axis: magnitude; Right Y-axis: phase)
Figure 5: Phase responses for the circuit model
To further validate the model, we consider an asymmetric case where the traces are coupled differential pairs. For this case, the traces are adjusted such that:
A coupling factor k=0.2 is considered for the differential pair
A delay line with an equivalent inductance of 10nH is added to one trace to generate skew in the differential pair
To make the channel asymmetric on the TX and RX side of the AC coupling cap, the electrical length of the transmission line is adjusted as follows:
o The length at the TX side is adjusted to be 1/12 wavelength at 2GHz
o The length of the differential pair at the RX side is adjusted to be 11/12 wavelength at 2GHz
The circuit is shown in Figure 6.
Figure 6: Asymmetric skewed circuit with 1/12 wavelength@2GHz trace on the TX side and 11/12
wavelength@2GHz on the RX side (top: AC cap outside of channel; bottom: AC cap inside channel)
Figure 7: Return loss of the asymmetric model
Figure 8: Insertion loss of the asymmetric model
Figure 9: Phase response for circuit model
The results for the asymmetric case show very little difference in the insertion loss and
return loss by placing the AC coupling capacitor outside of the channel, as shown in Figure 6, Figure 7, and Figure 8. Very minimum phase changes have been also observed as seen in Figure 9.
2.2. The capacitor value – when it matters?
The typical recommended AC coupling capacitor values are within the range of 10- 300nF. The most commonly used values for AC coupling capacitors in high-speed NRZ interfaces are summarized as in table 1.
Table 1: Typical AC coupling capacitor values by interface
Standard Data rate Data
encoding
DC blocking capacitor value
Min Typ Max
PCI-Express 2.5G / 5G 8b/10b 75nF 170nF* 265nF
PCI-Express 8G 128b/130b 176nF 221nF* 265nF
SFF-8431 10.3125G 64b/66b 100nF Implied by parts list for reference host compliance
board design
SAS-3 12G 8b/10b 12nF
Fibrechannel
16GFC
14.025G 64b/66b 100nF
Not explicitly specified, but commonly used
IEEE802.3bj 25.78125G 64b/66b 100nF Not explicitly specified, but
implied in some presentations like [4]
*The mid-point between min and max.
The self-resonant frequency of the AC coupling cap and its parasitic can be evaluated by 2*Pi*Sqrt(LC). Considering the parasitic effects, the self resonant frequency for a typical AC coupling capacitor is expected to be much less than 10MHz. An extreme case for the 1nF AC coupling capacitor, where the self resonant frequency is the upper bound, is set
to a nominal of 100nF AC for the structure discussed in section 2.2. The simulated results of IL, RL, and mode conversion for the two cases (1nF and 100nF) are plotted in Figure 10 and Figure 11. The self-resonant frequency by the AC coupling capacitor increases to ~7MHz for the 1nF case, which presents a noticeable change in the return loss at the low
frequency regime, but it is still lower than most standards specified channel S-parameter model starting frequency. Very little difference has been observed in the mode conversion and insertion loss between the 1nF and 100nF capacitor cases. In this work, we will only focus on the implementation effects, not the selection criteria of the
capacitor values.
Figure 10: IL and RL for 1nF (solid line) and 100nF(dash line) AC coupling capacitor for channel 1 and channel
2.
Figure 11: Mode conversion for 1nF(solid line) and 100nF(dash line) AC coupling capacitor
2.3. High-frequency 3D full-wave modeling and validation
In this section, the physical implementation of an AC coupling capacitor on a differential channel is analyzed. In accordance with most s-parameter models generated from testing and/or 3D full-wave analysis, we set the starting frequency at 10MHz. The capacitor(s) will be modeled as an ideal lumped element. Three cases are simulated:
1. Case 1: Capacitors are added to structure model as ideal lumped elements.
2. Case 2: Original capacitors are replaced with a perfect strip to short the AC
coupling capacitor pads.
3. Case 3: Capacitors will be cascaded with the s-parameter model used in case #2.
The structure models are based on the following implementation details:
AC coupling capacitor footprint: 0402
Pad size: square 20mils x 20mils
Pad pitch: 34mils
Capacitance value: 100nF
Channel configurations
a. Signal layer for Diff 1/channel 1: Layer 2
b. Signal layer for Diff 2/channel 2: Layer 9
c. Signal layer for Diff 3/channel 3: Layer 9
Stack-up: 10 layer board of 99mil thickness (see Figure 12)
Capacitor connection: Capacitor Pad-microstrip-Signal Via Pad (dogbone)
Figure 12 shows the screenshots of the case 1 & case 2 structure model. The strip between pads represents the ideal capacitor of 100nF for case 1, and a perfect conductor for case 2.
Figure 12: 3D board illustration
Figure 13 illustrated the equivalent model to cascade the ideal lumped capacitor of 100nF with the shorted structure model of case 2.
Figure 13: 100nF AC coupling capacitors lumped with the structure model where the AC cap pads are shorted
with a perfect conductor strip.
The insertion loss and return loss of the three differential pairs are shown in Figure 14, Figure 15, and, Figure 16 respectively. The IL and RL for the case 1, case 2, and, case 3 at each channel (channel 1-red, channel 2-purple, channel 3-blue) are almost overlapped.
Figure 14: Insertion loss/Return loss for case 1, 2, and 3 (three channels are plotted: channel 1-red, channel 2-
purple and channel 3-blue);
Figure 15: Zoomed in picture of insertion loss for case 1, 2, and 3 (note that only case 3 where an external
lumped capacitor is added has the right response whereas other cases are the extrapolated data from the S -
parameter model in the 3D simulator)
Figure 16: the phase of insertion loss (red) and return loss (purple) of a selected channel (channel 1/Diff 1) for
case 1 (solid line), case 2 (dash line) and case 3(dot line), respectively
The through and reflected mode conversion for the three cases are plotted in Figure 17.
Figure 17: Mode conversion of selected channels for case 1(solid line), case 2 (dash line), and case 3 (dot line)
From the results based on the 3D fullwave simulation of the structure and the cascaded circuit with ideal lumped elements simulation, very little difference has been observed in
magnitude and phase of the insertion loss and return loss. The mode conversion plots, however, show a noticeable, yet small, difference between the two approaches.
Based on the results shown in this section, it is fair to conclude that shorting the AC coupling pads to replace the ideal capacitor is an accurate approximation to investigate
the implementation details. We will use this approach to focus on the implementation effects of both the board level and package level configurations discussed in the following sections.
3. Component-Level AC coupling capacitor
implementation on a PCB
Interconnecting an AC coupling capacitor to the PCB traces on multiple layers may often require to use components such as solder pads, via, via pads, and anti-pads. All these
small structures may contribute to the signal integrity at high frequency as the physical size becomes comparable to the wavelength of interest. Here we categorize all these small structures associated with the AC coupling capacitor as an AC coupling capacitor component. In this section, we investigate the implementation at the component level
listed in the table 2. The combination of these implementations will cover most possible connection methods of the placement of the AC coupling capacitors. A standard SMT 0402 capacitor with 100nF capacitance will be used for the studies in this section.
Table 2: Board-level AC coupling capacitor implementation cases
Case # Connection method Placement Via Stub length
1 Via-in-pad Side-by-side Long/Short
2 Via-in-pad staggered Long/Short
3 Dogbone Side-by-side Long/Short
3.1. Side-by-side AC cap using via-in-pad connection
The via-in-pad implementation is expected to minimize the connection discontinuity for
the AC coupling capacitors. For a standard 0402 SMT capacitor, the standard pad size is 20x20mil. The selected drill size needs to fit into the pad size which may limit the applicability of the cap implementation.
In a high speed channel, the typical differential pair may be tightly coupled and the space
within the pair may not accommodate the clearance required for the SMT capacitor pads and vias. In our case, the differential pair configuration is 7.75-9.75-7.75mil which leaves only about 10mils separation for the capacitor pads. An increased in trace to trace spacing is made in such a way that the capacitors’ pads can be placed side by side. The AC
coupling capacitor is modeled as a perfect conductor strip in the 3D fullwave frequency domain simulation.
Figure 18: Side-by-side capacitors implementation (left: side view; right: top view)
The routing of the signal traces in the inner layers for the capacitors placed on the top of the board leaves vias with stubs. Top inner layers routing produces longer via stub comparing to the ones in the bottom inner layers. If back drilling technique is not adopted and via stub length is about a quarter wavelength of a frequency point, the via stubs may
be self-resonant and have a significant SI impact on the channel performance.
The model configurations details for the side-by-side implementation cases are listed in in the table 3:
Table 3: Model specifics for side -by-side implementation
Case # Channel
or Diff
Pair #
100ohm DP
(mil)
Trace
length
Routing
Layers/Via stub
(mil)
Anti-pad
(pads
cutout)
1.1 Ch 1 7.75-9.75-7.75 200mil Layer 2/85.05mil 25x59mil
Ch 2 7.75-9.75-7.75 200mil Layer 9/12.65mil 25x59mil
Ch 3 7.75-9.75-7.75 200mil Layer 9/12.65mil 25x59mil
1.2 Ch 1 7.75-9.75-7.75 200mil Layer 2/85.05mil 60x59mil
Ch 2 7.75-9.75-7.75 200mil Layer 9/12.65mil 60x59mil
Ch 3 7.75-9.75-7.75 200mil Layer 9/12.65mil 60x59mil
To consider the effects of the AC coupling capacitors, an equivalent model has been constructed by cascading the ideal 100nF capacitor with the S-parameter model from the 3D high-frequency simulation. This is shown in Figure 19.
Figure 19: Cascading an ideal capacitor (100nF) with the structure s -parameter model
3.1.1 Side-by-side via-in-pad implementation with 25x59mil
rectangular cutout
Large capacitor pad size relative to the transmission line width results in an impedance discontinuity. This is typically addressed through reduction of the parallel plate
capacitance effect that exists between the pad and the reference plane below through voids. The via-to-board parastitic capacitance contributes an excess capacitance to the AC coupling capacitance and thus creates impedance discontinuity. We use a rectangular cutout through the board to serve as both the anti-pad for the via and cutout for the
capacitor pads as listed in the table 3. For case 1.1, the differential insertion loss, return loss, and mode conversion are plotted in Figure 20, and, Figure 21, respectively.
Figure 20: Differential insertion loss and Return loss (diff 1 has the big notch on the IL line and higher RL
because of the long via stub);
Figure 21: Reflected and through differential to common mode conversion for channel 1 and channel 2;
3.1.2 Cutout sizing effects for the side-by-side via-in-pad
implementation
In this case, we extend the antipad cutout size discussed in 3.1.1 from 25x59mil to 60x59mil. The enlarged antipad will be expected to reduce the parasitic between the AC
cap pads and vias. The enlarged antipad is illustrated in Figure 22.
Figure 22: Top view and 3D view of enlarged antipad for the side -by-side AC cap implementation
The comparison between the enlarged antipad case (1.1) and the rectangular antipad case (1.2) are plotted in Figure 23-26.
Figure 23: Insertion loss comparison (solid line: case 1.2, dash line: case 1.1)
Figure 24: Return loss comparison (solid line – case 1.2; dash line – case 1.1)
Figure 25: Mode conversion comparison (solid line – case 1.2; dash line – case 1.1)
Figure 26: differential impedance comparison (Tr=40ps; solid line – case 1.2; dash line – case 1.1)
As seen from the above comparisons, by changing the size of the cutout to remove excess parasitic capacitance, the impedance mismatch could be reduced. However, this
improvement on the impedance match does not guarantee the improvement of the mode conversion over a wide spectrum of interests.
3.2 Dogbone vs. side-by-side via-in-pad implementation
In this section, we investigate the implementation of the AC cap where its pads are connected to the vias by short microstrips (referred as dogbone implementation in this paper, as seen in Figure 27). The use of the microstrip is to accommodate the space
clearance required for the pads without changing the spacing of the differential pairs. We compare the dogbone implementation to the side-by-side via-in-pad implementation by examining the return loss, insertion loss, and mode conversion.
Figure 27: the dogbone implementation of the AC coupling cap (left) and the side-by-side via-in-pad
implementation (right)
Figure 28: the IL and RL comparison between the dogbone implementation (solid line) and side -by-side via-in-
pad implementation (dash line);
Figure 29: the mode conversion comparison between the dogbone implementation (solid line) and side -by-side
via-in-pad implementation(dash line);
Figure 30: the differential TDR comparison between the dogbone implementation (solid line) and the side -by-
side via-in-pad implementation (dash line);
The results indicate that the side-by-side via-in-pad implementation has less discontinuity
within the differential pair, consequently, providing a better performance on the IL, RL and mode conversion over the spectrum of interests.
3.3 Staggered vs. side-by-side capacitor placement for via-in-
pad implementation
In this section, we take the via-in-pad implementation case to investigate the performance
of staggered vs. side-by-side placements. To minimize the other effects, we will focus on the differential pairs 1 and 2, adopting the same antipad sizes for all the cases modeled in this section. The detailed comparison study cases are listed in the table 4.
Table 4: Difference between staggered and side -by-side cases
Case
Description
Channel
or Diff
Pair #
100ohm DP
(mil)
Trace
length
Routing
Layers/Via stub
(mil)
Anti-pad
(pads
cutout)
Staggered 1 7.75-9.75-7.75 200mil Layer 2/85.05mil 25x59mil
2 7.75-9.75-7.75 200mil Layer 9/12.65mil 25x59mil
Side-by-
side
1 7.75-9.75-7.75 200mil Layer 2/85.05mil 25x59mil
2 7.75-9.75-7.75 200mil Layer 9/12.65mil 25x59mil
Figure 31: staggered placement of AC coupling capacitors , top view (left), 3D view (right);
The comparison of the insertion loss, return loss, TDR, and mode conversion between the staggered placement and the side-by-side placement for differential pair 1 (channel 1, layer 2) and differential pair 2 (channel 2, layer 9) are plotted in Figure 32-35.
Figure 32: Insertion loss (solid line: staggered placement; dash line: side -by-side)
Figure 33: Return loss (solid line: staggered placement; dash line: side -by-side)
Figure 34: Differential TDR (rise time=40ps, solid line: staggered placement; dash line: side -by-side)
Figure 35: Mode conversion (solid line: staggered placement; dash line: side -by-side)
Noticeable differences in the insertion loss, return loss, differential impedance, and mode conversion have been observed between the staggered placement and the side-by-side
placement. For the staggered placement, the coupling between the AC coupling capacitor associated structures (vias, pads, non-functioning pads etc.) and the trace is reduced.
The differential impedance for a coupled transmission line is defined as;
Z_diff = 2*Z0(1-k),
Where, Z0 and k are the characteristic impedance and coupling factor respectively. The reduction of the coupling at the AC coupling capacitor location by adding extra spacing for the side-by-side implementation leads to a higher impedance than the staggered placement. Accordingly, the coupling path has been extended through the vias and the
pads of the AC coupling capacitors which may contribute to the extra coupling. This explains why the staggered placement has lower differential impedance than the side-by-side placement.
Mode conversion may be of a big concern for the staggered implementation. From Figure
35, we notice that the mode conversion of the staggered placement is about 20~30dB higher than that of the side-by-side implementation. This may cause a significant increase in EMC/EMI risk. We will investigate this issue in more details in the section 5.4.
4. Device-Level AC Coupling
For systems operating within 8-15Gbps range, it is not uncommon to encounter ICs with device-level AC coupling implementations. Whether or not such strategies are feasible/practical for 25Gbps+ systems, it must be carefully analyzed to understand the tradeoffs and to minimize the impact on signal integrity. There are two possible ways to
implement device-level AC coupling, on-package or on-die, each having their own benefits and challenges.
4.1 On-Package AC coupling
One method of implementing device-level AC coupling is to place physical capacitors on the device package between the silicon die and the device lead pads, usually on a multi-layer laminate substrate. This technique offers several advantages from a system
perspective:
It allows for a traditional capacitor values to be used (i.e. 100nF-220nF).
It removes the need for AC coupling capacitors on-board, thereby freeing up valuable board real estate and enabling denser PCB designs.
It eliminates costly vias on the PCB, which can also lead to degradation in signal integrity and manufacturing reliability.
It simplifies and accelerates the PCB design process. The need for 3D analysis of
board-level AC coupling capacitor implementation is eliminated, thereby improving the cycle time on PCB design.
At the same time, there are multiple challenges associated with on-package AC coupling:
For large devices with high channel counts (switch fabric ASICs, front-port
ASICs, multi-channel retimers, etc.), the amount of available space on the package substrate limits the total number of capacitors which can be added.
The addition of capacitors on a package substrate can lead to higher layer count
which results in higher cost and potentially reduced signal integrity.
On-package passive components pose a risk to manufacturing yield and reliability, although this risk can often be managed.
With a fixed on-package implementation, there is a risk of cascading multiple AC
coupling capacitors in a system if multiple devices with on-package capacitors are connected. This is only an issue for smaller capacitor values and high consecutive identical digits (CID) encoding schemes.
The frequency response of the high-pass filter which results in AC coupling capacitor values described in Table 1 (assuming a 100Ω differential impedance) is illustrated in Figure 36.
Figure 36: High-pass filter for different standard AC coupling capacitor values and cascaded capacitor values
To illustrate the signal integrity impact of including AC coupling capacitors using surface mount components on a laminate substrate package, an example BGA package was designed with the following characteristics:
Number of layers: 4 (2 signal, 1 power, 1 GND)
Capacitor footprint: 0201
Capacitor value: 100nF
Dielectric material: FR406
Trace width: 5mil
Trace spacing: 5mil
The frequency responses of the high-speed nets on this experimental package with and
without the AC coupling capacitors implemented are shown in Figures 37 and 38 respectively.
Figure 37: Insertion loss (Sdd21) for package channels with and without capacitors
Figure 38: Return loss (Sdd22) for package channels with and without capacitors
From the these plots, it is evident that the inclusion of the capacitors on the package is
leading to a degraded insertion loss and return loss characteristic by approximately 0.5dB and 10dB, respectively.
To evaluate the impact of including the AC coupling capacitor on-package, a simple testbench was constructed to simulate four channels with a capacitor and four without, as
shown in Figure 39.
Figure 39: Simple testbench for evaluating package model performance
The performance of each package model was evaluated by examining the near-end eye opening (height and width). The results of these simulations are shown in Figure 40 and Figure 41.
Figure 40: Impact of on-package capacitor on near-end eye height
Figure 41: Impact of on-package capacitor on near-end eye width
These results suggest that there is a performance penalty associated with including the AC coupling capacitors on-package. This degradation in signal quality arises for two
predominant reasons:
0.650
0.700
0.750
0.800
0.850
0 1 2 3
Eye
he
igh
t [V
]
Eye Height versus Package Channel
With capacitor Without capacitor
0.865
0.870
0.875
0.880
0.885
0.890
0 1 2 3
Eye
Wid
th [U
I]
Eye Width versus Package Channel
With capacitor Without capacitor
1. Inclusion of AC coupling capacitors on-package requires additional vias on the package substrate, which lead to discontinuities and degraded insertion/return loss characteristics.
2. In order to fit AC coupling capacitors on-package, the total length of the package traces may be longer than if the capacitors were not placed on the package.
In order to truly evaluate the overall benefits of putting AC coupling capacitors on-package, the entire channel would need to be taken into account. Implementing capacitors
on-package means that capacitors and their associated vias would not be needed on the board. So the only way to draw an appropriate conclusion would be to consider both the package and the board trace together, which is done in Section 5.
4.2 On-Die AC Coupling
By far the most common method of implementing device-level AC coupling is using an on-die circuit solution. Such silicon-level solutions are appealing for several reasons:
It removes the need for AC coupling capacitors on-board, thereby freeing up valuable board real estate and enabling denser PCB designs.
It eliminates costly vias on the PCB, which can lead to degradation in signal
integrity and manufacturing reliability.
It simplifies and accelerates the PCB design process. The need for 3D analysis of board-level AC coupling capacitor implementation is eliminated, thereby improving the cycle time on PCB design.
It allows for the IC package design to be optimized for trace length and return loss performance without the negative impacts associated with putting passive components on the package.
As with most things in life, however, on-die AC coupling does not come for free. While
it has its definite benefits, implementing an AC coupling scheme on-die also poses some significant challenges:
Modern silicon process technology limits the capacitor value that can be implemented to much less than 100pF typically (see [8], and this series
capacitance is often accompanied by unwanted parasitic capacitance.
Lower AC coupling capacitor values lead to baseline wander, especially in systems with high CID.
While a board-level implementation of an AC coupling circuit using passive components is noiseless, a silicon-level implementation with active circuits will inevitably incur a noise penalty. The penalty is mostly borne out of the imperfection of the baseline wander correction circuit shown in Figure 42. The
penalty paid at 25Gbps+ is likely to be higher compared to lower speed systems (i.e. 8-15Gbps).
ESD
protection
Termination
network
Baseline wander
correction
(LPF), Common
Mode set
DC blocking cap
(HPF with pole > 10MHz)
RXP
RXN
Equalizer, Clock
and Data
Recovery
(CDR), etc.
+
+
Figure 42: Generic on-die AC coupling implementation
The principle draw-back of on-die AC coupling implementations has to do with the size of the AC coupling capacitor that can be implemented in silicon. Due to process limitations, the size is generally limited to much less than 100pF. For a 100Ω differential system, the impact of the reduced series capacitance will be on the cutoff frequency of
the high-pass filter. This is illustrated in Figure 43.
Figure 43: Impact of reduced AC coupling capacitor value on cutoff frequency
When the series capacitor is reduced in value, the cutoff frequency of the high-pass filter formed by the AC coupling capacitor increases. If the cutoff frequency rises above the
low end of the frequency range of the data being transmitted, then this can lead to unwanted attenuation of low-frequency data, or baseline wander.
To understand the impact that this effect has on signal integrity, a simple simulation testbench was constructed, consisting of a 25Gbps+ transmitter, a simple differential
channel, and a pair of series capacitors, as shown in Figure 44 below.
Figure 44: Simulation testbench to evaluate impact of reduced AC coupling capacitor value
Multiple conditions were simulated in order to obtain a comprehensive view of the impact of the series capacitor on link performance. Link performance was quantified by
measuring the far-end eye height and width, without any receiver-side equalization applied. Since baseline wander is directly affected by the capacitor value and the frequency spectrum of the data stream, eye height and width metrics were gathered and plotted for various capacitor values, data patterns, data rates, and channels, as shown in
Figure 45 and Figure 46 below.
Figure 45: Eye height versus DC blocking capacitor value
Figure 46: Eye width versus DC blocking capacitor value
These results show that for systems with long CID encoding schemes (like 64b/66b), link performance starts to degrade significantly when the series capacitor value falls below 10nF. For systems with shorter CID encoding schemes (like 8b/10b), link performance does not begin to degrade until the series capacitor value falls below 0.1nF.
Given that most interfaces operating above 10Gbps use encoding schemes with long CIDs like 64b/66b or higher, the eye height and width degradation caused by smaller series capacitor values must be compensated by a baseline wander correction circuit.
Such circuits have their own set of challenges and deficiencies and will require additional power consumption and device area in order to implement.
5. AC Coupling Capacitor Impact on A 25Gbps
Reference Backplane Channel
In this section, both the device level and board level implementations on a reference
channel will be analyzed. The reference channel construction is illustrated in Figure 47.
Figure 47: Reference backplane channel configuration illustration
5.1 25Gbps backplane reference channel correlation
In this section, we conduct a frequency domain test versus model correlation study for a reference backplane channel. The main purpose is to establish the solid baseline for the AC coupling capacitor impact on channel performance. In this reference channel, we will consider Megtron 6 and ISOLA IS415 line cards.. The backplane construction
details are listed below:
Channel length: Backplane: 29.0inch; LineCards (TX and RX): 5inch each; Total length: ~39.0inch;
Backplane Stackup: 26 layer;
Backplane connector: Molex’s Impel™ 40Gbps backplane connector
Material: Panasonic Megtron 6; Manufacturer published Dk/Df: 3.5/0.002;
Line cards designs:
o Linecard design 1 – 20 layers; Panasonic R-5775K Megtron 6; Manufacturer published Dk/Df: 3.5/0.002; 100 ohm differential pair;
o Linecard design 2 – 10 layers; LineCard 1: Material: ISOLA IS415,
Dk/Df:3.8/0.012; 100ohm differential pair;
The two linecards stack-up are illustrated in Figure 48.
Figure 48: Linecards stackup, left: l inecard design 1 (Megtron 6); right: linecard design 2 (ISO LA IS415) ;
The typical applications of backplane channel include both the blade server and modular
switches. It has been reported that for the potential 100GBE, the maximum channel distance can be within the range of 34-39inches [9]. For PAM-2 (NRZ) solution, this usually translates to a total loss of around 30dB. For the reference channel used in this work, we choose a total length of ~40 inch which includes the AC coupling capacitor
implementation, and the associated traces/vias, a 29inch trace on backplane, and two 5inch line cards traces.
The block representation of the 39” long reference channel is illustrated below in Figure 49.
Figure 49: the reference backplane channel il lustration;
The reference channel test and model correlation for line card design 1 ( without AC coupling capacitors) is shown in Figure 50. The measured data agrees very well with the simulation results up to 17GHz.
Layer Lyr Type Thickness
SolderMask 0.5
1 TOP 2.40
Prepreg 1080 9.75
2 INNER1 1.30
Core 1080*3 10.00
3 GND 1.30
Prepreg 1080 9.40
4 INNER2 1.30
Core 1080*3 10.00
5 GD2 1.30
Prepreg 1080 4.50
6 GD3 1.30
Core 1080*3 10.00
7 INNER3 1.30
Prepreg 1080 9.40
8 GD4 1.30
Core 1080*3 10.00
9 INNER4 1.30
Prepreg 1080 9.75
10 BOTTOM 2.40
SolderMask 0.50
Total Thickness 99.0
Figure 50: The correlation of measurement and simulation results for the 40inch reference backplane chan nel
for line card design 1 (model=Solid lines);
Line card design 2 is the base design for the AC coupling capacitor implementation study
that we have discussed in section 3. We take the same channel configuration, where the correlation has been established, and replace the line card design 1 with the line card design 2 to investigate the AC capacitor implementation impact. In this channel, the connector via models for the line card 1 are not updated with line card 2 material and
stack-up since only the cap implementation and trace losses are of importance . The simulation results of this channel versus the channel with line card 1are plotted in Figure 51. The insertion loss difference is caused by the higher loss of PCB material used in the line card design 2 (dash lines).
Figure 51: Differential IL and RL for line card design 1(Megtron 6, solid line) and line card design 2(ISO LA
415, dash line)
Since good correlation between the measured data and modeling results for the reference
backplane channel has been established, the modeled AC coupling capacitor implementation in conjunction with the model of the channel can be used to study both device level and board level implementations.
5.2 Device level implementation impact on the
reference channel
In addition to analyzing the AC coupling capacitor’s impact on board-level and device-
level implementation, we analyze the entire system (device plus board) to see if there are any advantages in different capacitor placement locations. The comparison between the placement of the capacitor on the board versus on the package is done by analyzing the relative change in the insertion loss and/or return loss characteristic.
For the device level implementation, we consider the channel configuration as depicted in Figure 52 where with the AC coupling capacitors replaced in the package of the RX. A reference channel data with AC coupling capacitors placed at the RX end on the board is also used for comparison purpose. The insertion loss and return loss with or without
capacitors for the channel and the package are shown in Figure 53 and Figure 54.
Figure 52: the device level AC coupling cap implementation for the reference channel;
Figure 53: Insertion loss comparison for channel (left) and package (right) models with and without capacitors
Figure 54: loss comparison for channel (left) and package (right) models with and without capacitors
When these models are cascaded (no-cap channel and with-cap package; with-cap channel and no-cap package), the total impact on insertion loss and return loss is illustrated in Figure 55 and Figure 56.
Figure 55: Insertion loss for package + backplane combination
Figure 56: Return loss for package + backplane combination
From this data it is apparent that, from an insertion loss perspective, there is not much difference between the board-level and device-level AC coupling capacitor
implementation, provided that the board-level implementation can be done with minimal
stub length. From a return loss perspective, however, there is a clear advantage for the board-level implementation over the device-level implementation by about 7dB at 12.5GHz. Long via stubs cause undesirable effects in the insertion loss characteristics.
This is an important effect which must be considered when evaluating the advantages/disadvantages of a board-level versus device-level implementations.
5.3 Board level implementation impact on the reference
backplane channel
In this section, two cases, staggered and side-by-side via-in-pad implementation with rectangular cutout (29x59mil), are analyzed in conjunction with the reference backlane
channel model. The implementation details of the two cases were discussed in section 3. As described in that section, the staggered via-in-pad implementation has shown a significant degradation of performance because of the increased discontinuity of the differential pair. To demonstrate the via stub effects, we use the same differential pair
configurations as desribd in section 3 where the differential pair 1 has a long via stub and the differential pair 2 has a short via stub. The investigation of the impact of the AC coupling capacitors is conducted by placing the
the AC coupling capacitor near the RX and backplane connector on the linecard (design 2) of the channel as illustrated in and Figure 57 and Figure 58. The value of the AC coupling capacitor is set to 100nF.
Figure 57: the board level implementation with AC coupling capacitors placed near the RX;
Figure 58: the board level implementation with AC coupling capacitors placed near the backplane connector;
In Figure 59, by placing the AC coupling capacitors farther away from the RX, the excess trace loss pacifies and reduces the total return loss produced by the capacitor via stub
effects.
Figure 59: the IL and RL comparison between the backplane connector end placement (solid line) and the RX
end (dash line) placement for the side -by-side via-in-pad implementation.
Figure 60: the IL and RL comparison between staggered implementation (solid line) and side-by-side
implementation (dash line) for Diff pr1(channel 1, long via stub) and Diff pr2(channel 2, short via stub) with AC
caps placed near the RX;
As shown in Figure 60, the staggered implementation creates a larger discontinuity in the channel. Up to 19GHz, the return loss measured at the RX victim is between 3 to 5dB higher than that of the side-by-side implementation for channel 1. Up to 12.5GHz, the RL is between 5-10dB higher for channel 2.
5.4 The placement of AC coupling capacitor impact on
the channel EMI
In section 3.5, we have demonstrated that the staggered AC coupling capacitor
implementation may have a higher potential EMI risk than the side-by-side implementation because of the higher mode conversion noise. In this section, we will further study this case and analyze its impact on the full channel EMI for two channels, channel 1 with AC cap of 85.05 mil via stub, and channel 2 with AC cap of 12.65 mil
stub). The two channel descriptions are listed in table 5:
Table 5: Channel details for staggered vi a-in-pad implementation
Case
Description
Channel
or Diff
Pair #
100ohm DP
(mil)
Trace
length
Routing
Layers/Via stub
(mil)
Anti-pad
(pads
cutout)
Staggered
via-in-pad AC coupling capacitor
1 7.75-9.75-7.75 200mil Layer 2/85.05mil 25x59mil
2 7.75-9.75-7.75 200mil Layer 9/12.65mil 25x59mil
Our work published in [10][11] indicated that the return loss may be a good parameter to consider the total radiated emission power of a system for the 25Gbps+ system, but the common mode noise, the mode conversion, and the common mode return loss indicate
the potential level of emission from the channel where a radiator is well identified. To investigate the potential common mode radiated emission, we simplified the reference backplane channel by removing the connector and the connector signal vias to establish a
baseline, where only the line card traces and midplane traces are included. By doing this, we are trying to remove the effects of the other components which may create discontinuity in the channel, therefore, characterizing the capacitor effects more clearly.
The AC coupling capacitor, which is implemented by a staggered via-in-pad method (channel 2), is to be included at two locations: 1) at the RX on the line card, and 2) between the line card trace and midplane trace (i.e., close to connector on the line card). The simplified baseline channel and the placement of the AC coupling capacitor are
illustrated below:
(a) Baseline channel
(b) AC cap package placed near RX on the linecard
(c) AC cap package placed between the midplane and line card at RX end (near a backplane connector);
Figure 61: simplified baseline channel for EMI study with staggered via-in-pad AC coupling capacitor
implementation; (a) reference; (b): AC cap package near RX; (c) AC cap package near connector;
5.4.1 Common mode received at the receiver
The differential to common mode conversion from the TX (diff 2) to RX (diff 1) is plotted in Figure 62 and Figure 63 for the frequency domain and time domain,
respectively. For the time-domain simulation, a step function differential signal (10/90% rise time= 20 ps, voltage=400mV) is launched from the TX. The blue lines in both figures are the reference case in which the small numerical simulation errors may have generated a negligible mode conversion (less than -80dB). The received common mode
power (RX) for AC cap near receiver (red line) shows little difference from that of placing an AC cap near the connector. The received common mode power at the receiver depends on the mode conversion occurring at the AC coupling capacitor as well as the common mode degradation through the transmission line. In this case, the 5inch line card
common mode loss is very close to the differential mode loss, and consequently the received common mode power shows minimum difference. If the balance between common mode and differential insertion loss is affected by trace geometry and/or fabrication artifacts, the outcome may be different. It is often observed that common
mode propagation is affected and attenuated more. For this case, both forward (BGA as a radiator) and reflected (from BGA/Chip package discontinuities), the magnitude of common mode energy is greater for the case where AC cap is closer to the chip.
Figure 62: the differential to common mode conversion (blue: baseline; Red: AC coupling capacitor package
near RX; Green: AC coupling capacitor package near connector);
Figure 63: The common mode signal noise level received at the receiver with a differential signal injected at the
TX (blue: baseline; Red: AC coupling capacitor package near RX; Green: AC coupling capacitor package near
connector);
5.4.2 Common mode noise received at the transmitter
If we look at the reflection of the converted common mode noise, as shown in Figure 64 and Figure 65, we notice that the reflected power is increased because of the AC coupling capacitor asymmetrical PCB implementation. It also shows that placing the AC coupling
cap near RX will reflect less than that of placing it near the connector, which is mainly an effect due to the excess attenuation of the common mode noise by the longer propagation distance. As shown in Figure 65, we observe that the common mode noise peak value of a launched differential signal (20ps 10/90% rise time and 400mV) for the AC coupling
capacitor placed near RX is about 25% less than the one placed near the connector. This may result in a significant increase in the amount of emission from a radiating discontinuity on the reflection path.
Figure 64: The return differential to common mode conversion at the TX (diff 2) (blue: baseline; Red: AC
coupling capacitor package near RX; Gree n: AC coupling capacitor package near connector);
Figure 65: The common mode signal received at the transmitter when a differential signal is injected into the
transmitter for the channels (blue: baseline; Red: AC coupling capacitor package near RX; Green: AC coupling
capacitor package near connector);
In this section, we focused on the asymmetrical implementation of the cap and assumed that it is the only source of mode conversion; however, one should consider all other potential sources with comparable mode conversion characteristics. For example,
application of the AC cap closer to the receiving chip may be more advantageous if the common mode is generated directly from the transmitter due to an imbalance between positive and negative rails of the differential signal.
6. Observations and Conclusions
In this paper, various implementations of AC coupling capacitors were reviewed. By
validating the equivalent circuit modeling approach for the AC coupling capacitor, we were able to use 3D fullwave EM tools to model and simulate the capacitor PCB implementation cases and develop an accurate end-to-end analysis. Our work at both the component level (AC coupling capacitor and its parasitic) and the complete channel
(channel simulation with AC coupling capacitor circuits) have shown that:
For the AC coupling capacitor and its parasitic modeling o It is reasonably accurate to replace the AC coupling capacitor with a
perfect conducting small strip for the detailed 3D high-frequency modeling; for the complete response with AC coupling capacitor, ideal lumped capacitors can be used in a circuit simulation tool to cascade with the S-parameter model. Both our circuit simulation and structure modeling
validate the equivalent model proposed in [6].
For the AC coupling capacitor and its parasitic SI characteristics o The parasitic effects associated with vias, stubs, etc. are more critical for
signal integrity than the capacitor value itself for both the package level
and board level since the capacitance effect occurs at a very low frequency.
For the AC coupling capacitor physical implementation effects on the channel
performance o The location of the AC coupling capacitor in the channel may have a
significant impact on the channel performance if the implementation
parasitic of the AC coupling capacitors creates a noticeable discontinuity within the channel. 3~5dB improvement on the return loss within the spectrum of interest is noticed by placing a via-in-pad implementation near the connector on the line card versus placing it near the receiver on
the line card. This is a reduction on the re-reflection from a potential chip/package reflection due to a channel and package impedance mismatch.
o Package-level AC coupling capacitor implementations may offer certain
system design advantages (reduced LC complexity), but they potentially come at the cost of having sub-optimal signal integrity performance (package complexity).
o Die-level implementation saves valuable board real estate and minimizes
the signal integrity degradation due to the AC cap implementation but it is susceptible to baseline wander effects, and correction circuits may have a performance penalty associated with them.
For the AC coupling capacitor EMI effect from the PCB implementation
o The potential EMI noise and emission may be aggravated if the cap implementation discontinuity introduces a significant amount of common mode noise. Assuming, the cap implementation is the only source of mode conversion, proximity to the receiving end can help to mitigate the
common mode noise magnitude.
7. Acknowledgements
The authors would like to thank Mr. CheeParng Chua and Vivek Shah, both from Molex Inc., for preparing the reference backplane channel data for this study. The authors would
also like to thank Marie Milleron, Nate Unger, and Jitendra Mohan from TI for their support.
8. References
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[4] P. Amleshi et al, “25 Gbps backplane links frequency and time domain characterization - correlation study between test and full-wave 3D EM simulation,” in Proc. IEEE EMC symposium 2011, pp.809-813, 2011
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http://grouper.ieee.org/groups/802/3/bj/public/may12/hidaka_01a_0512.pdf
[7] B. Su, P. Patel, et al. “AC Coupled Backplane Communication Using Embedded Capacitor,” in 2008 IEEE-EPEP Electrical Performance of Electronic Packaging. Available: http://people.ee.duke.edu/~shunter/EPEP2008.pdf
[8] Y. Dong, et al. “AC-Coupling Strategy for High-Speed Transceivers of 10Gbps and Beyond,” in 2007 IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2007). 2007 © IEEE. Available: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04402477
[9] Scott Kipp, Pravin Patel, Mike Li and Mike Dudek, “PAM-2 Broad Market Potential,” IEEE P802.3bj 100Gb/s Backplane and Copper Cable Task Force, November 2011.
[10] X. Wu, et al. “Test vs. Model Correlation Study on Return Loss Characteristics of an
Emulated 25Gbps+ Backplane System EMI Source,” in Proc. IEEE EMC Europe 2012, Rome, Italy, November 2012.
[11] P. Amleshi, et al. “High-Speed EMC/EMI Correlation Study- 3D EM Model versus Anechoic Chamber Test,” Designcon 2012, Santa Clara, Jan. 2012