DESIGN OF RING OSCILLATOR USING FORWARD BODY BIAS (FBB) TECHNIQUE

DAYANASARI BINTI ABDUL HADI

PROJECT REPORT SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF SCIENCE

FA CUL TY OF ENGINNERING AND BUILD ENVIRONMENT UNIVERSITI KEBANGSAAN MALAYSIA

BANGI

2017

11

DECLARATION

I hereby declare that the work in this thesis is my own except for quotation and

summaries which have been duly acknowledged.

31 January 2017 DAY ANASARI BINTI ABDUL HADI

P81521

111

ACKNOWLEDGEMENT

Praise to Allah, the Almighty. This dissertation would not have been possible without

close interactions and advice from numerous individuals. There are many people

whose help and support has been crucial, and whom I would like to take this

opportunity to thank.

Firstly, I would like to thank my supervisor and also my lecturer, Dr. Noorfazila

Kamal for her great faith in me and for her patient guidance throughout this project. It

was an honour for me to get a chance to do my project under her supervision mainly

because of the freedom that she gave me to explore various aspects of topics and in

instilling the confidence in me to pursue different approaches towards the problem,

without worrying about the results.

A special thanks to all the staffs of Department of Electrical, Electronic and System

that are directly or indirectly help me during my final project undergo. Not to forget,

my friends for spending so much of your time with me and for seeing me through the

tortuous process of finding the right direction.

Last but not least, I would like to thanks my beloved husband Roszaiedi Ismail and

family especially my beloved parent and in law for all the wonderful support that they

give me. Besides, the love, support, prayers and encouragement that they gave always

inspired me to do my best in this project. I am indebted to them.

IV

ABSTRAK

Senibina voltan pengayun terkawal (VCO) yang kebiasaan digunakan dalam fasa gelung terkunci (PLL) adalah pengayun cincin kerana ia mempunyai jarak penalaan yang lebar dan menggunakan kawasan yang kurang pada cip. Oleh kerana pengsekalaan teknologi dan evolusi sistem kumunikasi, permintaan terhadap penggunaan kuasa yang rendah telah menjadi salah satu kriteria utama dalam prespektif jurutera rekabentuk litar bersepadu (IC). Pincangan badan ke hadapan (FBB) digunakan di dalam litar bersepadu digit dan analog berkuasa-rendah untuk melaraskan voltan ambang transistor CMOS. Dengan itu, pendekatan FBB telah dicadangkan untuk dilaksanakan dalan merekabentuk litar pengayun cincin kerana ia berupaya mengurangkan voltan ambang transistor dan seterusnya membawa kepada litar berkuasa rendah. Projek ini membentangkan litar pengayun cincin yang berkuasa rendah direka untuk aplikasi tanpa wayar pada 3 GHz. 5-peringkat litar penghayun cincin direka menggunakan teknik FBB dalam teknologi 0.13 µm CMOS. Kerja-kerja simulasi · dilakukan dengan menggunakan ELDO Spice daripada Mentor Graphics. Dengan bekalan voltan 0.8 V, pelepasan kuasa adalah sebanyak 167.03 µW dan hingar fasa adalah -72.88 dBc/Hz pada 1 MHz. , Saiz litar pengayun cincin tersebut adalah 22.4 x 25.6 µm2.

v

ABSTRACT

A cominon voltage controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator because it has wider tuning range and consume less area on chip. Due to technology scaling trend and communication system evolution, the demand of low power consumption is become one of the major criteria in integrated circuit (IC) design engineer perspective. Forward bode bias (FBB) used in digital and low-power analog integrated circuits to adjust the threshold voltage of complementary metal-oxide-semiconductor (CMOS) transistors. Thus, a forward body biased approach is proposed to be implemented in designing the ring oscillator due to it capability to reduce threshold voltage of the transistor and leads to a low power consumption circuit. This project presents a low power ring oscillator designed for wireless application at 3 GHz. A 5-stage single-ended ring oscillator is designed using forward body bias technique in a standard 0.13 µm CMOS technology. The simulation is perfoi:med using ELDO Spice simulator from Mentor Graphics. With supply voltage of 0.8 V, the power dissipation is 167.03 µWand the phase noise is -72.88 dBc/Hz at 1 MHz. The proposed ring oscillator with new delay cell layout occupied 22.4 x 25.6 µm2

•

CONTENTS

DECLARATION

ACKNOWLEDGEMENT

ABSTRAK

ABSTRACT

CONTENTS

LIST OF TABLES

LIST OF FIGURES

LIST OF SYMBOLS

LIST OF ABBREVIATIONS

CHAPTER I

1.1

1.2

1.3

1.4

CHAPTER II

2.1

2.2

2.3

2.4

INTRODUCTION

Motivation and Background Study

1.1.1 Recent Trend of Communication System

Problem Statement

Thesis Objective

Thesis Organization

LITERATURE REVIEW

Introduction

Basic MOSFET Principle

2.2.l MOSFET 1-V Characteristic 2.2.2 MOSFET Threshold Voltage

Forward Body Bias (FBB) Mechanism

Basic Concept of Ring Oscillator

2.4.1 Oscillation Frequency 2.4.2 Phase Noise

Vl

Page 11

111

lV

v

Vl

vm

lX

Xl

Xll

1

2

5

5

6

7

7

9 11

11

14

16 16

Vll

2.5 Ring Oscillator Topology 18

2.5.1 Single-Ended Ring Oscillator 18 2.5.2 Differential Ring-Oscillator 22 2.5.3 Source Follower Ring Oscillator 23

CHAPTER III METHODOLOGY

3.1 Introduction 25

3.2 Software Description 27

3.3 FBB device Characterization 27

3.4 Proposed Ring Oscillator Circuit 29

CHAPTER IV RESULT AND DISCUSSION

4.1 Introduction 31

4.2 FBB Characterization on Device Level 32

4.3 Ring Oscillator Circuit Analysis 36

4.3.1 Conventional 5-stage Ring Oscillator 38 4.3.2 5-stage Ring Oscillator Under FBB 38

4.4 Comparison Study 39

4.5 Post Layout Simulation 40

CHAPTERV CONCLUSION

5.1 Conclusion 42

5.2 Recommendation 42

REFERENCES 44

· APPENDIX 49

LIST OF TABLES

Table No.

3.1 Simulation condition for both NMOSFET and PMOSFET

device for FBB characterization

3.2 Transistor sizing for PMOS and NMOS

3.3 Parameter for FBB condition

4.1 Summary of comparison study between conventional and

under FBB condition for 5-stage single-ended ring oscillator

vm

Pages

29

29

30

40

lX

LIST OF FIGURES

Figure No. Page

1.1 Basic architecture of PLL 1

1.2 Summary of scaling trends of the mobile driver 3

1.3 FBB scaling trend 4

2.1 NMOS device with four terminals 8

2.2 CMOS circuit diagram 8

2.3 Cross sectional diagram of CMOS 9

2.4 I-V characteristic ofNMOSFET 9

2.5 Cross-section diagram representation Schematic 12

representation of an NMOSFET under FBB and Auger

recombination process due to hole injection to the channel

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

3.1

by a positive substrate bias

Drain current 10 s against gate voltage Vas characteristics as

a function of substrate bias VBs from +0.5 V to 00.5 Vin

steps of 0.25 V

The measured and calculated V TH versus V ss for

NMOSFET and PMOSFET

The block diagram of 3 stages single-ended ring oscillator

Phase noise per unit bandwidth

The current starved inverter

The schematic current starved delay cell based voltage

controlled ring oscillator

Circuit level Implementation of current staved nng

oscillator based on the feedback loop architecture

Multiple-pass loop structure of 3 stage ring oscillator with

differential delay

A conceptual block diagram of ring oscillator with source

follower delay cell

Flow chart for design process of voltage controlled ring

oscillator

13

14

15

17

19

20

21

22

24

26

3.2

3.3

3.4

3.5

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

(a) 4 terminals NMOSFET device (b) 4 terminals

PMOSFET device

Test bench for FBB simulation (a) NMOSFET device and

(b) PMOSFET device.

Conventional circuit for 5-stages ring oscillator

Schematic of 5-stage ring oscillator under FBB condition

Drain current versus forward bulk voltage for NMOSFET

Drain current versus forward bulk voltage for PMOSFET

Drain current versus Gate voltage for (a) NMOSFET and

(b) PMOSFET devices with VFa variation (0- 0.8 V)

Comparison of threshold voltage, VTH as a function of bulk

voltage, VFa between NMOFET and PMOSFET

Drain current versus Gate voltage for NMOSFET devices

when Vns = 1.2 V (solid line) and Vns = 0.8 V (dashed

line)

Output waveform for conventional 5-stages ring oscillator

Phase Noise for conventional single-ended 5-stage ring

oscillator

The simulated output waveform for 5-stages ring oscillator

under FBB condition (Vnn=0.8 V and VFa=0.6 V)

Phase Noise for single-ended 5-stage ring oscillator under

FBB condition

Final post-layout of single-ended 5-st~ge ring oscillator

under FBB condition

x

28

28

30

30

32

33

34

35

36

37

37

38

39

41

A

Box

~F

f osc

Hz

I min

losat

k

L

n

ni

q

T

td

tox

VTH

Vos

Vos

Vos

Vss

VFB

Voo

Vosat

w w

LIST OF SYMBOLS

Area

Gate-oxide capacitance per unit area

Load capacitance

Capacitance per unit area of the depletion layer

Degree Celsius

Decibel below the carrier per Hertz

Permittivity of oxide

Fermi potential

Oscillation frequency

Hertz

Drain Current in linear mode

Drain Current in saturation mode

Temperature coefficient

Channel Length

Number of stage

Intrinsic concertation

Mobility of the charges

Electron charge

Temperature

Propagation delay

Oxide thickness

Threshold voltage

Drain-source voltage

Gate-source voltage

Drain-Gate voltage

Source-source voltage

Forward body voltage

Supply voltage

Drain Voltage in saturation

Watt

Channel Width

Xl

AP

CMOS

CPU

DA-IC

DC

DRC

EDA

FBB

IC

IEEE

ITRS

PLL

vco LOP

LVS

MOSFET

NMOSFET

PMOSFET

RBB

RF

TSMC

LIST OF ABBREVIATIONS

Application Processor

Complementary Metal Oxide Semiconductor

Central Processing Unit

Design Architecture-Integrated Circuit

Direct Current

Design Rule Check

Electronic Design Automation

Forward Body Bias

Integrated Circuit

Institute of Electrical and Electronics Engineers

International Technology Roadmap for Semiconductor

Phase Locked Loop

Voltage Controlled Oscillator

Low Operating Power

Layout Versus Schematic

Metal Oxide Semiconductor

n-type Metal Oxide Semiconductor

p-type Metal Oxide Semiconductor

Reverse Body Bias

Radio Frequency

Taiwan Semiconductor Manufacturing Company

Xll

CHAPTER I

INTRODUCTION

1.1 MOTIVATION AND BACKGROUND STUDY

In the wireless communication system, Phase-Locked Loop (PLL) is an essential

circuit component in electronics and communication. The basic architecture of PLL

comprises of phase detector, charge pump, loop filter, and voltage controlled oscillator

as shown in Figure 1.1. The phase detector receives input from reference clock and the

local clock produced by the PLL itself. Based on the naming itself, its detect the phase

difference between these two clock due to clock skew. Then the clock signal is sent to

charge pump and convert them into current pulse. Lastly, the voltage controlled

oscillator (VCO) adjust the oscillation frequency of the signal. The loop filter is

inserted to reduce high frequency noise being injected into the VCO causing jitter in

the clock frequency. The adjusted clock frequency is then fed back into the phase

detector. Depending on the application, a divide by N device is often inserted to just

after the VCO to produce a frequency multiplication effect.

!RD

Figure 1.1 Basic architecture of PLL.

Source: Hailu, & Maneatis 2009

2

VCO plays an important role in the RF subsystem (Hsu, & Chen 2011) as they

determine whether the PLL is working in a wide-band or narrow-band. VCO is used

to generate local oscillator frequency to up convert and down convert signal in a radio

frequency (RF) transceiver. Narrow-band PLLs generally employ the resonant

characteristic of inductors and capacitors to create the VCO. Meanwhile, wide-band

PLLs avoid using on chip inductors. Thus, there are two architectures of VCO

namely; ring oscillator and LC oscillator. In this work, the VCO core is based on an

inverter-type ring oscillator supplied by a current coming from the voltage-to-current

converter. Low phase noise, low power consumption and high frequency swing are the

desired characteristic in the VCO design.

1.1.1 Recent Trend of Communication System

Every wireless technology from cell phones to automatic gate uses radio frequency to

communicate. Many devices share frequencies that cause interference as they transmit

or receive signal among them. The demand for high frequency processor with low

power consumption is increasing rapidly. Short range wireless communication is held

by Wi-Fi which are corresponding to the IEEE 802.1.la and 802.llb work around 5

GHz and 2.4 GHz respectively. Nowadays, 5 GHz band used in the Wi-Fi networks

for media streaming and transferring music, picture and video to help address the

digital noise that come with the signal.

Latest 2015 International Technology Roadmap for Semiconductor (ITRS) reported

that the number of core for Application Processors (AP) increases 4x in the time

horizon and cellular data rate growth -1.3x/year as tabulated in Figure 1.2. In

addition, the processor clock speed also increases over year and it is only one of

several factors that will ultimately determine the productivity of a given computer

system. The micro architecture of the CPU itself, the number of instructions per clock

cycle, the speed of the disk storage system and the design of the software in use play a

contributing role. But raising the clock speed of the CPU has traditionally been one

sure way to get more work done in the same amount of time.

3

'Vear 2015 2017 2019 2021 2023 ' 2025 2027 2029

Number of AP con!S 4 9 18 18 28 36 30 2S

Number of GPU cores 6 19 49 69 141 247 273 303 Max·frequency of any Component In System

2.7 2.9 3.2 •J.4 3.7 4 43 4.7 • (GM't\

Number of Men plxeis In Display 2.1 2.1 3 •. 7 a.a 8.8 n.2 ll.2 JU

1nput Band Wlcith between AP and Main memory

25.6 34.8 52.& 57.1 61.9 &1;9 61.9 61.9 (Gb/s)

Metrics Number of Sensors 14 16 20 20 21 21 22 22

Nurnber of Antennas 11 u 13 14 15 1S 15 15

Nurnber of I~ 7-10 7·10 1·10 7-10 7•10 7·10 7•10 7·10

Cellular data me 11rowfn11;"'1.3x/vear tMB/sl 12.S 12.S 21.63 40.75 40.75 40.75 40.75 40.75

Wl-R data rateevolvln1 with standards (Mb/s) 867 867 867 7000 7000 28000 28000 28000

PCB area of main Components rc:m21 62 OUtput

69 76 84 93 103 103 103

Metrics Board pcwer averaged at "7%/year IW) 4.2 4.64 S.12 5,64 6 .. 22 6..86 7.56 8.48

Figure 1.2 Summary of scaling trends of the mobile driver.

Source: Graef et al. 2015

In addition, the main requirement in designing a circuit is to have minimal power

consumption of transistor operation. Based on Moore's law the number of transistor

on a chip doubles every two years. For example; latest cell phone Application

Processor (AP) increased from approximately 1 billion transistors for A 7 to

approximately 2 billion transistors for A8 while the die size is decreasing 13%. The

ITRS roadmap predicts that the Forward Body Bias (FBB) scaling trend for low

operating power (LOP) systems is likely to as Yoo scale from 1.2 V to 0.3 V, from the

130 nm node to beyond the 18 nm node at the end of the roadmap as illustrated in

Figure 1.3.

v. Vpb<Vu

18nm node, V,,rO.AV v,.=- o.1v~ ·v.=•.sv

20ft

1.4

1.2

> o.a ~

0.2

0

-().2

--

Vpb

vrro

2·2nmn.,.1

v,.=w, 13Gnm noc1e,v.=1.2V

v,..=a:rv. v .. =o.sv 2016 2001

. . ~ v •• v~ ' . ' >

, . , . - - - ,._ -· - -o- - - "'°'" - - -o-".1- -o vni>

~ Ji VtJt>

(nmos

1a 22 sz 45 .es 90 1so Technology node (nm)

Figure 1.3 FBB scaling trend.

Source: Ananthan et al. 2004

4

5

1.2 PROBLEM STATEMENT

Basically, there are two architectures for VCO namely; ring oscillator and LC

oscillator. This work is only focus on ring oscillator. The VCO core is based on an

inverter-type ring oscillator supplied by a current coming from the voltage-to-current

converter. On the performance point of view, ring oscillators are better than

relaxation oscillators. Although relaxation oscillators easily achieve very wide tuning

range but they are not so power efficient. On the other hand, the LC oscillator

consumes large die area, has low tuning range and the phase noise performance is

depending on the quality factor. Thus, ring oscillator is preferable to be used in this

work due to their compact size, digital compatibility and ease of porting.

Ring oscillator is widely used in the communication system design especially in the

wireless system (Jalil, Reaz & Ali 2013; W. H. Lee et al. 2010; Rani, & Ranjan 2012;

Thakare, & V. Ramekar 2014) and FPGA application (Kodytek, & Lorencz 2015;

Ruething et al. 2012). It also used to study the degradation of logic CMOS circuit

(Kerber et al. 2015; Wang, Olthof & Metselaar 2006). Many trade-offs in terms of

speed, power, area and application domain need to be considered in designing a ring

oscillator. Thus, it is important to determine accurate frequency oscillation of the ring

oscillator so that the designer able to make decisions regarding these trade-offs.

The main purpose of this project is to design a 5-stages ring oscillator in 0.13 µm

CMOS technology process using Mentor Graphic simulation software. The ring

oscillator is designed for 3 GHz operating frequency with low power dissipation.

However, the phase noise performance of the circuit is a bit high compare to other

works and the area occupied is reduced significantly.

1.3 THESIS OBJECTIVE

The objective ofthis project are as follow:

1. To design low supply voltage ring oscillator circuit using forward body bias

(FBB) technique.

6

II. To investigate and simulate the optimum FBB parameter to be implemented

in the ring oscillator circuit.

ui. To compare performance of the conventional and FBB ring oscillator circuit.

1.4 THESIS ORGANIZATION

This master thesis includes five chapters, starts with Chapter 1 that give an

introduction to this project includes the motivation that drive this project, problem and

the aim this study.

Chapter 2 describes literature review on forward body bias (FBB) mechanism, ring

oscillator principle, type of ring oscillator and design parameter consideration. Prior to

that, a brief introduction on basic principle of MOSFET and their characteristic are

covered in this chapter in order to further understand the importance of FBB as

compared to normal MOSFET. In this chapter, a detail discussion on previous works

is presented.

Chapter 3 explains the methodology and the simulation parameters used throughout

this project. A few parameters such as transistor sizing, bulk voltage and supply

voltage is chosen for circuit simulation . Then, a brief introduction about the Mentor

Graphic software used in this project was described in this chapter.

Chapter 5 discusses and explains the results, which the analysis is performed based on

the graphs obtained during simulation.

Lastly, Chapter 6 draws conclusion from the simulation results obtained throughout

the project. Recommendation for future work also included in this chapter in order to

improve the performance of the proposed circuit.

CHAPTER II

LITERATURE REVIEW

2.1 INTRODUCTION

In designing phase locked loop system, the ring oscillator has been a crucial building

block. This chapter gives background theory that support main topics and design of

choice made throughout this project.

Firstly, there will be a short presentation on MOSFET principle and subsection of

their important 1-V characteristic and threshold voltage in order to strengthen the basic

knowledge of the device itself. Followed by an important section concerning body

biasing that specific to forward body bias technique used in this project. Lastly, an

overview of basic concept of ring oscillator is presented and the design consideration

like frequency, phase noise and power consumption are studied.

2.2 BASIC MOSFET PRINCIPLE

Basically NMOS and PMOS devices consist of four terminals; gate (G), source (S),

drain (D) and body (B) (body is also known as substrate or bulk) as shown in Figure

2.1 and it is understood that body terminal on connected to its own source terminal. In

Complementary Metal Oxide Semiconductor (CMOS), the substrate of NMOS is

connected to the ground and PMOS is connected to voltage supply (VDD) as illustrates

in Figure 2.2 and the cross sectional diagram shown in Figure 2.3. This results in

constant zero bias at the pn-junction between substrate and the conducting channel.

Thus, the substrate does not play important role in circuit operation and can be

neglected. Width (W) and length (L) of the channel are two important design

parameters that control the current and capacitance in one design. The size or footprint

8

and speed of the transistor are determined by the channel length of the transistor. The

speed of the transistor increases as the channel length is reduced. The width of the

transistor determine the current flow through the transistor.

D

B

s Figure 2.1 NMOS device with four terminals.

Source: Maheshwari et al. 2014

Figure 2.2 CMOS circuit diagram

9

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Figure 2.3 Cross section of CMOS

2.2.1 MOSFET 1-V CHARACTERISTIC

MOSFET operates in three main regions; subthreshold, linear and saturation and each

of them has its own advantages and disadvantages. Figure 2.4 shows the current­

voltage (I-V) characteristic of NMOSFET device and it shows the device operates at

three regions as mentioned earlier. The 1-V characteristic describes current behaviour

in one device that depends on the voltage applied to its terminals.

"subthreshol.d region" T 'rw

"linear region" "saturation region"

Figure 2.4 I-V characteristic ofNMOSFET

10

The drain current expression for three regions are as follow:

w lvun = LµnCoxCVGs - VrH)Vvs

... (2.1)

lvsat = WCoxVsatCVGs - VrH) ... (2.2)

where:

... (2.3)

... (2.4)

Parameters µndefine as mobility of the charges, C0 x is the gate-oxide capacitance per

unit areas, E0 x is the permittivity of oxide and t 0 x is the oxide thickness of the device.

Assume that gate-source voltage (VGs) is much greater than threshold voltage (VrH)

for both equations. However, for linear mode, Vvs « Vvsat meanwhile for saturation

mode Vvs » Vvsat· The drain current in subthreshold region is a bit different because

the device operates when VGs « VrH and the drain current is very small. The

expression is given by:

w VGs-VTH Vvs

I - µ C vr 2 el.8 e nvT (1 - e VT) Dlin - L n ox ... (2.5)

where:

c n = 1 + dep

Cox

... (2.6)

KT Vr=-

q ... (2.7)

Vr, T, K and q is the thermal voltage, temperature, temperature coefficient and

electron charge respectively. Cdep represent the capacitance per unit area of the

depletion layer.

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2.2.2 MOSFET THRESHOLD VOLTAGE

Threshold voltage (VrH) is one of the important parameter beside the drain current. It

can be expressed by (Hokazono et al. 2006):

... (2.8)

where

... (2.9)

... (2.10)

The equation above is applied when V58 * O; meaning that the bulk terminal is

connected to any voltage potential. <PF and y are MOSFET device parameters; fermi

potential and body effect coefficient respectively. V58 is source-body potential and

VrHo is threshold voltage when V58 = 0. NAis the p-substrate doping concentration for

NMOS and ni is the intrinsic concentration. It is known that threshold voltage is

constant when source and substrate are tied together (conventional NMOSFET).

However, for body effect device, the threshold voltage is altered lead to change in

transistor delay time.

2.3 FORWARD BODY BIAS (FBB) MECHANISM

Body bias control is one of the method used in digital applications to obtain low

power dissipation and high speed (Chang, Chouhan & Halonen 2015; Su et al. 2009).

In this approach, the threshold voltage of the device varied with the voltage applied to

the body. There are two types of body bias namely; forward body bias (FBB) and

reverse body bias (RBB). Application of FBB to transistor decreases the threshold

voltage (Vm) and increase device performance (Hokazono et al. 2006; Moradi et al.

2009; Su et al. 2009). Meanwhile, RBB increases Vm and reduces leakage power

(Hokazono et al. 2006; Kamae, Tsuchiya & Onodera 2011; Keshavarzi et al. 2001).

12

However, for CMOS inverter, VTH increases by forward body bias and VTH decreases

by reverse body bias for NMOSFET and vice versa for PMOSFET (Kumar 2016).

In this technique, the NMOSFET body terminal is connected to a positive voltage

instead of ground as for conventional NMOS structure as illustrated in Figure 2.5. The

positive voltage applied to the bulk attract electrons anywhere in the substrate and

underneath the gate terminal toward the body terminal. So, its depletion region is

reduced as well as the number of dopants in the depletion region is less. Referring to

the definition of VTH, this means that, in order to equate the number of dopants, less

channel charge is needed. So, the final effect is lower VTH value to compensate the

forward bias applied to the body. This effect is quantitatively can be expressed by

equation (2.8) as mentioned in pervious sub-chapter.

Figure 2.5

Auger Recombination

0

v + BS

Cross-section diagram representation of a NMOSFET under FBB and Auger

recombination process due to hole injection to the channel by a positive

substrate bias.

Source: Su et al. 2008