design in the nano era: a statistical challenge! · 2009. 12. 29. · marcel pelgrom behavioral...

Date: Sept 14, 2006 Behavioral Modeling And Simulation Conference 2006

Slide 1

Design in the nano era: a statistical challenge!

Marcel Pelgrom

Behavioral Modeling and Simulation Conference San Jose, September 14, 2006

Philips Research LaboratoriesProf. Holstlaan 4 (HTC5)

5656 AE Eindhoven, The Netherlands

[email protected]


Slide 2

Wafer Size History

675mm/2021?450mm/2012300mm/2001200mm/1990 -

Small dimensions on large wafers


Slide 3

25 nm

15nm

65 nm

45 nm

90 nm

32 nm

22 nmanalogue

analogue

logic logic

memories

memories

memories

memories

IC industry: Quo vadis?


Slide 4

Moore’ law: Cost per IC function

1

10

100

pric

e pe

r IC 100 k

1 M

10 M

0.7 0.5 0.35 0.25 0.18 0.12µm 90 65 45nm

Reference point: 30 mm2 in CMOS12,

Dataquest: monitor of wafer price per unit area 1998-2005Dataquest mask cost: 1998-2010


Slide 5

0

1

2

3

4

5

1989 1992 1995 1998 2000 2002 2004 2007 2010 2015Year of production (ITRS)

Pow

er s

uppl

y [V

olt]

0.7 0.5 0.35 0.25 0.18 0.12 90 65 45 32

More on a chip: the power crisis

Power= activity x frequency x capacitance x voltage2


Slide 6

Power crisis:

Need to reduce power supply voltage limited by:- sub-threshold leakage

(can be avoided by switching functional blocks)- variability

0

1

2

3

4

5

1989 1992 1995 1998 2000 2002 2004 2007 2010 2015Year of production (ITRS)

Volt


Slide 7

• Variability: deterministic effects

• Variability: statistics

• The analog approach

• The digital approach

• Signal Integrity

• Outlook

Outline


Slide 8

Variability: what is it?

Uncontrolled parameter variation between individual transistors or components in one circuit:

intra-die instead of inter-die variations.

“Uncontrolled”=

• Technologist: something new on the IEDM

• Designer: something not included in the CAD tools


Slide 9

Deterministic effects, but difficult to predict and control:- Lithographical deviations- Negative Bias Temperature Instability- Well Proximity Effect- Signal integrity- Stress by wiring or Shallow Trench Isolation- Temperature gradient- Substrate noise

Stochastic (random) processes:- Component mismatch- Jitter- …………and many more effects

Variability:


Slide 10

Courtesy: Boris Ljevar (Philips)

Variability:90 nm CMOSFrequencydistribution offree-runningoscillators16x7 per reticule

reticule

CenterDonut(RTA)

boundaryRandom deviations

Lithography


Slide 11

Tensile stress increases electron mobility (30-50%)

Compressive stress increases hole mobility (50-70%)

Stress is used to improve mobilityLayer applied

to create stress

P-substrate

gate

s dµ


Slide 12

Shallow trench isolation (STI):

• STI field isolation creates compresive stress• Increases hole µ, reduces electron µ• Up to 10% ∆IDsat at close range• Links lay-out environement to current drive

P-substrate

Source: “Observation after SACOX, C065 STI Trench morphology »Crolles 2 allianceCeline Detcheverry

gate

s dµ


Slide 13

#2 Position#2 Position#1 Position#1 Position

Mismatch differences caused by mechanical strain differences due to asymmetrical placement of Metal-2 CMP dummies! Current loss of 1-5 %

Stress caused by tiling!

2/1 µm trans.

#1#1#1

#2#2#2


Slide 14

propagationH. Veendrick

Substrate Noise:A designers view


Slide 15

The problem:

Interference generator:every node of the circuit is contributing, dependingon frequency components, capacitor, undershoot

Interference channel:mostly through substrate, but may take short-cuts!

Interference receiver:every node picks up interference, many (canceling) paths

substrate


Slide 16

A simple experiment

N-well

VDD

GND

0.18 um CMOSHigh-ohmic substrateSubstrate model extractedby commercial tool:5487R’s and 6765 C’s

Zx,y Zring

GND

Courtesy: AMoS/G.Vogels

GND

0.1 V

RGND


Slide 17

70 dB between different layout implementations ! (interferer: 1 MHz sine wave at 100 mV amplitude)

A simple experiment8 variants in x,y, guard ringsilicon compared to simulation

-80

-70

-60

-50

-40

-30

-20

-10

0

10

201 2 3 4 5 6 7 8

layout

nois

e [d

b]

measurementssimulations

Courtesy: AMoS/G.Vogels


Slide 18

Some observations:

• Substrate modeling works for simple circuitshowever also a very accurate description ofthe power grid is needed!

• Simple circuits result in a complex substrate description, interpretation is difficult

• No practical solution to simulation with substrate noise

• No clue towards interference reduction


Slide 19

• Many flavors of effects as processes shrink

• Most effects can be kept in check via design rules

• The penalty is in additional area, labor and power.

• Transfer of designs becomes more difficult:“annotated designs”

• Simulation approach is unclear.

Variability: Deterministic effects


Slide 20






• Outlook

Outline


Slide 21

Limits to accuracy

Basic limit to accuracy is the abilityto reproduce exact copies,

What are the basic reasons?


Slide 22

Gate

Insulator

Substrate

Stochastic variation

Source: IntelGranularity on molecular level is reached:0.25/0.25 transistor = 1200 doping atoms0.1/0.065 transistor = 60-80 atomsStochastical variations in number of atomsdominate the component behavior


Slide 23

σ∆VTVin Vref

010203040506070

∆ VT [mV]-4.0 -2.0 0.0 2.0 4.0

Count m σ

CMOS matching

W,L

mVinWL

AVTVT =σ∆

Input

mVinVVV 2T1TT −=∆

The mean variation can be reduced to zero,The s. d. is prop to the square root of charges

1TV 2TV


Slide 24

CMOS matching

mVinWL

AVTVT =σ

0

2

4

6

8

0.0 0.2 0.4 0.6 0.8 1.0

σ∆VT(mV)

10/0.2510/1

2/1

0.2/4

0.4/10

10/10

1.2 1.4

2/10

2/0.18

0.4/1

1.6 1.8

Ref: M. Pelgrom IEEE JSSC 1989 p. 1433

0.5 µm NMOS

m/1inWL/1 µ

0.18 µm NMOS

65 nm NMOS90 nm NMOS


Slide 25

Matching: CMOS 90nm, W/L=10/5

1.5 volt

0.50

0.60

0.70

0.80

0.90

0.30 0.40 0.50 0.60 0.70

typsnspsnfpfnspfnfp Vn

Vp

10 µA

Vn

Vp

(simulation)


Slide 26

0.50

0.60

0.70

0.80

0.90

0.30 0.40 0.50 0.60 0.70

typ

snsp

snfp

fnsp

fnfp

1.5 volt

Vn

Vp

10 µA

Vn

Vp

Matching: CMOS 90nm, W/L=1/0.5

(simulation)


Slide 27

0.50

0.60

0.70

0.80

0.90

0.30 0.40 0.50 0.60 0.70

typ

snsp

snfp

fnsp

fnfp

Vn

Vp 1.5 volt

Vn

Vp

10 µA

Matching: CMOS 90nm, W/L=0.2/0.1

(simulation)


Slide 28

Global and local variation:Differential design:

VDD

∆VT1=100 mV

∆VT2=100 mV

∆Vout=0

VDD

∆VT1=+1 mV

∆VT2=-1mV

∆Vout>>0

Just increasing the parameter window is no option!


Slide 29

Present approach to statistical sim:Global variations:- worst-best case, or

- use random point in parameter space

Local variations:

- relates process and size to distribution

- determine per component a unique set of parameters

- run in Monte Carlo mode.

Global and local variations can be used independently

WLAVT

VT =σ


Slide 30

10.0M 100.0M

1.0G10.0G

100.0G(LOG)

-100.0

-90.0

-80.0

-70.0

-60.0

-50.0

-40.0

-30.0

-20.0

-10.0

0.0(LIN)

Analysis: ACSTAT Frequency

- y1-axis -DB(Vcommon)

DB(Vdiff)

VDD

Substrate noise

Example:Differential design:


Slide 31

Prediction of matching in CMOS is good (s.d. within 5-10%)

Prediction of bandgap:

count


Slide 32

Yield vs. comparator mismatch

6 mV4 mV2 mV0 mV0%

20%

40%

60%

80%

100%

Yield

Standard deviation of comparator s.d. voltage

Probability thatall 2N-1 transitions are monotonic

7-bit8 bit9 bit10 bit

1 mV

Ref: M.Pelgrom, IEEE J SSC 1994, p.879


Slide 33

Differential linearity errors in 10-bit CMOS ADC, before and after fine tuning (measured).

-2-1.5

-1-0.5

00.5

11.5

2

0 1024

-2-1.5

-1-0.5

00.5

11.5

2

0 1024

DNL (old design)

DNL (new design)

Improving performance


Slide 34






• Outlook

Outline


Slide 35

Statistical analog design1985 design: - Auto-zero techniques- Dynamic element matching

1985 simulation: Simulate with offset sourceson transistor level


Slide 36

Statistical analog designAuto-zeroing comparator

inVVDD

refV

Removes off-set at the input, loses time


Slide 37

1/2Divider

2I

I2I1

I4I3

Clock

fc

I1=I+∆I I2=I-∆I

Switches

Averaging out current sources mismatch. THD < -95dB possibleOutput currents have to be filtered by RC.

Statistical analog designDynamic Element Matching (DEM)


Slide 38

Statistical analog design1985: - Auto-zero techniques- Dynamic element matching

1995:- Sub-block techniques- Data-weighted averaging- Averaging inputs

1985: Simulate with offset sourceson transistor level

1995:Statistical models andMonte-Carlo, digital controltreated as analog circuit


Slide 39

inV

clock clock clock

Rt Rc

Resistors add the input signal linearly, whilethe comparator mismatch adds with sqrt.

Ref: Kattmann, K. and Barrow,

inV1i,refV − i,refV 1i,refV +

Statistical analog designMismatch averaging


Slide 40

Statistical analog designData weighted averaging

Digital to analog conversion:


Slide 41

Statistical analog design1985: - Auto-zero techniques- Dynamic element matching

1995:- Sub-block techniques- Data-weighted averaging- Averaging inputs

2005:- (Sub)-system cancellation- Error calibration

1985: Simulate with offset sourceson transistor level

1995:Statistical models andMonte-Carlo, digital controltreated as analog circuit

2005:Need for advanced mixed-level and mixed mode


Slide 42

Statistical analog design

ΣFineADC

N-n bits

CoarseADCn bits

DACInput

DEC

OD

ER N bits

Digitalanalysis

Correction

in

out

Digitalanalysis


Slide 43

Present status in analog:• Analog designers tackle statistical problems ona sub-system level for optimum performance

• These methods involve signal processing ofincreasing (digital) complexity.

• Co-Simulation in various domains (digital, “MatLab”,extracted lay-out and transistor level) is needed.

• Statistical simulation with Monte-Carlo is no longeracceptable: too time consuming and does not tracethe real corner cases.


Slide 44






• Outlook

Outline


Slide 45

Latch

Analog and digital

Egateσ∆VT

Vin VrefW,L

Diff pair

Transistor mismatch dominates thermal noise:• Major issue in many analog components• Starts bothering digital designers

kT100ACCE

WLCC,LW

A

2VTox

2VTgategate

oxgateVT

VT

≈=σ×=

=×

=σ

∆

∆


Slide 46

SRAM 6T cell

BL BL

+ +WL WL

Current drive mustbe sufficient to retaindata during read andavoid flipping due toBL pre-charge level.

Cell must allow a write operationby a low bit line


Slide 47

I

II

VinIVoutII

VinIVoutII

[V]

[V]

SNM

In SRAM 6T cells Static Noise Margin: size of “eye” defines robustness

count

SRAM has mismatch problems


Slide 48

0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0

0.2

0.4

0.6

0.8

1.0

1.2

1000 trials, nominal conditions, predicted AVT

SRAM static noise margin “32nm”


Slide 49

SRAM moving to 7,8, 10 transistor cell

BL BL

+ + +

write read

Ref: B. Calhoun, MIT, ISSCC2006

WL WL


Slide 50

∆T1 ∆T2

16 ps(Cload=50fF)

16 ps(Cload=50fF)

0.25 µm

16 ps(Cload=35fF)

21 ps(Cload=50fF)

0.18 µm 90 nm0.13 µm

33 ps(Cload=20fF)

22 ps(Cload=25fF)

σ∆T2

68 ps(Cload=50fF)

38 ps(Cload=50fF)

σ∆T2

Timing getting worse for new generations.

Wp=2Wn=8Lmin


Slide 51

Statistics in digital design• The first digital paradigms (6T cell) are under discussion due to the statistical challenge.

• More trouble to follow (statistical timing).

• In contrast to analog there is little room to escape in digital.

• How to maintain the digital abstraction withoutsacrificing too much area/power/performance?

• Digital circuits go analog!Will digital simulation also go analog?


Slide 52

Variability: What to do?

Actual values from stochastic distributions cannot be predicted.

Circumstances (temp, voltage, process corner) can be measured

More optimum setting can then be achieved

Measuring of analog parameters in VLSI ICs


Slide 53

analogueanalogue

logic logic

memories

memories

memories

memories


Slide 54

Signal Integrity Architecture

Functional block 1

Processorblock 2

IP block 3

IEEE Std. 1149.1 TAP

regi

ster

Monitor 1

register

Monitor 2

regi

ster

Monitor 4

SIST controller

CMOS IC

register

Monitor 3

Petrescu, Pelgrom, Veendrick et al, ISSCC 2006


Slide 55

technologymonitors

designmonitors

functionalcore

A

B

C

D

SiliconFour identical functional

coresA: No decapB: Half decapC: Nominal decap 500pFD: Double decap

In 90nm CMOS process


Slide 56

Measurements Results

nohalfnominaldouble

DECAP

100%0.6

0.7

0.8

0.9

1.0

1.1

1.2

0% 20% 40% 60% 80%Activity

min

Vdd

(V)

2x

1x

0.5x

0


Slide 57

65 nm test chip


Slide 58

Measurement Results65 nmV re

fin

mV

823824825826827828829830831832

-30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120

Temperature

Ref

eren

ce v

olta

ge

0

20

40

60

80

100

120

0 10 20 30 40 50 60 70 80 90 100 110

Actual temperature

Switc

h po

int t

empe

ratu

re sist0sist1sist2sist3sist4sist5sist6sist7sist8Petrescu, Pelgrom

et al.ESSCIRC 2006


Slide 59

OutlookVariability is one of the main design-technologicalproblems in deep sub micron technology.

• Most effects are understood and can be addressedeither by design rule or by statistical analysis.

• Statistical design will become dominant over best-worst case practices.

• Digital and analog design come together on circuitbut also on block level.

• Still a lot of challenge ahead!


Slide 60

Conclusion• In the nanometer era the atomic scale is reached:this inevitably leads to statistics dominating thebehaviour of components.

• In analog design statistics are part of the design process.

• The CAD tools to support the analog circuit solutionsare unavailable or immature.

• Digital designers rapidly find themselves in troublefacing the same issues.

• Solutions on circuit and CAD level will borrow fromanalog methodologies.

design in the nano era: a statistical challenge! · 2009. 12. 29. · marcel pelgrom behavioral...

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