design and implementation of modular multilevel inverter ... · design and implementation of...

International Journal of Science Engineering and AdvanceTechnology, IJSEAT, Vol. 5, Issue 5 ISSN 2321-6905May -2017

www.ijseat.com * Corresponding Author Page 556

Design And Implementation of Modular Multilevel Inverter With ReducedNumber Of Components

B Satya*1, G V Ram Mohan2

M.Tech Student, Department of EEE, KIET-II, kakinada, India.1

Asst. Professor, Department of EEE, KIET-II, Kakinada, India.2

ABSTRACT-In this paper, utilizing H-connect topology a general

course multilevel inverter for the execution of 49thlevel inverter and another calculation in producing allvoltage levels for a 49th level with less number of dcsources. Brings about diminished intricacy andpractical. The examination is finished with thecustomary topologies and affirmed by recreation comesabout.

Index Terms— voltage source inverter, developed H-bridge, multilevel inverter, Cascaded multilevelinverter.

I. INTRODUCTION

With the advancement in inverters, multilevelinverters have received more attention because high-power and medium voltage ratings provides advantagein of high power quality, lower order harmonics, andbetter electromagnetic interference etc. Byappropriately arranging the semi-conductor basedswitches the inverter will generate a stepped voltagewaveform. The primary structures of the multilevelinverters have been exhibited: "diode clasped multilevelinverter", "flying capacitor multilevel inverter," and"fell multilevel inverter". Multilevel inverters is madeout of symmetric and deviated bunches in view of thedc voltage sources.

The fell multilevel inverter is made out ofvarious single-stage H-connect inverters and is arrangedinto symmetric and hilter kilter bunches in view of theextent of dc voltage sources. In the symmetric sorts, thesizes of the dc voltage wellsprings of all H-extensionsare equivalent while in the awry sorts, the estimationsof the dc voltage wellsprings of all H-scaffolds aredistinctive. As of late, a few topologies with differentcontrol methods have been introduced for fellmultilevel inverters [5]–[8]. In [4] and [9]–[15],distinctive symmetric fell multilevel inverters havebeen exhibited. The primary preferred standpoint of

every one of these structures is the low assortment of dcvoltage sources, which is a standout amongst the mostimperative components in deciding the cost of theinverter. Then again, on the grounds that some of themutilize a high number of bidirectional power switches, ahigh number of protected entryway bipolar transistors(IGBTs) are required, which is the primary hindrance ofthese topologies. A lopsided topology has beenexhibited in [16]. The primary inconvenience of thisstructure is identified with its bidirectional powerswitches, which cause an expansion in the quantity ofIGBTs and the aggregate cost of the inverter. In [15],another topology with three calculations have beenexhibited, which decrease the quantity of requiredpower switches yet increment the assortment of dcvoltage sources. In [1], [4] and [17], and [18], a fewcalculations for deciding the extents of dc voltagehotspots for the customary fell multilevel inverter havebeen exhibited. The significant preferred standpoint ofthis topology and its calculations is identified with itscapacity to produce an impressive number of yieldvoltage levels by utilizing a low number of dc voltagesources and power switches yet the high assortment inthe extent of dc voltage sources is their most wonderfulweakness. In this paper, with a specific end goal toexpand the quantity of yield voltage levels and diminishthe quantity of energy switches, driver circuits, and theaggregate cost of the inverter, another topology of fellmultilevel inverters is proposed. It is critical to note thatin the proposed topology, the unidirectional powerswitches are utilized. At that point, to decide the size ofthe dc voltage sources, another calculation is proposed.Also, the proposed topology is contrasted and differenttopologies from various perspectives, for example, thequantity of IGBTs, number of dc voltage sources, theassortment of the estimations of the dc voltage sources,and the estimation of the blocking voltages per switch.At long last, the execution of the proposed topology increating all voltage levels through a 49 - level inverteris affirmed by MATLAB reenactment.

II. PROPOSEDTOPOLOGY










I. INTRODUCTION














I. INTRODUCTION







In Fig. 1, two new topologies are proposed fora seven-level inverter [19]. As appeared in Fig. 1, theproposed topologies are gotten by including twounidirectional power switches and one dc voltagesource to the H-connect inverter structure. At the end ofthe day, the proposed inverters are included sixunidirectional power switches ( , , , , , , , ,, ) and two dc voltage sources ( , , ). Inthis paper, these topologies are called developed H-bridge. As shown in Fig. 1, the simultaneous turn-on of, , ( , , )

Fig. 1. Proposed seven-level inverters. (a) Firstproposed topology. (b) Second proposed topology.

No.

, , , , ( .1( )) ( .1( ))1 1 0 0 1 0 1 , ,2 1 0 0 1 1 0 , − ,3 1 0 1 0 0 1 , − , , + ,4 1 0 1 0 1 0 0 0

0 1 0 1 0 15 0 1 1 0 1 0 − , − ,6 0 1 1 0 0 1 − , ,7 0 1 0 1 1 0 -( , −, )

-( , +, )

causes the voltage sources to short-circuit. Therefore,the simultaneous turn-on of the mentioned switchesmust be avoided. In addition, and should not turnon, simultaneously. The distinction in the topologiesdelineated in Fig. 1 is in the association of the dcvoltage sources extremity. Table I demonstrates theyield voltages of the proposed inverters for variousconditions of the switches. In this table, 1 and 0 showthe ON-and OFF-conditions of the switches,individually. As it is evident from Table I, if theestimations of the dc voltage sources are equivalent, thequantity of voltage levels abatements to three. Alongthese lines, the estimations of dc voltage sources oughtto be distinctive to create more voltage levels withoutexpanding the quantity of switches and dc voltagesources. Considering Table I, to produce all voltage

levels (odd and even) in the proposed topologyappeared in Fig. 1(a), the extents of〖 V〗_(L,1) andV_(R,1) ought to be viewed as 3pu and 1pu, separately.Thus, for the topology appeared in Fig. 1(a), the extentsof V_(L,1) and V_(R,1) ought to be viewed as 2pu and1pu, individually. Considering the previouslymentioned clarifications, the aggregate cost of theproposed topology in Fig. 1(b) is low since dc voltagesources with low sizes are required. By building up theseven-level inverter appeared in Fig. 1(b), the 31-levelinverter appeared in Fig. 2 can be proposed. Thistopology comprises of ten unidirectional powerswitches and four dc voltage sources. As per Fig. 2, ifthe power switches of (S_(L,1),S_(L,2)),(S_(L,3),S_(L,4)), (S_(R,1),S_(R,2)), and(S_(R,3),S_(R,4)) turn on all the while, the dc voltagesources ofV_(L,1),V_(L,2),V_(R,1), and V_(R,2) willbe shortcircuited, individually. Consequently, theconcurrent turn-on of these switches ought to be keptaway from. In addition, and should not turn onsimultaneously. It is important to note that the 127-leveltopology can be provided through the structurepresented in Fig. 1(a), where the only difference will bein the polarity of the applied dc voltage sources. Bydeveloping the proposed 49th level inverter, a 49th -level inverter can be proposed as shown in Fig. 3. Thistopology

Fig. 3. Proposed 49-level inverter.

Fig. 4. Proposed general topology.



consists of 14 unidirectional power switches and 6 dcvoltage sources. Similarly, by developing the proposedbasic topology, a general topology, as shown in Fig. 4,can be proposed. The general topology consists of 2dc voltage sources ( is the number of the dc voltagesources on each leg) and 4 + 2 unidirectional powerswitches. In the proposed general topology, the numberof output voltage levels( ), number ofswitches ( ), number of dc voltagesources( ), and the maximum magnitude of thegenerated voltage ( , ) are calculated as follows,respectively: = 2 − 1

------------ (1)= 4 + 2----------- (2)= 2

------------ (3), = , + ,------------- (4)

The other important parameters of the total cost of amultilevel inverter for evaluation are the variety of thevalues of dc voltage sources and the value of theblocking voltage of the switches. As the variety of dcvoltage sources and the value of the blocking voltage ofthe switches are low, the inverter’s total cost decreases[20]. The number of variety of the values of dc voltagesources is given by= 2

----------- (5)The following pattern is utilized to calculate themaximum magnitude of the blocking voltage of thepower switches. As shown in Fig. 1(b), the blockingvoltage of , and , are calculated as follows:, = , = ,

----------- (6)Where , and , indicate the maximum blockingvoltages of , and , , respectively. The blockingvoltage of , and , are as follows:

, = , = ,----------- (7)

Where , and , indicate the maximum blockingvoltages of , and , , respectively. Therefore, themaximum blocking voltage of all switches in theproposed seven-level inverter ( , )is calculated asfollows: , = , + , + , + , + += 4( , + , )

----------- (8)

Considering Fig. 2, the maximum blocking voltage ofthe switches is as follows:, = , = ,

------------ (9), = , = , − ,----------- (10), = , = ,

--------------- (11), = , = , − ,---------------(12)= = , + ,

------- (13)Therefore, the maximum blocking voltage of allswitches of the proposed 31-level inverter( , )is asfollows:, = , + , + , + , + , + ,+ , + , + += 4( , + , )

--------- (14)Similarly, the maximum blocking voltage of allswitches of the 49-level inverter is calculated asfollows: , = 4( , + , )

----------- (15)Finally, the maximum blocking voltage of all theswitches of the general topology , is calculatedas follows: , = 4( , + , )

------------ (16)

III. PROPOSED ALGORITHM TO DETERMINETHE MAGNITUDES OF DC VOLTAGE SOURCES

In this paper, the following algorithm is applied todetermine the magnitude of dc voltage sources. It isimportant to note that all voltage levels (even and odd)can be generated.

A. Proposed 49-Level InverterThe magnitudes of the dc voltage sources of theproposed 127-level inverter are calculated as follows:, =

----------- (17), = 2----------- (18), = 5----------- (19), = 10----------- (20), = 25---------- (21), = 50---------- (22)



By using this algorithm, the inverter can generate allnegative and positive voltage levels from 0 to 63with steps of

D. Proposed General Multilevel InverterThe magnitudes of the dc voltage sources of theproposed general multilevel inverter can be obtained asfollows: = 5 = 1,2,3, … . ,

--------- (23)= 2 × 5 = 1,2,3, … . ,------------- (24)

Considering (4) and (16), the values of, and , of the proposed general multilevelinverter are as follows, respectively:, = , + , = 3 × 5

---------- (25), = 4 , + , = 12(5 )----------- (26)

IV. CALCULATION OF LOSSES

Mainly, two kinds of losses (i.e., conduction andswitching losses) are associated with the switches.Since the switches include IGBTs and diodes, theconduction losses of an IGBT ( , ( )) and a diode( , ( )) are calculated as follows, respectively [7],[22]: , ( ) = + ( ) ( )

----------- (27), ( ) = + ( ) ( )------------ (28)

Where and are the forward voltage drops ofthe IGBT and diode, respectively. and are theequivalent resistances of the IGBT and diode,respectively, and is a constant related to thespecification of the IGBT. Considering that at instant ,there are transistors and diodes in the currentpath, the average value of the conduction powerloss ( ) of the multilevel inverter can be written asfollows:= 12 [ ( ) , ( ) + ( ) , ( )]

------------ (29)The switching losses are calculated based on the energyloss calculation. The switching losses occur during theturn-off and turn-on periods. For simplicity, the linearvariations of the voltage and current of the switches inthe switching period are considered. Based on thisassumption, the following relations can be written [7],[22]:

, = ( ) ( ) = 16 ,---------- (28)

, = ( ) ( ) = 16 , ′

---------- (29)Where , and , are the turn-off and turn-onlosses of the switch , respectively. and are theturn-off and turn-on times of the switch,respectively, is the current through the switch beforeturning off, ′ is the current through the switch afterturning on, and , is the OFF-state voltage on theswitch. The switching power loss ( ) is equal to thesum of all turn-on and turn-off energy losses in afundamental cycle of the output voltage. This can bewritten as follows [7], [22]:= , + ,,,

----------- (30)Where is the fundamental frequency and , and, are the numbers of turn-on and turn-off of theswitch during a fundamental cycle. Also, , is theenergy loss of the switch during the ℎ turn-on and, is the energy loss of the switch during the ℎturn-off. The total loss( )of the multilevel converteris the sum of the conduction and switching losses asfollows: = +

-------- (31)Finally, the efficiency ( ) of the inverter is calculatedas follows: = = +

---------- (32)Where and denote the output and input powersof the inverter.

V. COMPARING THE PROPOSED GENERALTOPOLOGY WITH THE CONVENTIONAL

TOPOLOGIES

In order to clarify the advantages and disadvantage ofthe proposed topology, it should be compared with thedifferent kinds of topologies presented in literature. In[4], the conventional cascaded multilevel inverter withtwo different algorithms has been presented. Thesealgorithms are known as the symmetric cascadedmultilevel inverters and the asymmetric ones with thebinary method for determining the magnitude of dcvoltage sources. In the comparison, the conventionalsymmetric cascaded multilevel inverter is indicated by


www.ijseat.com * Corresponding Author 60

and the conventional binary asymmetric cascadedmultilevel inverter is shown by . Three otheralgorithms have been presented for this topology in [1],[17], and [18], which are indicated by – ,respectively. Moreover, another topology with threedifferent algorithms for determining the value of dcvoltage sources has been introduced in [15], which areshown by – in this comparison. In [9]–[12], fourdifferent structures for the cascaded multilevel inverterhave been presented, and in this paper, they areindicated by – and – . It is important tonote that the power switches in the aforementionedtopologies are unidirectional. In addition, othertopologies based on bidirectional switches have beenpresented in [13] and [14]. In [14], three differentalgorithms have been recommended, which are denotedas – , and the presented topology in [13] isindicated by in this comparison. Fig. 5 shows all ofthe aforementioned structures. Fig. 6 compares thenumber of IGBTs of the proposed general topologywith the aforementioned cascaded multilevel inverters.It is obvious that the proposed inverter requires a lessernumber of IGBTs in comparison with the othermentioned topologies to generate particular levels. Fig.7 compares the number of dc voltage sources of theproposed inverter with the aforementioned cascadedmultilevel inverter. As shown in Fig. 7, the proposedinverter has better performance in comparison with theother presented topologies except the topologypresented in . However, the magnitude of the dcvoltage sources in is a little more than that of theproposed topology.Fig. 8 compares the variety of magnitudes of the dcvoltage sources of the proposed inverter with that of theaforementioned cascaded multilevel inverter.Obviously, the proposed inverter uses a wider variety ofmagnitudes of the dc voltage sources in comparisonwith those of all the aforementioned topologies. Thisfeature is the most important disadvantage of theproposed topology because the variety of the values ofdc voltage sources is as one of the remarkable factors indetermining the cost of the inverter. However, thisfeature in the proposed topology is similar to thepresented topologies ofand . Fig. 9 compares the magnitude of the blockingvoltage of the switches of the proposed inverter withthat of the aforementioned cascaded multilevel inverter.This figure shows the reduction of the magnitude of theblocking voltage of the proposed inverter in comparisonwith those of all the aforementioned multilevelinverters.

VI. SIMULATION RESULTS

In order to verify the correct performance of theproposed multilevel inverter in generating all outputvoltage levels (even and odd), a 49-level inverter basedon the topology shown in Fig. 2 has been used for thesimulation. Table II shows the switching states of the49-level inverter.

Fig. 11 49 level voltage and currentThe simulation is done by using MATLAB software,and the practical prototype is made in the experimentalenvironment. Fig. 10 shows the experimental setup. It isimportant to note that the IGBTs used in the prototypeare HGTP10N40CID (with an internal anti-paralleldiode) with the voltage and current ranges of 400 V and10 A, respectively. The 89C52 microcontroller byATMEL Company has been used to generate allswitching patterns. In all processes of the simulationand experiment, the load is assumed as R–L with R=45Ωand L=55mH. Moreover, the magnitude ofVL,1 isconsidered 15 V, so based on (29) and (30), themagnitudes of the other dc voltage sources will be 30,75, and 150 V, which are related toVR,1,VL,2,andVR,2, respectively. According to (31), themaximum output voltage of this inverter will be 225 V.In this paper, the fundamental frequency switchingcontrol method has been used [21]. In this method, thesinusoidal reference voltage is compared with theavailable dc voltage levels and the level that is nearestto the reference voltage is chosen [22]. The mainadvantage of this control method is related to its lowswitching frequency, which leads to reduction ofswitching losses. The simulated output voltage andcurrent waveforms are shown in Fig. 11. As Fig. 11(a)shows, the proposed topology is able to generate 31levels (15 positive levels, 15 negative levels, and 1 zerolevel) with the maximum voltage of 225 V. Comparingthe output voltage and current waveforms indicates thatthe output current waveform is more similar to the idealsinusoidal waveform than the output voltage becausethe R–L load acts as a low-pass filter. In addition, thereis a phase difference between the output voltage andcurrent waveforms, which is caused by the inductivefeature of the load. The total harmonic distortions of theoutput voltage and current are equal to 0.94% and0.19%, respectively. Fig. 12(a) and (b) shows the



harmonic spectrum of the output voltage and current,respectively. The figure shows that the magnitudes ofharmonics of both voltage and current waveforms arelow. However, the harmonics of the current waveformare lower than the voltage

(a) Harmonic spectrum of output voltage of 31 levelinverter

(b)Fig. 12. Harmonic spectrum of (a) output voltage of 49level inverter

considered nonlinear. In the test condition, themeasured input and output powers are about 1203 and1112 W, respectively. Therefore, the efficiency is about92.4%. Based on the loss calculations given before, thepower loss is about 86 W. Therefore, the calculated losshas a good accordance with the measured efficiency. Asmentioned before, the power switches in the proposedtopology are unidirectional from the voltage viewpoint.

In order to prove this issue, the voltages on the switchesof a single leg of the inverter( . . , , , , , , , , , ) are shown in Fig. 13.As can be seen, the maximum blocking voltage byswitches , , , , , , , , are equal to 15, 15,60, 60, and 225 V, respectively. Obviously, the voltagevalues are zero or equal to the positive ones, which iswell in accordance to the unidirectional feature of theswitches from the voltage view point. Considering themagnitude of the blocking voltage of the switches, therelations associated to the maximum voltage drop of theswitches are well confirmed. Fig. 14 shows theexperimental results of the implemented inverter. It isimportant to note that there is a good agreementbetween the experimental and simulation results.

VII. CONCLUSIONIn this paper, two basic topologies have been

proposed for multilevel inverters to generate sevenvoltage levels at the output. The basic topologies can bedeveloped to any number of levels at the output wherethe 49-level and general topologies are consequentlypresented. In addition, a new algorithm to determine themagnitude of the dc voltage sources has been proposed.The proposed general topology was compared with thedifferent kinds of presented topologies in literaturefrom different points of view. According to thecomparison results, the proposed topology requires alesser number of IGBTs, power diodes, driver circuits,and dc voltage sources. Moreover, the magnitude of theblocking voltage of the switches is lower

Fig. 13. Voltages of switches (a) SL,1 , (b) SL,2

than that of conventional topologies. However, theproposed topology has a higher number of variety of dc



voltage sources in comparison with the others. Theperformance accuracy of the proposed topology wasverified through the MATLAB simulation and theexperimental results of a 49-level inverter.

REFERENCES[1] Ebrahim Babaei, Member, IEEE, Somayeh Alilu,and Sara Laali, Student Member, IEEE” A NewGeneral Topology for Cascaded Multilevel InvertersWith Reduced Number of Components Based onDeveloped H-Bridge” IEEE TRANSACTIONS ONINDUSTRIAL ELECTRONICS, VOL. 61, NO. 8,AUGUST 2014

[2] E. Babaei and S. H. Hosseini, “Charge balancecontrol methods for asymmetrical cascade multilevelconverters,” inProc. ICEMS, Seoul, Korea, 2007, pp.74–79.[3] K. Wang, Y. Li, Z. Zheng, and L. Xu, “Voltagebalancing and fluctuationsuppression methods offloating capacitors in a new modular multilevelconverter,”IEEE Trans. Ind. Electron., vol. 60, no. 5,pp. 1943–1954, May 2013.[4] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “Anew topology of cascaded multilevel converters withreduced number of components for high-voltageapplications,”IEEE Trans. Power Electron., vol. 26, no.11, pp. 3109–3118, Nov. 2011.[5] M. Manjrekar and T. A. Lipo, “A hybrid multilevelinverter topology for drive application,” inProc. APEC,1998, pp. 523–529.[6] M. Narimani and G. Moschopoulos, “A novelsingle-stage multilevel type full-bridge converter,”IEEETrans. Ind. Electron., vol. 60, no. 1, pp. 31– 42, Jan.2013.[7] N. Abd Rahim, M. F. Mohamad Elias, and W. P.Hew, “Transistor-clamped H-bridge based cascadedmultilevel inverter with new method of capacitorvoltage balancing,”IEEE Trans. Ind. Electron., vol. 60,no. 8, pp. 2943–2956, Aug. 2013.[8] S. R. Pulikanti, G. Konstantinou, and V. G.

Agelidis, “Hybrid seven-level cascaded active neutral-point-clamped-based multilevel converter under SHE-PWM,”IEEE Trans. Ind. Electron., vol. 60, no. 11, pp.4794–4804, Nov. 2013.[9] Y. Hinago and H. Koizumi, “A single-phasemultilevel inverter using switched series/parallel dcvoltage sources,”IEEE Trans. Ind. Electron., vol. 57,no. 8, pp. 2643–2650, Aug. 2010.[10] G. Waltrich and I. Barbi, “Three-phase cascadedmultilevel inverter using power cells with two inverterlegs in series,”IEEE Trans. Ind. Appl., vol. 57, no. 8,pp. 2605–2612, Aug. 2010.

[11] W. K. Choi and F. S. Kang, “H-bridge basedmultilevel inverter using PWM switching function,”inProc. INTELEC, 2009, pp. 1–5.[12] E. Babaei, M. Farhadi Kangarlu, and F. NajatyMazgar, “Symmetric and asymmetric multilevelinverter topologies with reduced switchingdevices,”Elect. Power Syst. Res., vol. 86, pp. 122–130,May 2012.[13] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian,“A new multilevel converter topology with reducednumber of power electronic components,” IEEE Trans.Ind. Electron., vol. 59, no. 2, pp. 655–667, Feb. 2012.[14] E. Babaei, S. H. Hosseini, G. B. Gharehpetian, M.Tarafdar Haque, and M. Sabahi, “Reduction of DCvoltage sources and switches in asymmetricalmultilevel converters using a novel topology,”Elect.Power Syst. Res., vol. 77, no. 8, pp. 1073–1085, Jun.2007.[15] E. Babaei and S. H. Hosseini, “New cascadedmultilevel inverter topology with minimum number ofswitches,”Energy Convers. Manage., vol. 50, no. 11,pp. 2761–2767, Nov. 2009.[16] S. Mekhilef and M. N. Kadir, “Voltage control ofthree-stage hybrid multilevel inverter using vectortransformation,”IEEE Trans. Power Electron., vol. 25,no. 10, pp. 2599–2606, Oct. 2010.[17] A. Rufer, M. Veenstra, and K. Gopakumar,“Asymmetric multilevel converter for high resolutionvoltage phasor generation,” presented at the Proc. EPE,Lausanne, Switzerland, 1999.[18] S. Laali, K. Abbaszades, and H. Lesani, “A newalgorithm to determine the magnitudes of dc voltagesources in asymmetrical cascaded multilevel converterscapable of using charge balance control methods,”inProc. ICEMS, Incheon, Korea, 2010, pp.

design and implementation of modular multilevel inverter ... · design and implementation of...

Documents