design and implementation of aynchronous fifo
TRANSCRIPT
DESIGN AND
IMPLEMENTATION OF
ASYNCHRONOUS FIFO
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Under the guidance of:
Smt. S. JyothiAssociate Professor,
Dept. of E and C,
PESCE, Mandya.
Agenda
Project Proposal
Project End Goal
Project sub tasks
Project Implementation
Expected duration and team size
Project Proposal
Domain: Application Specific Integrated
Circuits (ASIC) – VLSI
Objective: To Design and Implement an
Asynchronous FIFO and to get ourselves
familiar with the VLSI design flow and to
apply various design optimization
techniques in terms of speed, power and
area.
Proposed End Goal
To design and implement First In First
Out (FIFO) of size 128x8 and to impose
optimization techniques for the area,
power and timing.
Also to do a well established physical
design of FIFO using Cadence tool.
Learning Cadence tool.
Sub Task
Learning ASIC flow.
To get our self familiar with Verilog
Hardware Description Language
(HDL).
To get our self familiar with Cadence
Tool for VLSI.
ASIC
Design
specification
Behavioral
description
Functional
verification
Logic
synthesis Logical
description
(HDL)
Floor
planning
Place and
route
Layout
Physical
verification
and STA
Logic
verification
and STA
Fab Front end
Back end
Physical Design
Design specification
High level representation of the system
Performance, functionality and physical
dimensions (size of the die)
Fabrication technology and design
techniques
Architecture of the system is also defined
Behavioral description
Algorithmic description of the system
Main functional units are identified
Expected behavior of the design for the
inputs are defined
Behavior in terms of output, input and
timing
Logical description
Control flow, words width, register
width, arithmetic and logical operations,
represents the functional design
Register Transfer Level (RTL)
VHDL, verilog
Simulated and verified
Functional verification
RTL is simulated with the various
simulators available
Modelsim (Mentor graphics), NC sim
(Cadence), VCS(Synopsys)
Functionality and responses of the design
for input patterns are verified
Logic synthesis
RTL to gate level netlist
Netlist – Defines gates and their inter
connections
Synthesif flow,
• Translate
• Mapping
• Optimization
Logic verification and STA
Functionality of synthesized logic is
verified
Netlist and RTL compared to chek
whether they are logically equal
STA – Static Timing analysis, design
timing is verified (to make sure, the
design operates in specific frequency)
Floor planning
Shape of the design is defined
Orientation and co-ordinates of IO pins
are defined
Power planning is done to make sure
proper power distribution to the entire
design
Placement
Process of determining the location of each
cell (gate or block) in the netlist
Traditional objectives
• Wire length
• Timing and
• Congestion
Recently thermal hotspot, power consumption
and power supply noise drew much attention
CTS
Building of clock network
Object is to minimize clock latency and
minimize skew
Make sure that clock is reaching all the
flops with minimum delay
Routing
Interconnection or standard cells and
macros and other sub modules
Done in two steps,
• Global routing – estimation of wire length
and virtual routing
• Detail routing – Actual routing
First in First out (FIFO)
FIFO describes the principle of a queueprocessing technique or servicingconflicting demands by ordering processby First Come First Served (FCFS)behavior: what comes in first is handledfirst, what comes in next waits until the firstis finished.
Types of FIFO are 1. Asynchronous and
2. Synchronous
Asynchronous FIFO
An asynchronous FIFO refers to a FIFOdesign where data values are written to aFIFO buffer from one clock domain and thedata values are read from the same FIFObuffer from another clock domain, wherethe two clock domains are asynchronous toeach other.
Asynchronous FIFOs are used to safely passdata from one clock domain to anotherclock domain.
Applications of FIFO
For buffering and flow control which is
from hardware to software.
Used to safely pass data from one clock
domain to another clock domain.
Design and Implementation
We do both logical and physical design
starting from our own Design
specifications, Register – Transfer Level
(RTL) coding using Verilog and end the
process by generating Graphic Database
System Information Interchange(GDSII )
file using Cadence Tool.
Design and Implementation (contd..)
Logical Design:
We verify our design of Verilog test bench file using
Cadence Native Code compiler Simulator (ncsim).
We do synthesis and optimization of our design with
the help of Cadence RTL Compiler (rc). For that we
give the following files as input.
• Verilog design files and test bench.
• Design constraint file written by us (It is also
called as .sdc or .g file).
• Libraries.
Design and Implementation (contd..)
Physical Design:
For the physical design, we use Cadence SOC
Encounter tool.
The physical design includes floor planning, power
planning, placement, CTS (Clock Tree Synthesis),
routing and the generation of GDSII file.
In this physical design part, we concentrate on timing
optimization and power optimization. Power
optimization includes,
• Dynamic power optimization using clock
gating
• Leakage power optimization using multi –
threshold voltage cells.
THANK YOU