department of computing and technology iqra university

CROSS LAYER TIME SYNCHRONIZATION

IN WIRELESS SENSOR NETWORKS

Engr. Syed Muhammad Usman Hashmi

051-11-14473

A Thesis Submitted in

Partial Fulfillment of the

Requirements for the Degree of

Doctorate of Philosophy in Telecommunication and Networks

Department of Computing and Technology

Iqra University, Islamabad Campus

2015

In The Name Of Allah,

The Most Beneficent

The Most Merciful

Read; In The Name Of Your Lord

Who Created, Created Man From

A Clot

Read; And Your Lord Is

The Most Bounteous

Who Taught By The Pen

Taught Man That Which

He Did Not Know

Al-Quran

THESIS BRIEF

THESIS TITLE

Cross Layer Time Synchronization in Wireless Sensor Network

SUPERVISED BY

Dr. Qasim Mahmood Chaudhari

Engr. Syed Muhammad Usman Hashmi Reg No. 051-11-14473

Ph.D. (Telecommunication & Networks) Department of Computing & Technology

IQRA University Islamabad Campus

Dedication

To my parents, wife, teachers & friends

whose prayers & consultation enabled me

to have such a wonderful thesis

Acknowledgements

Thanks to Almighty ALLAH, The Merciful, The Beneficent, whose bountiful blessings

and exaltation flourished my thoughts and thrived my ambitions to have the cherish

fruit of my modest efforts in the form of this thesis. I offer my humblest thanks from the

core of my heart to the holy Prophet (Peace be upon Him) who is forever a model of

guidance and knowledge for humanity. I feel great depth of obligation for my loving

parents specially my father (Syed Pervaiz Hashmi), mother (Yasmin Farhat) and wife

(Nadia Usman) whose prayers have enabled me to reach at this stage and my son

(Syed Muhammad Zarrar Hashmi) for his sacrifices when baba is busy doing his PhD

.

I owe a special debt of gratitude to my reverend supervisor Dr. Qasim Mahmood for

their invaluable guidance, expert advices, co-operation, encouraging attitude, positive

criticism and healthy suggestions. I also wish to record my sincere appreciations to

Dr. Affan Ahmad, Dr. Imran Shafi, Dr. Islam, Dr. Basheer Samin, Dr. Jamil Ahmed and

Dr. Ismail Shah for their support and guidance.

I express my great respect to all my friends, who extended their full support and every

possible help during my analysis of the existing project.

ENGR. SYED MUHAMMAD USMAN HASHMI

i

ABSTRACT

Accomplishing synchronized time remains an essential task for most disseminated networks.

Time synchronization obliges an exceptional blend of high precision and energy efficiency. A

few application layer protocols have been proposed to meet these necessities. This research

work endorse that the symbol timing recuperation procedure can give application layer clock

skew estimate and the application layer clock can be amended with the assistance of this

estimate. This cross layer methodology diminishes the quantity of message trades needed by

application layer for time synchronization which stimulates energy preservation. It contends

that such a cross layer methodology can give a more exact skew estimation, or on the other

hand can accomplish more noteworthy energy efficiency, for a given precision, by diminishing

the message trades. Examination of proposed strategy, simulation results, experimentation

outcomes and mathematical analysis demonstrates that physical layer clock skew can be

utilized to adjust application layer clock skew as they are derived from hardware clock within

the node. Analysis of proposed method provides concrete bounds on achieved improvement.

ii

CONTENTS

List of Figures ...................................................................................................................... xi

Chapter # 1 ........................................................................................................................... 1

Introduction .......................................................................................................................... 1

1.1 Overview ..................................................................................................................... 1

1.2 Cross Layer Approach ................................................................................................. 3

1.3 Organization of Thesis ................................................................................................. 4

Chapter # 2 ........................................................................................................................... 5

Ad Hoc & Sensor Networks .................................................................................................. 5

2.1 Ad Hoc Networks ........................................................................................................ 5

2.2 Mobile Ad hoc NETwork ............................................................................................ 5

2.2.1 Challenges ............................................................................................................ 6

2.2.1.1 Scalability ...................................................................................................... 6

2.2.1.2 Routing .......................................................................................................... 6

2.2.1.3 Security .......................................................................................................... 6

2.2.1.4 Services ......................................................................................................... 6

2.2.1.5 Energy Conservation ...................................................................................... 6

2.2.1.6 Internetworking .............................................................................................. 7

iii

2.2.1.7 Time Synchronization .................................................................................... 7

2.2.1.8 Reliability ...................................................................................................... 7

2.2.1.9 Interoperation ................................................................................................. 7

2.2.2 Applications ......................................................................................................... 7

2.3 Wireless Sensor Network ............................................................................................ 8

2.3.1 Types of Wireless Sensor Network ....................................................................... 8

2.3.1.1 Structured WSN ............................................................................................. 8

2.3.1.2 Unstructured WSN ......................................................................................... 8

2.3.2 Sensors ................................................................................................................. 8

2.3.2.1 Mote .............................................................................................................. 9

2.3.2.2 Energy Consumption ...................................................................................... 9

2.3.2.2.1 Transducer ............................................................................................ 10

2.3.2.2.2 Transceiver ........................................................................................... 10

2.3.2.2.3 Processing and Memory Operations ...................................................... 10

2.3.3 Challenges .......................................................................................................... 10

2.3.3.1 Energy Conservation .................................................................................... 10

2.3.3.2 Node Cost .................................................................................................... 11

2.3.3.3 Scalability .................................................................................................... 11

2.3.3.4 Self Organization ......................................................................................... 11

2.3.3.5 Security ........................................................................................................ 11

iv

2.3.3.6 Reliability .................................................................................................... 11

2.3.3.7 Routing ........................................................................................................ 12

2.3.3.8 Clock Synchronization ................................................................................. 12

2.3.4 Applications ....................................................................................................... 12

2.3.4.1 Military Applications ................................................................................... 12

2.3.4.2 Habitat Applications .................................................................................... 13

2.3.4.3 Environment Applications ............................................................................ 13

2.3.4.4 Health Applications ..................................................................................... 13

2.3.4.5 Miscellaneous Applications.......................................................................... 13

Chapter # 3 ......................................................................................................................... 15

Application Layer Clock Synchronization ........................................................................... 15

3.1 Application layer clock .............................................................................................. 15

3.1.1 Imprecisions of clock .......................................................................................... 15

3.1.1.1 Phase error ................................................................................................... 16

3.1.1.2 Frequency error ............................................................................................ 16

3.1.1.3 Phase and Frequency error ........................................................................... 17

3.1.1.4 Perfect Clocks .............................................................................................. 18

3.1.2 Clock Adjustments ............................................................................................. 19

3.1.2.1 Clock Correction .......................................................................................... 19

3.1.2.1.1 Instantaneous Correction ....................................................................... 19

v

3.1.2.1.2 Continuous Correction .......................................................................... 20

3.1.2.2 Untethered Clocks ........................................................................................ 20

3.1.3 Global Time Access ............................................................................................ 20

3.1.3.1 Installation of GPS in all Nodes ................................................................... 20

3.1.3.2 Using Synchronization Protocols.................................................................. 20

3.2 Synchronization ......................................................................................................... 20

3.2.1 Critical Metrics ................................................................................................... 21

3.2.1.1 Precision ...................................................................................................... 21

3.2.1.2 Efficiency .................................................................................................... 21

3.2.1.3 Lifetime ....................................................................................................... 21

3.2.1.4 Cost ............................................................................................................. 21

3.2.1.5 Scope and Availability ................................................................................. 22

3.2.2 Significance ............................................................................................................ 22

3.3 Clock Synchronization Protocols ............................................................................... 22

3.3.1 Wired Network Clock Synchronization ............................................................... 22

3.3.1.1 Network Time Protocol ................................................................................ 23

3.3.1.2 Simple Network Time Protocol .................................................................... 24

3.3.1.3 Precision Time Protocol ............................................................................... 24

3.3.1.4 Time Transmission Protocol ......................................................................... 25

3.3.1.5 Miscellaneous Protocols ............................................................................... 25

vi

3.3.2 Wireless Network Clock Synchronization ........................................................... 25

3.3.2.1 Reference Broadcast Synchronization Protocol ............................................ 26

3.3.2.2 Romer’s Protocol ......................................................................................... 27

3.3.2.3 Timing-sync Protocol for Sensor Networks .................................................. 27

3.3.2.4 Flooding Time Synchronization Protocol ..................................................... 28

3.3.2.5 Miscellaneous Protocols ............................................................................... 30

3.3.2.6 Limitations of Current State of the Art and Motivation ................................. 30

3.4 Clock Synchronization in WSN ................................................................................. 31

3.4.1 Challenges .......................................................................................................... 31

3.4.2 Synchronization Performance ............................................................................. 31

3.4.3 Synchronization Concerns .................................................................................. 31

3.4.4 Comparison of RBS, TPSN and FTSP ................................................................ 32

Chapter # 4 ......................................................................................................................... 34

Physical Layer Time Synchronization ................................................................................. 34

4.1 Physical Layer Clock ................................................................................................. 34

4.1.1 Imperfections ...................................................................................................... 34

4.1.1.1 Timing Phase Offset..................................................................................... 35

4.1.1.2 Timing Frequency Offset ............................................................................. 35

4.2 Communication Systems ........................................................................................... 35

4.2.1 Pulse Amplitude Modulation System .................................................................. 36

vii

4.2.2 Quadrature Amplitude Modulation System ......................................................... 37

4.2.3 Miscellaneous Modulation Schemes ................................................................... 38

4.2.4 Significance of Symbol Timing Recovery ........................................................... 38

4.3 Time Synchronization................................................................................................ 38

4.3.1 Feedback Time Synchronization ......................................................................... 39

4.3.2 Discrete Time Feedback Symbol Timing Synchronization .................................. 39

4.4 Components of Symbol Timing Synchronization ....................................................... 40

4.4.1 Timing Error Detector ........................................................................................ 40

4.4.1.1 Maximum Likelihood Timing Error Detector ............................................... 40

4.4.1.1.1 Error Signal ........................................................................................... 41

4.4.1.1.2 Structure................................................................................................ 41

4.4.1.2 Early Late Timing Error Detector ................................................................. 41

4.4.1.2.1 Error Signal ........................................................................................... 41

4.4.1.2.2 Structure................................................................................................ 42

4.4.1.3 Zero Crossing Timing Error Detector ........................................................... 42

4.4.1.3.1 Error Signal ........................................................................................... 42

4.4.1.3.2 Structure................................................................................................ 43

4.4.1.4 Gardner Timing Error Detector .................................................................... 43

4.4.1.4.1 Error Signal ........................................................................................... 43

4.4.1.4.2 Structure................................................................................................ 43

viii

4.4.1.5 Mueller and Muller Timing Error Detector ................................................... 44

4.4.1.4.1 Error Signal ........................................................................................... 44

4.4.1.4.2 Structure................................................................................................ 44

4.4.2 Interpolator ......................................................................................................... 44

4.4.2.1 Piecewise Polynomial Interpolation ............................................................. 45

4.4.2.1.1 Linear Interpolation ............................................................................... 45

4.4.2.1.2 Cubic Interpolation ................................................................................ 46

4.4.3 Interpolation Control........................................................................................... 46

4.4.3.1 Basepoint Index ........................................................................................... 47

4.4.3.2 Fractional Interval ........................................................................................ 47

4.4.3.3 Design ......................................................................................................... 47

4.4.4 Loop Filter .......................................................................................................... 48

Chapter # 5 ......................................................................................................................... 49

Cross Layer Time Synchronization...................................................................................... 49

5.1 Cross Layer Approach ............................................................................................... 49

Chapter # 6 ......................................................................................................................... 56

Simulation, Experimentation and Results ............................................................................ 56

6.1 Simulation ................................................................................................................. 56

6.2 Experimentation ........................................................................................................ 62

6.3 Mathematical Analysis .............................................................................................. 75

ix

6.3.1 Energy Efficiency ............................................................................................... 75

6.3.2 Cramer-Rao Lower Bound and Symbol Rate ...................................................... 78

6.3.3 Cross Layer Packet ............................................................................................. 79

6.3.4 Bayesian Estimation ........................................................................................... 82

6.4 Comparison with FTSP.............................................................................................. 86

Chapter # 7 ......................................................................................................................... 87

Conclusion and Future Work ............................................................................................... 87

Appendix – A ...................................................................................................................... 88

TMS320C6713 DSP Starter Kit .......................................................................................... 88

A.1 Digital Signal Processing Chips ................................................................................ 88

A.2 TMS320C6713 DSP ................................................................................................. 90

A.2.1 Central Processing Unit ..................................................................................... 90

A.2.2 Memory ............................................................................................................. 91

A.2.3 Enhanced Direct Memory Access Controller ...................................................... 91

A.2.4 Serial Ports ........................................................................................................ 91

A.2.5 Miscellaneous Internal Peripherals ..................................................................... 91

A.2.6 Instruction Set .................................................................................................... 91

A.3 TMS320C6713 DSP Starter Kit ................................................................................ 93

Appendix – B ...................................................................................................................... 95

Project Codes ...................................................................................................................... 95

x

B.1 Code at Transmitting Node ....................................................................................... 95

B.2 Code at Receiving Node ........................................................................................... 99

B.3 Pulse Shaping Filter Used ....................................................................................... 108

B.4 Codes for Various Graphs ....................................................................................... 108

Nomenclature .................................................................................................................... 109

References ........................................................................................................................ 111

xi

LIST OF FIGURES

Figure 1 - Time Synchronization at Different Layers ............................................................. 3

Figure 2 - Structure of typical WSN node .............................................................................. 9

Figure 3 - Applications of Wireless Sensor Network ........................................................... 14

Figure 4 - Phase Error in Application Layer Clocks ............................................................. 16

Figure 5 - Frequency Error in Application Layer Clocks ..................................................... 17

Figure 6 - Phase and Frequency Error in Application Layer Clocks ..................................... 18

Figure 7 - Perfect Application Layer Clocks ........................................................................ 19

Figure 8 - Network Time Protocol Hierarchy ...................................................................... 23

Figure 9 - Network Time Protocol Node Synchronization ................................................... 23

Figure 10 - Precision Time Protocol Mater-Slave Architecture ............................................ 24

Figure 11 - Precision Time Protocol Node Synchronization ................................................. 25

Figure 12 - Time Transmission Protocol Node Synchronization .......................................... 25

Figure 13 - Reference Broadcast Synchronization Protocol Deployed Wireless Network ..... 26

Figure 14 - Reference Broadcast Synchronization Protocol Node Synchronization .............. 27

Figure 15 - Romer's Protocol Node Synchronization ........................................................... 27

Figure 16 - Timing-sync Protocol for Sensor Network Architecture .................................... 28

Figure 17 - Timing-sync Protocol for Sensor Network Node Synchronization ..................... 28

Figure 18 - Flooding Time Synchronization Protocol Network Architecture ........................ 29

xii

Figure 19 - Flooding Time Synchronization Protocol Node Synchronization ....................... 29

Figure 20 - Flooding Time Synchronization Protocol Multi Hop Synchronization ............... 30

Figure 21 - Delay Components Effecting Synchronization Performance .............................. 31

Figure 22 - Synchronization Concerns ................................................................................. 32

Figure 23 - RBS, TSPN and FTSP Comparison ................................................................... 33

Figure 24 - Timing Phase Offset between two System Clocks ............................................. 35

Figure 25 - Timing Frequency Offset between two System Clocks ...................................... 35

Figure 26 - Transceiver Block Diagram ............................................................................... 36

Figure 27 - Pulse Amplitude Modulation Transceiver .......................................................... 36

Figure 28 - Quadrature Amplitude Modulation Transceiver ................................................. 37

Figure 29 - Role of Symbol Timing Recovery ..................................................................... 39

Figure 30 - Basic Components of Symbol Timing Recovery ............................................... 39

Figure 31 - Discrete Time Feedback Symbol Timing Synchronization ................................ 40

Figure 32 - Maximum Likelihood Timing Error Detector .................................................... 41

Figure 33 - Early Late Timing Error Detector ...................................................................... 42

Figure 34 - Zero Crossing Timing Error Detector ................................................................ 43

Figure 35 - Gardner Timing Error Detector ......................................................................... 43

Figure 36 - Mueller and Muller Timing Error Detector ........................................................ 44

Figure 37 - Interpolation...................................................................................................... 45

Figure 38 - Interpolation Control ......................................................................................... 48

xiii

Figure 39 - Loop Filter ........................................................................................................ 48

Figure 40 - Binary PAM Symbol Timing Synchronization System for Physical Layer ......... 50

Figure 41 - Time Synchronization at Application Layer using FTSP ................................... 52

Figure 42 - Cross Layer Time Synchronization ................................................................... 54

Figure 43 - Flowcharts of Time Synchronization at Different Layers ................................... 55

Figure 44 – Physical Layer and Application Layer Role in Cross Layer Model ................... 55

Figure 45 - Timing Error and Fractional Interval Over 3000 Symbols at Physical Layer ...... 57

Figure 46 - Slope of fractional interval shows negative skew of -4.9505x10-3 ...................... 58




Figure 50 - Slope of fractional interval shows positive skew of 1.2500x10-3 ........................ 61

Figure 51 - Slope of fractional interval shows positive skew of 1.6667x10-3 ....................... 61



Figure 54 - Experimental Setup ........................................................................................... 62

Figure 55 - Timing Error and Fractional Interval over 22000 Symbols ................................ 63

Figure 56 - Physical Layer frequency Offset Computed for Various Number of Symbols

Transmitted ......................................................................................................................... 64

Figure 57 - Clock Jitter ........................................................................................................ 65

xiv

Figure 58 - Application Layer Clocks of DSK A and DSK B Estimated using LS ............... 66

Figure 59 - Application Layer Frequency Offset computed using various Number of

Timestamps ......................................................................................................................... 67

Figure 60 - Comparison of Application Layer and Physical Layer Frequency Offset ........... 68

Figure 61 - Hardware clock skew of used DSKs .................................................................. 69

Figure 62 - Fractional interval with skew of 3.6042x10-6 ..................................................... 70

Figure 63 - Physical Layer Clock Skew Estimate for Experiment I ...................................... 70


Figure 65 - Physical Layer Clock Skew Estimate for Experiment II .................................... 71

Figure 66 - Hardware clock skew of used DSKs for experiment III and IV ......................... 72


Figure 68 - Physical Layer Clock Skew Estimate for Experiment III ................................... 73


Figure 70 - Physical Layer Clock Skew Estimate for Experiment IV ................................... 74

Figure 71 – Energy Efficiency ............................................................................................. 77

Figure 72 - Required Symbol Rate for Cross Layer Approach ............................................. 79

Figure 73 - Required Symbols for Cross Layer Packet......................................................... 80

Figure 74 - Required Symbols for Cross Layer Packet with Respect to Timestamps used at

Application Layer ............................................................................................................... 81

Figure 75 - Cross Layer Packet ........................................................................................... 82

xv

Figure 76 - Applications of Digital Signal Processing Chips in Various Fields .................... 89

Figure 77 - TMS320C6713 DSP [38] .................................................................................. 90

Figure 78 - Block Diagram of the TMS320C6713 DSP Starter Kit (DSK) [38] ................... 93

Cross Layer Time Synchronization In Wireless Sensor Networks

Introduction 1

CHAPTER # 1

INTRODUCTION

This chapter presents the overview of the research work and key idea of cross layer time

synchronization. It focuses on time synchronization in distributed networks at different layers

and introduces a novel cross layer approach.

1.1 OVERVIEW

Distributed systems need a shared notion of causality to enable coordination. In cyber physical

and sensor networks, due to interaction with physical processes governed by time dependent

laws, the causality notion is strengthened to establish a synchronized notion of time which can

have microsecond precision requirements. Thus, systems can now localize intruders, determine

projectile trajectories and even establish accurate movements.

Establishing this shared notion of time remains a challenge. The notion of time in any

computing device is kept by using an oscillator that produces a periodic signal at known

frequency. The signal is then used to increment a hardware counter, with time derived as a

simple multiplicative factor of the known frequency. This approach of keeping time has two

fundamental limitations.

First, with systems initialized at different time, the global value of time will be different. This

absolute difference between system clocks is called the phase offset. The second limitation

arises from the variation in the known frequency, due to environmental and manufacturing

differences, of the oscillator and is known as the frequency offset. When different clocks


Introduction 2

calculate and compensate for the phase offset, a different notion of the time increment causes

the clocks to drift apart over time.

Researchers have found several ways to compensate for both these limitations [1] [2] [3] [4].

Phase offset is calculated with message exchanges, with several novel mechanisms taking care

of the uncertainties. Frequency offset can be eliminated by using stable, but expensive

oscillator. A more traditional, and low cost, approach is to estimate the frequency offset using

regression techniques on the results of several message exchanges. A significant amount of

research in frequency estimation has gone into making it more accurate while using lesser

number of message exchanges, thus conserving energy.

Key insight of research work is the observation that physical layer symbol recovery already

compensates for frequency offset using feedback or feed forward time synchronization system

[5] [6] [7] [8]. The clock recovery process includes in itself information to estimate the

frequency offset.

This research thesis argues here that not only can this approach estimate the frequency offset

accurately, but it can also use the estimate to significantly improve the application layer

frequency offset calculation. The contributions of this research are, thus, threefold:

1. It presents the key idea that physical layer clock recovery can be used to estimate

frequency offset in application layer clock. As both the physical layer and application

layer clocks are derived from same quartz crystal within the device, therefore,

frequency offset should be same.

2. It experimentally evaluates the estimation using signal received at the physical layer

and then compares it with application layer mechanism. Computer simulations are

performed on MATLAB whereas experimental evaluation is done using DSP Kits.

3. It provides energy efficiency of the model and theoretical bounds that show the

minimum possible variance of the timing frequency error. It also computes the energy

efficiency and the number of symbols a cross layer packet must have in order to

accurately estimate the frequency offset.


Introduction 3

1.2 CROSS LAYER APPROACH

This research specifically deals with time synchronization problem at application and physical

layers in a wireless sensor network. A relationship between these layers is investigated and

exploited to propose a cross layer design for time synchronization. This design require fewer

computations and number of transmissions per sensor node to make use of available energy.

Thus higher accuracy and efficiency can be achieved with fewer number of timestamp

exchanges.

Figure 1 depicts the methodology for time synchronization at application layer, physical layer

and proposed cross layer design.

Figure 1 - Time Synchronization at Different Layers

Detailed explanation of time synchronization at different layers will be covered in detail latter.

Chapter 3 explains the application layer time synchronization, Chapter 4 explains the physical

layer time synchronization and Chapter 5 discusses the cross layer proposed approach.

Cross Layer Time Synchronization

•Symbol Timing Recovery

•Estimate Timing Frequency Offset

•Apply Frequency Correction to Physical Layer Clock

•Apply Frequency Correction to Application Layer Clock

Application Layer Time

Synchronization

•Broadcast Time stamps


•Apply Frequency Correction to Application Layer Clock

Physical Layer Time

Synchronization

•Symbol Timing Recovery


•Apply Frequency Correction to Physical Layer Clock


Introduction 4

1.3 ORGANIZATION OF THESIS

In Chapter 2, multiple ad hoc and sensor networks are discussed. The focus is on Wireless

Sensor Network (WSN) and different challenges in order to design and maintain the network.

Chapter 3 addresses different application layer time synchronization protocols of wired and

wireless networks. Physical layer time synchronization or symbol timing recovery is explained

in Chapter 4. Chapter 5 explains the core idea, i.e., cross layer time synchronization in detail.

Chapter 6 includes experimental setup, results and mathematical analysis. Chapter 7 concludes

the research work and elaborates future dimensions.


Ad Hoc & Sensor Networks 5

CHAPTER # 2

AD HOC & SENSOR NETWORKS

This chapter present an overview of various ad hoc and sensor networks. It focuses on Wireless

Sensor Network (WSN), its applications and design issues.

2.1 AD HOC NETWORKS

Ad hoc network is an autonomous system of mobile hosts which communicates via wireless

links. Wireless ad hoc network is a dispersed network that does not have any defined

infrastructure. Each mobile host routes and forward data for other mobile hosts which creates

a dynamic structure of network that exempt the need of routers or access points. In any ad hoc

network each mobile host can communicate with each other mobile host within its wireless

range.

2.2 MOBILE AD HOC NETWORK

Mobile Ad hoc NETwork (MANET) is a self-organizing network of Mobile Hosts (MH) [9]

[10]. It does not have any infrastructure or fixed stations. The network topology of MANET

dynamically changes as each MH is free to move. When communication of information is

required, each mobile host broadcast the information, which is received by all the nodes in

transmission range. If communicating mobile hosts are not within the range of each other, then

intermediate nodes are used to forward the message to the destination host. Therefore, each

node has the capability of routing and hence Ad hoc networks are without any infrastructure.



2.2.1 CHALLENGES

This section outlines few major problems that needs to be addressed when considering the

deployment of MANET.

2.2.1.1 SCALABILITY

Scalability refers to the size of ad hoc network. Increasing the size of network also raises the

overhead, as this may require additional data to transmit among nodes for time synchronization,

route acquisition, location acquisition and encryption key acquisition.

2.2.1.2 ROUTING

Routing of information among mobile hosts is major challenge due to varying topology of the

network. Communicating mobile hosts may not be in range of each other. Hence,

communication may contain multiple hops, which is again a challenge in such mobile

environment.

2.2.1.3 SECURITY

Due to dynamic wireless structure, ad hoc networks are very prone to malicious attacks,

impersonation and eavesdropping [9] etc. There must be multiple protocols deployed within a

network to secure.

2.2.1.4 SERVICES

Different services like file transfer, voice and live video must be provided according to

requirements of the network. The main challenge is to design a network that provides quality

service where applications are having different requirements.

2.2.1.5 ENERGY CONSERVATION

Energy is a scarce resource due to one-time deployment of mobile hosts and their battery life

that defines the lifetime of the ad hoc network. Therefore, energy conservation must be

addressed at each layer of MANET or any other ad hoc network. Better batteries, energy

efficient operations of mobile host and energy aware routing can increase the lifetime of the ad

hoc network.



2.2.1.6 INTERNETWORKING

Some application running over MANET may require connection with internet. This

interoperation of MANET and internet requires a communication interface. Mobile hosts

having internet access may provide internet connectivity to other mobile hosts which have no

internet access.

2.2.1.7 TIME SYNCHRONIZATION

Time synchronization among the mobile hosts is very crucial and energy consuming process.

Different protocols must be deployed to maintain the same notion of time in MANET.

2.2.1.8 RELIABILITY

Ad hoc network uses wireless communication link which leads to reliability issues. The

network may become non-reliable if it is not compensated for limited wireless transmission

range, hidden terminal problem, data error or loss due to mobile architecture, etc.

2.2.1.9 INTEROPERATION

It is a challenge to avoid interference when two independent networks that have become very

adjacent to each other. This interference may lead to security threat, inefficient routing and

incorrect time synchronization.

2.2.2 APPLICATIONS

MANET applications are very diverse in nature. A MANET can be highly mobile, dynamic,

energy constrained and large in size as well as it can be small and static. Some of the MANET

applications are discussed as follows.

MANET technology was initially developed for military to monitor and route information to

soldiers and vehicles [10]. It can also be used for emergency situations like law enforcement,

natural disasters, etc. A personal area network can be deployed using short range MANET.



2.3 WIRELESS SENSOR NETWORK

WSN is an ad hoc network with less or no mobility [10] [54] [55] [56] [57] [69] [77] [78] [80],

in fact it is a distributed network of sensors which are organized to observe the real world

phenomena. In an ad hoc network, data can be retained from any mobile host, but in WSN data

is retained to reflect the overall environment of the deployed network. This is achieved by using

large number of sensors deployed to sense the required aspect [10] [11]. WSN is a smart choice

to create an association between virtual and physical world.

2.3.1 TYPES OF WIRELESS SENSOR NETWORK

Typically WSN does not have any infrastructure because of thousands of nodes which are

monitoring a geographical area. Two types of WSN based on structural differences are given

below.

2.3.1.1 STRUCTURED WSN

Such a WSN contains some special sensor nodes with specific attributes which are deployed

across the network in some order. Remaining nodes are deployed in ad hoc manner.

2.3.1.2 UNSTRUCTURED WSN

Such a WSN has large number of sensors which are deployed in ad hoc manner. Comparatively,

it is difficult to maintain and manage the network due to unplanned and outsized nature.

2.3.2 SENSORS

Sensors are the key to gather information in a WSN. Each WSN has large number of sensor

nodes which can sense the data from the physical world, process the gathered information and

communicate with each other.

Sensor is a small inexpensive device with limited processing, power and the ability to sense

and communicate. The structure of a low powered sensor node contains sensor transducer,

actuator, memory, power supply, processor and transceiver [11] as shown in the Figure 2.



A transceiver transmit and receive information typically at a data rate of 10Kbps to 1Mpbs and

in a 50 to 125 meter range [10]. Each node has a limited memory of 3Kb to 1Mb. Memory,

transmission rate and range are totally dependent on application and can vary according to the

requirements. Embedded processor control the overall operation of sensor node. Battery is the

power source available for sensing, processing and transmission. Secondary power source can

be anything that can extract energy from environment such as solar panel. Sensor actuator can

trigger transducer, vary parameters and can move the sensing device [11]. Transducers can

convert physical quantities to electrical signals. Physical quantities may include temperature,

sound, light intensity, pressure, acceleration, velocity, humidity, pollution, etc.

2.3.2.1 MOTE

Commercially available devices that can sense, process and communicate are known as motes

[12]. These motes act as sensor nodes in any wireless sensor network. Their specifications may

vary according to requirement of the network.

2.3.2.2 ENERGY CONSUMPTION

Each node in WSN is responsible for sensing, computing, transmitting and receiving of data.

These operations require energy which is provided either by the battery or energy harvesting

device like solar panels. Sleep mode can be installed within a sensor to conserve energy by

turning the components on and off periodically.

Memory

Transceiver

Battery *

Sensor Transducer

Actuator

Processor

* Power supply connected to every component

Figure 2 - Structure of typical WSN node



2.3.2.2.1 TRANSDUCER

Transducers installed on sensors for sensing the phenomena, requires energy and its

consumption depends on the hardware used. At times actuators are also installed with

transducers which also require energy. The data extracted from transducers goes through

Analog/Digital Converter (ADC) which consumes 3.1µW [10].

2.3.2.2.2 TRANSCEIVER

The energy required for transmission 𝐸𝑇𝑥(𝑘, 𝑑) and reception 𝐸𝑅𝑥(𝑘) of k-bit data to distance

d is given by [10] and [13] as,

𝐸𝑇𝑥(𝑘, 𝑑) = 𝐸𝑒𝑙𝑒𝑐𝑘 + 𝜀𝑘𝑑2 (2.1)

𝐸𝑅𝑥(𝑘) = 𝐸𝑒𝑙𝑒𝑐𝑘 (2.2)

Where 𝐸𝑒𝑙𝑒𝑐 is required by transmitter/receiver circuit and 𝜀𝑘𝑑2 is the energy used by

transmitter amplifier. The research work in [13] utilizes value of 𝐸𝑒𝑙𝑒𝑐 = 50𝑛𝐽𝑚2 per bit and

𝜀 = 100 𝑝𝐽𝑚2 per bit to compute the energy used for data transmission.

2.3.2.2.3 PROCESSING AND MEMORY OPERATIONS

The processor is responsible for executing all the protocols and algorithms required by the

WSN. The switching operations within the processor requires energy which is defined as a

product of total switched capacitance and square of supplied voltage, as discussed in [14] .

When processor is in no-operation mode, it still consumes leakage energy [14].

2.3.3 CHALLENGES

There are many challenges need to be addressed during wireless sensor network design and

deployment [56] [57] [58] [62]. Some of the important design issues and challenges are

discussed below.

2.3.3.1 ENERGY CONSERVATION

Sensor nodes are small and low cost devices that can store limited amount of energy, therefore,

efficient use of available energy is a major concern [61] [68] [79]. To make WSN economically



feasible, sensor devices must be efficient in their energy consumption, computation and

communication capabilities. Sensor nodes have to overcome the hardware limitations and also

fulfill the application requirements. The algorithms and protocols must provide energy efficient

and robust communication which also includes efficient modulation, channel coding, source

coding and channel access strategy.

2.3.3.2 NODE COST

Making a sensor as a low cost device is a challenging issue, as large number of sensors are

required to accomplish a given task. This challenge further amplifies with an increment of

network requirements per node.

2.3.3.3 SCALABILITY

Scalability is another challenging issue in WSN design. Increasing the size of network requires

additional maintenance concerns due to increase in data overhead. Large number of nodes

require additional communications throughout the network for time synchronization, routing,

etc.

2.3.3.4 SELF ORGANIZATION

A wireless sensor network is dynamic and ad hoc. Sensor nodes must have the ability to

dynamically configure itself in a WSN in order to reflect network environment. A sensor node

may fail due to insufficient energy, hardware destruction or change in position. Failure to

communicate due to congestion or radio propagation issues causes change in a network

topology. WSN must be able to adopt such changes and hence self-configuration and

robustness is a major system’s design requirement.

2.3.3.5 SECURITY

Similar to any wireless network, WSN is also very prone to malicious attacks which must be

compensated by using authentication and encryption protocols [64] [74].

2.3.3.6 RELIABILITY

WSN must be fault tolerant. Failure of one node should not disturb the overall working of the

network. Communication link issues must also be compensated.



2.3.3.7 ROUTING

Routing in large network is also a challenge. When nodes are not within range of each other,

multi hop communication should be incorporated by using intermediate nodes. Many routing

protocols are available for energy efficient routing of information.

2.3.3.8 CLOCK SYNCHRONIZATION

In WSN, the main task is collection of sensor readings and timestamps to have a significant

outcome. The process of altering and merging individual sensor readings into required output

dictates the necessity for a common notion of time among the sensors is called clock

synchronization. Synchronization is one of the most vital concerns in WSN because it plays an

important role of data fusion and therefore, it is compulsory at different layers to implicate

frequency and phase synchronization [15].

2.3.4 APPLICATIONS

Sensors can be deployed in the environment to access the inaccessible or dangerous areas and

can be used for military systems, geophysical monitoring, wildlife monitoring, manufacturing

machinery performance monitoring, building safety and earthquake monitoring, etc. [16] [17]

[59] [60] [63] [65] [66] [67] [70] [71] [72] [73] [75] [76] [78] [81]. Based on the requirement

of WSN, transducers are installed in sensors to sense different phenomena. WSN applications

are discussed as follows.

2.3.4.1 MILITARY APPLICATIONS

Military applications of sensor networks include enemy tracking, security detection, battlefield

surveillance, target classification, nuclear attack, etc. [12]. Sensor networks can track location

of army men, equipment and ammunition. Sensitive areas can be deployed with wireless sensor

networks to monitor any kind of activity. WSN can timely report any intrusion of the attacking

military, whereas chemical, biological or nuclear activities can also be efficiently monitored

[18].



2.3.4.2 HABITAT APPLICATIONS

WSN can be used for animal monitoring and tracking. Any other moving phenomenon can be

monitored or tracked. One such sensor network is deployed by University of California at

Berkeley with the coordination of Intel Research Laboratory in Great Duck Island to monitor

storm petrel [10] [19].

2.3.4.3 ENVIRONMENT APPLICATIONS

Sensors are used for monitoring different aspects of environment, e.g., weather, temperature

and pressure, etc. Environmental applications also include detection of any hazard like fire

detection, earth quake and flood detection etc. [12] [18]. One such prototype for environment

observation and forecasting system is CORIE [10].

2.3.4.4 HEALTH APPLICATIONS

Remote patient monitoring, communicating vital signs (heart rate, blood pressure, etc.) of

patient and doctors monitoring etc. falls in this category of applications. One such human vision

restoration application is developed by Smart Sensor and Integrated Microsystem (SSIM)

project [20].

2.3.4.5 MISCELLANEOUS APPLICATIONS

Wireless sensor network is deployed in various fields for monitoring or tracking. University of

Hawaii deployed a WSN named as PODS to monitor the growth of plants [21]. The work

presented in [22] proposes a wireless sensor monitoring system for monitoring of drinking

water quality. Similarly WSNs are deployed for the detection of storm, fire, flood, earthquakes,

monitoring of soil moisture, building cracks, factory, inventory, machine, etc. [10]. Tracking

applications also includes human, traffic and car theft tracking. Home automation and

environmental control can also be done using WSN [18]. Few other applications are discussed

by [83] [84] [85] [86] [87].

Figure 3 summaries few of the WSN applications.



Figure 3 - Applications of Wireless Sensor Network

Militray

Nuclear, biological,

chemical attack

Hazardous material detection

Enemy vehicles and aircraft monitoring

Friendly forces, equipment and

ammo monitoring

Habitat

Animals monitoring

Birds tracking

Ecological and Biological habitats

monitoring

Environment

Weather forecasting

Temperature and pressure

monitoring

Fire, earth quake and flood detection

Health

Remote patient monitoring

Doctors tracking and monitoring

Patient vital signs monitoring

Miscellaneous

Drinking water quality monitoring

Soil moisture, building

monitoring

Factory, inventory, machine

monitoring

Car theft, traffic monitoring


Application Layer Clock Synchronization 15

CHAPTER # 3

APPLICATION LAYER CLOCK SYNCHRONIZATION

This chapter presents the idea of application layer clocks, synchronization, different protocols

of application layer used for time synchronization in any wired and wireless networks. One of

the WSN protocols for time synchronization among nodes of network is FTSP, discussed in

detail here.

3.1 APPLICATION LAYER CLOCK

In any ad hoc network, each node has to maintain its own clock. Application layer clocks are

usually timers that counts the oscillations of quartz crystal and maintain two registers to define

that how many oscillations of crystal is equal to one application layer clock tick [3] [23]. These

two registers are counter register and holding register. Counter register counts the oscillations

of crystal and after every specific number of oscillations, holding register value is increased

and counter register is set to zero. Holding register has the clock value which can be mapped

to actual time of day, which is usually not the practice.

3.1.1 IMPRECISIONS OF CLOCK

As these application layer clocks are derived from the quartz crystal oscillations, they deviate

from the actual values. Specifically in any ad hoc network where each node has its own clock

with its own quartz crystal, time variations are expected. These clocks can have two types of

inaccuracies discussed as follows.



3.1.1.1 PHASE ERROR

Phase error corresponds to the difference in clock values of two nodes. Figure 4 shows two

clocks with phase error.

Figure 4 - Phase Error in Application Layer Clocks

Clock A and Clock B are running at a phase difference of 20 and the difference remains

constant for the given time t.

3.1.1.2 FREQUENCY ERROR

Frequency error corresponds to the difference in speed of clocks. Figure 5 shows two clocks

with frequency error and no phase error.

2 4 6 8 10 12 14 16 18 2010

15

20

25

30

35

Time (t)

Clo

ck V

alu

es

Clock A

Clock B



Figure 5 - Frequency Error in Application Layer Clocks

Clock A and Clock B are running with different speeds. Initially the clocks are at zero phase

difference, but with passage of time phase difference is introduced because of different

frequencies of clocks. Frequency error is also known as clock skew.

3.1.1.3 PHASE AND FREQUENCY ERROR

Between any two clocks, there may be phase as well as frequency error. Figure 6 shows two

clocks with frequency and phase error.

2 4 6 8 10 12 14 16 18 2010

12

14

16

18

20

22

24

26

28

30

Time (t)

Clo

ck V

alu

es

Clock A

Clock B



Figure 6 - Phase and Frequency Error in Application Layer Clocks

Clock A and Clock B are running with different speeds and initially the clocks have a phase

difference of 20. With passage of time phase difference is increased and clock values keep

diverging from each other.

3.1.1.4 PERFECT CLOCKS

Perfect clocks are synchronized and they have no phase and frequency error. Such clocks are

known as synchronized clocks, which is a crucial requirement of any ad hoc network. Figure 7

shows two perfect clocks with no phase and frequency error.

2 4 6 8 10 12 14 16 18 2010

15

20

25

30

35

40

45

Time (t)

Clo

ck V

alu

es

Clock A

Clock B



Figure 7 - Perfect Application Layer Clocks

Clock A and Clock B are perfectly synchronized clocks running with same speed and no phase

difference.

3.1.2 CLOCK ADJUSTMENTS

Two things can be done if the clocks are found to be incorrect. Clock values may be corrected

or they may be allowed to run untethered.

3.1.2.1 CLOCK CORRECTION

This method of clock adjustment imposes the change of clock values and hence synchronized.

Clock correction can be done gradually be varying the frequency or instantaneously.

3.1.2.1.1 INSTANTANEOUS CORRECTION

Instantaneous correction can cause skipping of events. If some event is triggered within the

time that is skipped then node will not be able to identify that event.

2 4 6 8 10 12 14 16 18 2010

12

14

16

18

20

22

24

26

28

Time (t)

Clo

ck V

alu

es

Clock A

Clock B



3.1.2.1.2 CONTINUOUS CORRECTION

Continuous correction of clocks is more suitable because there may not be chance left for

skipping any event. Change in frequency spans the correction of clock in some time and hence

no event can be missed because node is aware at every clock value.

3.1.2.2 UNTETHERED CLOCKS

Another method of clock adjustment between nodes is to let the clock run untethered. Only the

difference between the clock values of the nodes is saved in the register by each node such that

whenever they are communicating with each other, then saved value can be took into

accordance. This type of clock adjustment is getting more popular due to the advantages offered

by it.

3.1.3 GLOBAL TIME ACCESS

The need of global time arises when all nodes desire the common notion of time. There are two

ways of achieving global time.

3.1.3.1 INSTALLATION OF GPS IN ALL NODES

Installation of GPS device to access the global time in all nodes will eliminate the need of

synchronization within network, but this will increase the cost of node and hence practically

not possible.

3.1.3.2 USING SYNCHRONIZATION PROTOCOLS

The practical approach is to install GPS in few or one node that may be considered a master

node and all other nodes need to synchronize with this master node only using synchronization

protocols. Synchronization and different protocols for wired and wireless networks are

discussed in coming sections.

3.2 SYNCHRONIZATION

Synchronization is the foundation of coordinated events in a population of networking agents.

Clock/time synchronization is a very important aspect of any wireless distributed network.



WSN make use of time synchronization for sensor data fusion or any coordination in the

network. Clock precision and accuracy varies with requirements of different WSN.

3.2.1 CRITICAL METRICS

Critical metrics of any system are the criteria by which efficiency, performance, progress, or

quality of service can be evaluated. For time synchronization in any WSN, critical metrics can

be precision, efficiency, lifetime, cost, scope and availability.

3.2.1.1 PRECISION

Precision of a clock refers to the maximum error that a clock can have in a network with respect

to the master clock. Required precision depends on the application of sensor network.

3.2.1.2 EFFICIENCY

Efficiency corresponds to the time, energy and computations required to perform the

synchronization. Energy efficiency is a major requirement and one way to concur is to have a

synchronization protocol with very few computations. The simpler the protocol, higher the

energy efficiency and longer the battery life. Energy efficiency can also be increased by

decreasing the number of data transmissions required for a node to work properly in the

network. Time synchronization in fewer numbers of transmissions also decreases the energy

requirements.

3.2.1.3 LIFETIME

Lifetime of the synchronization refers that how often time synchronization should be done.

Increasing lifetime of synchronization improves energy efficiency, but affects precision and

accuracy of the synchronizing clocks.

3.2.1.4 COST

Cost is another major factor, as there is a requirement of very large number of devices/sensors

in a network. Technology advancements are improving cost factor.



3.2.1.5 SCOPE AND AVAILABILITY

Scope and availability corresponds to the coverage issues. Increasing size of the network may

affect the working of the sensor network. Every node’s radio range may be adjusted without

reducing the energy efficiency.

3.2.2 SIGNIFICANCE

Each node of any distributed system has its own clock. When distributed systems are deployed

and with the passage of time, the clocks of the nodes vary in their values (phase offset). The

clock ticking rates (frequency) may also change. This possess a grave problem for the

applications which are time dependent. Mostly applications are time dependent and time is the

only frame of reference within a network. Networks have to relate events with time and hence

each node has to associate time stamp with the events happening. The time interval between

two events may also be of interest. Time synchronization is very crucial especially if ordering

of the events are required. Most of the ad hoc networks and even wired networks have this

requirement. Time synchronization ensures that all distributed nodes have common notion of

time and hence time dependent quires can be resolved.

3.3 CLOCK SYNCHRONIZATION PROTOCOLS

Every network, whether it is wired or wireless, needs clock synchronization. There are different

protocols available for the wired and wireless network synchronization at application layer.

3.3.1 WIRED NETWORK CLOCK SYNCHRONIZATION

Clocks of every node need to be synchronized in wired network so that these can relate events

to time, time stamp data and time of day service, etc. As energy is not a very scarce resource

in comparison with wireless networks, time synchronization packets can be sent periodically

before any node in the network losses its synchronization.

Any of the synchronization protocol must have few abilities, which includes coping with

unreliable network transmission, maintaining common notion of time throughout the network,

gradual clock correction so that no time is skipped or move backward and acceptable

synchronization overhead [3]. Few of the important protocols suitable only for wired network

are discussed below.



3.3.1.1 NETWORK TIME PROTOCOL

Network Time Protocol (NTP) is most widely used in wired networks for time synchronization

[2] among different protocols. NTP creates a hierarchical tree of time servers. Primary server

synchronizes with the global clock and distributes the time information to the secondary servers

and then to the clients. Secondary servers are also called backup servers, as they act as backup

for the primary servers. NTP tries to ensure an extremely accurate clock and that’s why primary

servers usually equipped with atomic clock. Figure 8 shows the implementation of NTP in

wired network.

Figure 8 - Network Time Protocol Hierarchy

Nodes that need synchronization sends a User Datagram Protocol (UDP) packet to time server

and gets the time information in return [24]. Following this method, each node in the

hierarchical structure synchronizes. Figure 9 shows node synchronization procedure.

Figure 9 - Network Time Protocol Node Synchronization

Clients

Secondary Server

Primary Server PS

SS1

C1 C2 C3

SS2

C4 C5 C6

SS3

C7 C8

• Requests time using UDP

Node

• Returns time information

Time Server• Apply clock

correction

Node



3.3.1.2 SIMPLE NETWORK TIME PROTOCOL

Simple Network Time Protocol (SNTP) is a subset of NTP and used for the same purpose, i.e.

for time synchronization among nodes of network. SNTP, as the name suggest, is the simple

implementation of NTP and can be used where full NTP implementation is not justified or

needed.

3.3.1.3 PRECISION TIME PROTOCOL

Precision Time Protocol (PTP) uses a master-slave architecture for the distribution of clock

among the nodes of wired network. The master node provides the time information to the slave

nodes and is determined by the group of nodes using Best Master Clock (BMC) algorithm [25].

Master node is synchronized with grand master node attached to time reference such as Global

Positioning System (GPS). GPS is a satellite navigation system that provides time and location

information and can be used as a time reference [3]. Figure 10 shows the specimen of PTP

implementation.

Figure 10 - Precision Time Protocol Mater-Slave Architecture

PTP uses series of messages between reference master clock server and the node that needs to

be synchronized. Time offsets from various messages are used to estimate the precise and more

accurate clock value [25] [26]. Figure 11 shows PTP node synchronization procedure.

Grand Master

Master1

Slave1

Slave2

Slave3

Master2

Slave4

Slave5

Slave6

Master3

Slave7

Slave8

GPS



Figure 11 - Precision Time Protocol Node Synchronization

3.3.1.4 TIME TRANSMISSION PROTOCOL

In Time Transmission Protocol (TTP), a node send its time stamp to the synchronizing node.

The node that receives multiple time stamps, estimate the time of the source node by the help

of message delay statistics [3], and synchronizes itself. This requires large number of

synchronization packets within a network and causes computational overhead, making it

unrealistic. Figure 12 shows the node synchronization process.

Figure 12 - Time Transmission Protocol Node Synchronization

3.3.1.5 MISCELLANEOUS PROTOCOLS

Time synchronization protocols also include Cristian’s protocol, Set-valued Estimation

protocol, etc. These protocols exchange multiple time stamps between synchronized node and

synchronizing node and estimate clock values using different algebraic formulas.

3.3.2 WIRELESS NETWORK CLOCK SYNCHRONIZATION

Wired network time synchronization protocols do not offer very good results in wireless sensor

networks because of the different requirements, i.e., energy efficiency, infrastructure, end to

end latency, reliability [3] [27] etc. Using GPS in every wireless node to maintain same time

Multiple time stamp exchanges between

synchronizing node and master

Estimating Time Offset using all the available time stamps

Apply time correction to the synchronizing node

Source Node

Time stamp 1Time stamp 2Time stamp 3

.

.

.

.Time stamp n

Synchronizing Node estimate source node's

time

Apply clock correction



in the network is also not reliable option, as it makes the inexpensive wireless nodes more

expensive and energy consuming. GPS communication also requires line of sight with the

satellite which may not be available, depending of deployment environment. Time

synchronization in wireless networks can be done in three different ways. Relative timing

seems to be the simplest one, as it only relies on the order of the events and do not maintain an

actual clock, but this can only be used in limited types of wireless networks. Another way of

synchronizing is that each node has the information about its frequency and phase offset with

other nodes and can synchronize their clock values. This approach is mostly deployed by many

of the time synchronization protocols. Global synchronization, another method of

synchronization, tries to maintain a global clock throughout the network. Such synchronization

approach is very rarely used. Many protocols are available for time synchronization at the

application layer in any wireless network. Few of these are discussed below.

3.3.2.1 REFERENCE BROADCAST SYNCHRONIZATION PROTOCOL

Reference Broadcast Synchronization (RBS) protocol can be used in wireless distributed

network for time synchronization to decrease non-deterministic latency using receiver to

receiver synchronization [1] [3] [28]. Wireless node sends reference broadcast beacons to its

neighbors using physical layer broadcasts and compute the non-determinism of packet send

time, access time and propagation time, depending only on the packet receive time. This

reference broadcast packet can be used to synchronize a set of receivers with one another [1].

RBS maintains a table that contains the local clock values of each node in the network. RBS

relates the local clocks of node with each other using table and let the clocks run without

correction. Figure 13 shows the RBS using wireless network.

The process used by RBS for the estimation of time is shown in the Figure 14.

Wireless Node

with time info

Neighbors

Beacons

Figure 13 - Reference Broadcast Synchronization Protocol Deployed Wireless Network



Figure 14 - Reference Broadcast Synchronization Protocol Node Synchronization

3.3.2.2 ROMER’S PROTOCOL

In [29] the Romer's protocol uses an innovative time transformation algorithm for achieving

clock synchronization. It uses message delay, which is estimated by the lower bound and the

upper bound round trip time (RTT) to compare the utmost difference between two

communicating nodes [1]. Romer's protocol also uses the same principle as RBS to let the

clocks run untethered. Continuous clock synchronization protocols spread the correction of

clock over a finite interval. The local clock time is corrected by gradually speeding up or

slowing down the clock rate [3]. It provides the minimal message complexity, fault tolerance

[3] and avoids unpredictable instantaneous corrections of clock values. Figure 15 shows the

process of node synchronization using Romer’s protocol.

Figure 15 - Romer's Protocol Node Synchronization

3.3.2.3 TIMING-SYNC PROTOCOL FOR SENSOR NETWORKS

Timing-sync Protocol for Sensor Networks (TPSN) [30] is a sender-receiver based

synchronization protocol designed for WSN. TPSN creates tree of the nodes and synchronize

Node with Time Info

•Broadcast beacons

Neighbor Nodes

•Compute time error using packet send time, access time and propogation time

Neighbor Nodes

•Apply clock correction

Message delay estimated and applied on communicating nodes

Upper bound

RTT

Lower bound

RTT



them in two phases namely, level discovery phase and synchronization phase. In level

discovery phase, a tree of node is created by assigning a level to each node. Level discovery

phase also defines the master node or root node. In synchronization phase all nodes synchronize

with its upper level nodes and eventually synchronize to root node. Figure 16 shows the

architecture of TPSN.

Figure 16 - Timing-sync Protocol for Sensor Network Architecture

Figure 17 shows the network synchronization process using TPSN.

Figure 17 - Timing-sync Protocol for Sensor Network Node Synchronization

3.3.2.4 FLOODING TIME SYNCHRONIZATION PROTOCOL

Flooding Time Synchronization Protocol (FTSP) [4] [31] seems to be the most promising

application layer protocol used for time synchronization in wireless networks. FTSP provides

good bandwidth efficiency and robust to wireless node failures. FTSP transmits it time stamp

periodically to all of the nodes in the wireless network and these nodes correct their application

layer clock by comparing the time stamps. Using FTSP, a master node can synchronize every

node in its range by using a single radio message time-stamped at both the master and the

receiving nodes. FTSP uses MAC layer byte wise time stamping and hence avoids all issues

involved in radio message delivery. Figure 18 shows the FTSP network architecture.

.

Level - II

Level - I

Root Node RN

N1.1

N2.1

. .

N2.2

.

N2.3

.

N1.2

N2.4

.

N2.5

.

N2.6

.

N1.3

N2.7

.

N2.8

.

Level Discovery Phase

•Allocate root node

•Assign levels to each node

Synchronization Phase

•Node synchronizes to upper level nodes

•Network synchronizes to root node



Figure 19 shows the process of FTSP node synchronization

Figure 19 - Flooding Time Synchronization Protocol Node Synchronization

Every node in FTSP deployed network maintains unique ID, root ID, sequence number, local

clock and regression table. Synchronization message contain root ID, sequence number and

timestamp. Following this method FTSP can synchronize in nodes that are not in direct range

of root node, i.e. FTSP supports multi hop time synchronization. Consider node A as

synchronized node and is selected as a root node as shown in the Figure 20. Node A broadcasts

time synchronization message and synchronizes with node B, C and D. Node D synchronizes

node E, F, G that are in its broadcast range. Node G synchronizes remaining nodes and hence

multi hop synchronization is achieved. Now suppose if root node A fails, then node D, E and

H may be selected at random and become root nodes. All other nodes are out of sync from

current root nodes. After exchanging messages, node E decided to be the root node and again

synchronizes the whole network where node D and H left the root mode. Root node selection

methods are given by [4] [31] [32].

Root Node

•Broadcast time stamp

Neighbor Nodes

•Correct their clocks with respect to receiving time stamp

Root Node

Broadcast

timestamps

Synchronizing

Nodes

Synchronizing

Nodes

Figure 18 - Flooding Time Synchronization Protocol Network Architecture



3.3.2.5 MISCELLANEOUS PROTOCOLS

Protocols discussed by [1] and [3] are network wide time synchronization protocols that have

the capability hold large node density. Delay Measurement Time Synchronization, which is an

energy-efficient protocol, but less accurate than the RBS [28] protocol. Probabilistic Clock

Synchronization extends RBS by providing probabilistic bounds on the accuracy of clock

synchronization. Time-Diffusion Protocol (TDP) based on a diffusion of messages involving

all the nodes in the synchronization process. All of the above protocols mentioned in [2] [3]

[28] [29] [40] [41] [42] [43] [44] [45] [46] [47] [48] [51] [53] can be used for application layer

clock synchronization in any wireless distributed network (e.g. Wireless Sensor Network [1]

[3]) depending on the environment and requirements because each has its own merits and

challenges.

3.3.2.6 LIMITATIONS OF CURRENT STATE OF THE ART AND MOTIVATION

Using any of the above-mentioned protocols require multiple timestamps to estimate the

frequency offset, however, phase offset correction can be done using one timestamp. FTSP

uses multiple timestamp exchanges and computes the frequency offset on the basis of these

timestamps. However, the proposed method uses only one timestamp for the correction of

phase offset as well as frequency offset. Cross layer approach will estimate the frequency offset

of application layer clock from the symbol timing recovery process of the physical layer. Use

of one timestamp increases the energy efficiency and accuracy, which is the motivation of the

current research work.

B

A

D

C

F

E G H

I

Figure 20 - Flooding Time Synchronization Protocol Multi Hop Synchronization



3.4 CLOCK SYNCHRONIZATION IN WSN

Clock synchronization in WSN has the same importance as of any other wireless network. Any

of the above-mentioned wireless time synchronization protocols can be deployed in WSN.

Discussion below dictates challenges and concerns specific to WSN clock synchronization, a

comparison between major protocols and why FTSP is preferred.

3.4.1 CHALLENGES

Wireless sensor networks has to face some specific design challenges because of the ad hoc

nature and cheap sensor node design requirement. Each sensor node has limited energy derived

from a single battery. That energy needs to be used in efficient manner which impersonate

limited range, bandwidth and computational power. Furthermore, the nodes can die and

network topologies may change. A compensation must be incorporated in sensor nodes.

3.4.2 SYNCHRONIZATION PERFORMANCE

Any wireless time synchronization protocol depends on four factors, i.e., packet send time,

access time, propagation time and receive time. Send time is the time required for the

construction of the message, access time is network access delay, propagation time is time

required for transmission of message and receive time is message processing time at receiver

end as shown in Figure 21. Synchronization performance of any protocol can be increased by

excluding any of the above-mentioned time in the process of clock correction. It is always

suggested using a protocol that can counter these delays in wireless sensor networks.

Figure 21 - Delay Components Effecting Synchronization Performance

3.4.3 SYNCHRONIZATION CONCERNS

There are so many concerns when it comes to the selection of protocol for wireless sensor

network. Synchronization offered by various protocols have two architectures namely Master

Delay Components

Sender Node

Send Time Access Time

Wireless Transmission

Propogation Time

Receiver Node

Receive Time



Slave and Peer-to-Peer. Master Slave architecture assigns a master for each group of slaves

whereas in peer-to-peer architecture every node is free to communicate with every other node

in network. Another concern is about correction of clock, i.e., whether the clocks of

synchronizing nodes needs to be adjusted or left to run untethered with a reference of error

stored in node’s memory. Other concerns can be, use of real world time using any external

source is required or internal synchronization will be enough for this wireless sensor network,

protocols do offer probabilistic as well as deterministic synchronization, which one to use,

synchronizing protocol uses sender to receiver or receiver to receiver synchronization method,

sensor network is single hop or multi hop network, nodes are stationary or mobile or both [2]

[3] [18] [49] [50] [52]. Figure 22 shows the summary of few synchronization concerns.

Figure 22 - Synchronization Concerns

3.4.4 COMPARISON OF RBS, TPSN AND FTSP

Key timing protocols that are used in wireless sensor networks are RBS, TPSN and FTSP. Each

has its own merits and demerits, however, FTSP is a preferred protocol. RBS protocol abolishes

the time required for message construction and network access time where TPSN also abolishes

the propagation time as well and hence preferred over RBS [4]. TPSN has a disadvantage over

Architecture

Master Slave

Peer to Peer

Clock Adjustment

Clocks Correction

Untethered Clocks

Time

Use External Source

Internal Synchronization

Type

Probabilistic Synchronization

Deterministic Synchroniztion

Method

Sender to Receiver

Synchronization

Receiver to Receiver

Synchronization

Network

Single Hop

Multi Hop

Nodes

Stationary

Mobile



FTSP that it requires bi-directional message exchanges and FTSP also removes the packet

encoding time at sender, network access time and packet decoding time at receiver [4]. Most

of all FTSP is robust protocol and can efficiently handle topological changes which TPSN

cannot handle efficiently. FTSP also requires less network resources than RBS and TPSN.

TPSN and FTSP both uses sender to receiver synchronization whereas RBS uses receiver to

receiver synchronization method, which is not preferred on sender to receiver synchronization

method. RBS is not designed for multi hop network where TPSN and FTSP are designed for

multi hop networks hence eliminating range issues. A comparison highlighting major

advantages of these three protocols is shown in Figure 23. FTSP seems to be the most

promising protocol for wireless sensor networks.

Figure 23 - RBS, TSPN and FTSP Comparison

RBS TPSN TPSN FTSP


Physical Layer Time Synchronization 34

CHAPTER # 4

PHYSICAL LAYER TIME SYNCHRONIZATION

This chapter presents physical layer clocks, communication systems and physical layer time

synchronization methods that are used by every wireless communication network for symbol

timing recovery.

4.1 PHYSICAL LAYER CLOCK

In order to design a communication hardware, a digital signal processor is required if the

communication is of digital nature. The processor is responsible for every act, hence every

algorithm is simulated by it. The algorithm written for the processors is sequence of instructions

to carry out some specific tasks. These instructions need to be run one by one and it is only

possible if there is some timing information, otherwise all of the instructions will run

simultaneously and no output can be gained. Proper execution of instructions requires some

sort of clock. A clock is a component which ticks at regular intervals and helps to synchronize

the flow of instructions within the processor. This is known as physical layer clock which also

depends on the oscillations of quartz crystal identical to application layer clock.

4.1.1 IMPERFECTIONS

Physical layer clock is dependent on the crystal oscillator and hence suffer from the

imperfections. These imperfections are known timing phase offset and timing frequency offset

discussed below.



4.1.1.1 TIMING PHASE OFFSET

Timing phase offset between any two clocks refer to the absolute difference between clock

values. One reason of phase offset is that the systems are initialized at different times and

maintain their own clocks. Figure 24 shows the phase offset between the clocks of two systems.

The ticks of both clocks are represented by lines.

System A

System B

4.1.1.2 TIMING FREQUENCY OFFSET

The second imperfection, which is known as frequency offset, arises from the variation in the

known frequency due to environmental and manufacturing differences of the oscillator. The

clocks start running with different speeds causes a drift in clock values and hence diverge from

each other. Figure 25 shows the frequency offset between the clocks of two systems. The ticks

of both clocks are represented by lines.

System A

System B

Figure 25 - Timing Frequency Offset between two System Clocks

4.2 COMMUNICATION SYSTEMS

This section discussed some linear modulation communication systems which are widely in

use at the physical layer for the purpose of data communication whether it is between any

wireless nodes or specifically between wireless sensor nodes. Each node is deployed with a

transceiver which implements any communication system that makes the node capable of

communication. Figure 26 shows the block diagram of a transceiver.

Phase Offset

Figure 24 - Timing Phase Offset between two System Clocks



Transmitting bits are mapped to symbols according to the selected modulation scheme. This is

usually done with the help of a lookup table that has the information of how these bits will be

mapped to symbols. Upsampling and pulse shaping filter makes the pulses on each symbol.

These pulses composed of few samples per symbol are of discrete nature and hence needs to

be converted to analog for transmission. This completes the transmitter part. The analog data

received at the receiver side is first converted to digital. Consequently a counter part of pulse

shaping filter, i.e., matched filter processes the data, downsamples it and decisions are made

according to the used modulation scheme. Practically, selection of sample is a very critical

concern. Symbol timing recovery dictates that which sample should be chosen for decision.

Symbol timing recovery will be discussed later in this chapter. Discrete time realization of few

systems using popular modulation schemes are discussed below.

4.2.1 PULSE AMPLITUDE MODULATION SYSTEM

A simple discrete time communication system using binary Pulse Amplitude Modulation

(PAM) scheme is shown in Figure 27.

Symbol Timing Recovery

Symbols

Mapping

Up

Sampling

Pulse Shaping

Filter

Digital to Analog

Convertor

Bits

Transmitter

Decision Sampling Matched

Filter Analog to Digital

Convertor

Bits

Receiver

Figure 26 - Transceiver Block Diagram

PAM

Symbols

Pulses Pulse Shaping

Filter

Digital to Analog

Convertor

Bits

Transmitter

Lookup Table

0 -1

1 +1

N

Sampling Matched

Filter Analog to Digital

Convertor

Bits

Receiver

Decision

Figure 27 - Pulse Amplitude Modulation Transceiver



Orignal data bits are first mapped to binary PAM symbols. Each 0 is mapped to -1 and each 1

is mapped to +1. Having symbols at hand, N is the ratio of sample rate to the symbol rate,

symbols are upsampled by N. These upsampled symbols passes through a pulse shaping filter

causing a pulse in place of each symbol. Among different pulse shapes available, square root

raised cosine pulse shape is mostly used. This data is then converted to analog and transmitted

over channel.

On the reception of data, an analog to digital converter does the job to create discrete data.

Matched filter shapes the signal to ensure optimum detection and decision block gives the PAM

symbols, which are later converted to bits.

4.2.2 QUADRATURE AMPLITUDE MODULATION SYSTEM

A simple discrete time communication system using Quadrature Amplitude Modulation

(QAM) scheme is shown in Figure 28.

Pulse Shaping

Filter

DDS

Lookup Table

0 -1

1 +1

N

Pulse Shaping

Filter

DAC

Lookup Table

0 -1

1 +1

N

Serial to Parallel

Converter

PAM

Symbols

Pulses

PAM

Symbols

Pulses

Bits

Transmitter

Bits

Matched

Filter

DDS

Sampling ADC

Receiver

Matched

Filter Sampling

Decisions

Figure 28 - Quadrature Amplitude Modulation Transceiver



At the transmitter side, data bits are first converted to two parallel streams. These parallel

streams passes from their respective lookup tables and are mapped into symbols. Each 0 is

mapped to -1 and each 1 is mapped to +1. Symbols are then upsampled by N. These upsampled

symbols passes through a pulse shaping filter causing a pulse in place of each symbol. Now a

DDS provides the sin and cos signal to make inphase and quadrature components. This data is

then converted to analog and transmitted over channel.

On the reception of data, an ADC converts signal to discrete data. Inphase and quadrature

components are separated and matched filter computes the projection of these components and

decision block gives the QAM symbols, which are latter converted to bits.

4.2.3 MISCELLANEOUS MODULATION SCHEMES

Other than different variations of the above-mentioned schemes, Quadrature Phase Shift

Keying (QPSK) and Offset QPSK are popular. The PAM, QAM, QPSK, etc., are not limited

to 2-ary or 4-ary modulations as discussed in previous sections. The schemes can be used for

m-ary communication. They all fall in the category of linear modulation schemes.

4.2.4 SIGNIFICANCE OF SYMBOL TIMING RECOVERY

Symbol timing recovery is the soul of wireless communication and is requirement of every

communication system. The received data always needed to be aligned with receiver clock and

symbol timing recovery synchronizes the transmitter physical layer clock to receiver physical

layer clock. Next section discusses some symbol timing recovery schemes used for the above-

mentioned communication systems.

4.3 TIME SYNCHRONIZATION

Time synchronization at physical layer refers to symbol timing recovery and extracting the

phase and frequency of transmitter's timing clock at the receiver end [5] [6] [7] [8] [33] [34].

The basic idea is to estimate the unknown timing delay in the received pulse train. The output

of the matched filter can be seen as eye diagram and the ideal sampling instant is the center of

the eye diagram. Sampling other than center of eye diagram will cause dispersion in signal

space projection, hence makes impossible decision regions. Figure 29 shows that how the

symbol timing recovery states the receiver where to take sample from the output of the matched

filter.



Time synchronization can be done using feedforward or feedback mechanisms. Feedback

systems are of interest here and is discussed in next section.

4.3.1 FEEDBACK TIME SYNCHRONIZATION

Feedback systems adjust the synchronization parameters using the error signal in a recursive

manner and can operate at or higher than symbol rate [7]. Basic components of any feedback

symbol timing recovery system are shown in Figure 30.

Timing Error Detector uses a clock signal from the Voltage Controlled Clock (VCC) and

computes its difference from the output of matched filter. The output of the matched filter has

the transmitter’s clock which when compared with built in VCC generated clock causes error

signal. This error signal is filtered by loop filter and again used by VCC to adjust its clock.

4.3.2 DISCRETE TIME FEEDBACK SYMBOL TIMING SYNCHRONIZATION

The goal of symbol timing synchronization is to produce discrete samples at the matched filter

output during each symbol interval and select the sample that is at optimum instant. A discrete

time approach for the resolution of this issue is shown in Figure 31.

Received Signal

Sampling Instant

Sampling Decision

Symbol Timing

Recovery

Matched Filter

Figure 29 - Role of Symbol Timing Recovery

Timing Error

Detector Loop Filter

Voltage

Controlled Clock

Matched Filter

Figure 30 - Basic Components of Symbol Timing Recovery



The above shown approach relocates the samples to correct time instant using interpolation

technique. The interpolator, with the help of interpolation control, regenerates the matched

filter output, which is aligned to optimum sampling instant. Error feedback system uses

different types of interpolations, timing error detectors, loop filters and interpolation controllers

to achieve different synchronization schemes. These components that are used for

synchronization has different requirements as well as different performance capabilities. Few

of them are discussed in upcoming sections.

4.4 COMPONENTS OF SYMBOL TIMING SYNCHRONIZATION

This section discusses different types of timing error detectors, interpolator, interpolation

control and loop filter. These components working together can achieve different performance

levels of synchronization.

4.4.1 TIMING ERROR DETECTOR

Timing Error Detector (TED) generates discrete time error signal at symbol rate. This error

signal is the estimate of timing information extracted from the output of the matched filter. The

research works in [5] [6] [7] [8] and [35] describe different types of TED that can be used to

produce error signal by exploiting the output of the matched filter 𝑥(𝑘𝑇𝑠 + �̂�). Where 𝑘𝑇𝑠

represents the k-th symbol time and �̂� is the timing estimate. Few of the important types of

TEDs are discussed below.

4.4.1.1 MAXIMUM LIKELIHOOD TIMING ERROR DETECTOR

Maximum Likelihood Timing Error Detector (ML-TED) uses the slope of the symbols and

apply sign correction to get the error signal [8] [35]. To get the slope of the symbols, time

Interpolator Timing Error

Detector

Interpolation

Control

Matched Filter

Loop Filter

Output

Figure 31 - Discrete Time Feedback Symbol Timing Synchronization



derivative of the matched filter output �̇�(𝑘𝑇𝑠 + �̂�) is required. Discrete time differentiators

ℎ(𝑛) given by [35] can be used to find the derivative, which is defined as,

ℎ(𝑛) = {(−1)𝑛

𝑛𝑇𝑛 ≠ 0

0 𝑛 = 0 (4.1)

4.4.1.1.1 ERROR SIGNAL

The error signal of ML-TED is defined as the sign of matched filter output multiplied by the

derivative of the matched filter output.

𝑒(𝑘) = 𝑠𝑔𝑛{𝑥(𝑘𝑇𝑠 + �̂�)} × �̇�(𝑘𝑇𝑠 + �̂�) (4.2)

Where 𝑠𝑔𝑛{𝑥(𝑘𝑇𝑠 + �̂�)} are the estimate of data symbols.

4.4.1.1.2 STRUCTURE

Figure 32 shows the structure of ML-TED that is based on the above equation.

4.4.1.2 EARLY LATE TIMING ERROR DETECTOR

Early Late Timing Error Detector (EL-TED) is the same as ML-TED, but a time difference is

used to compute the derivative of the matched filter output.


The error signal of EL-TED is defined as the sign of matched filter output multiplied by the

time difference of the matched filter output.

𝑒(𝑘) = 𝑠𝑔𝑛{𝑥(𝑘𝑇𝑠 + �̂�)} × {𝑥((𝑘 + ∆)𝑇𝑠 + �̂�) − 𝑥((𝑘 − ∆)𝑇𝑠 + �̂�)} (4.3)

Matched Filter sgn

Discrete Time

Differentiator

𝑥(𝑘𝑇𝑠 + �̂�)

𝑠𝑔𝑛{𝑥(𝑘𝑇𝑠 + �̂�)}

�̇�(𝑘𝑇𝑠 + �̂�) 𝑒(𝑘)

Figure 32 - Maximum Likelihood Timing Error Detector



Where ∆ allows the adjustment of time difference and popular choice is 0.5.

4.4.1.2.2 STRUCTURE

Figure 33 shows the structure of EL-TED that is based on the above equation.

4.4.1.3 ZERO CROSSING TIMING ERROR DETECTOR

Zero Crossing Timing Error Detector (ZC-TED) tries to find the zero crossing of the eye

diagram produced by the output of matched filter. It always operates at two samples per symbol

and hence the matched filter should be operating at two samples per symbol or its output may

be down sampled.


The error signal of ZC-TED is defined as the difference of symbol estimates multiplied by one

of the two samples available at the output of the matched filter.

𝑒(𝑘) = 𝑥 ((𝑘 − 12⁄ )𝑇𝑠 + �̂�) × [𝑠𝑔𝑛{𝑥((𝑘 − 1)𝑇𝑠 + �̂�)} − 𝑠𝑔𝑛{𝑥(𝑘𝑇𝑠 + �̂�)}] (4.4)

Matched Filter sgn

Time

Difference

𝑥(𝑘𝑇𝑠 + �̂�)


𝑥((𝑘 + ∆)𝑇𝑠 + �̂�)− 𝑥((𝑘 − ∆)𝑇𝑠 + �̂�) 𝑒(𝑘)

Figure 33 - Early Late Timing Error Detector



4.4.1.3.2 STRUCTURE

Figure 34 shows the structure of ZC-TED that is based on the above equation.

4.4.1.4 GARDNER TIMING ERROR DETECTOR

Gardner Timing Error Detector (G-TED) is non-data-aided version of ZC-TED. G-TED also

tries to find the zero crossing of the eye diagram produced by the output of matched filter,

similar to ZC-TED. It requires matched filter to operate at two samples per symbol and

specifically designed to support phase shift keying modulation schemes [35].


The error signal of G-TED is defined similar to ZC-TED, instead of using symbol estimates,

samples of matched filter output is used.

𝑒(𝑘) = 𝑥 ((𝑘 − 12⁄ )𝑇𝑠 + �̂�) × [𝑥((𝑘 − 1)𝑇𝑠 + �̂�) − 𝑥(𝑘𝑇𝑠 + �̂�)] (4.5)

4.4.1.4.2 STRUCTURE

Figure 35 shows the structure of G-TED that is based on the above equation.

Unit Sample

Delay

𝑥((𝑘 − 1)𝑇𝑠 + �̂�)

sgn

Unit Sample

Delay

𝑥 ((𝑘 − 12⁄ )𝑇𝑠 + �̂�)

𝑒(𝑘)

𝑠𝑔𝑛 𝑥((𝑘 − 1)𝑇𝑠 + �̂�)

sgn


Matched Filter

𝑥(𝑘𝑇𝑠 + �̂�)

+ −

Figure 34 - Zero Crossing Timing Error Detector

Unit Sample

Delay

𝑥((𝑘 − 1)𝑇𝑠 + �̂�)

Unit Sample

Delay

𝑥 ((𝑘 − 12⁄ )𝑇𝑠 + �̂�)

𝑒(𝑘)

Matched Filter

𝑥(𝑘𝑇𝑠 + �̂�)

+ −

Figure 35 - Gardner Timing Error Detector



4.4.1.5 MUELLER AND MULLER TIMING ERROR DETECTOR

Mueller and Muller Timing Error Detector (MM-TED) uses symbol estimates as well as

matched filter output operating at one sample per symbol.


The error signal of MM-TED is defined as,

𝑒(𝑘) = 𝑠𝑔𝑛{𝑥((𝑘 − 1)𝑇𝑠 + �̂�)}𝑥(𝑘𝑇𝑠 + �̂�) − 𝑠𝑔𝑛{𝑥(𝑘𝑇𝑠 + �̂�)}𝑥((𝑘 − 1)𝑇𝑠 + �̂�) (4.6)

4.4.1.4.2 STRUCTURE

Figure 36 shows the structure of MM-TED that is based on the above equation.

4.4.2 INTERPOLATOR

Interpolation is required to compute interpolant from given number of symbols, which is the

output of matched filter, can be done in various ways where the polynomial interpolation is

common [5] [6] [8] and is discussed below. Before getting into details of interpolation,

fractional interval 𝜇(𝑘) and basepoint index 𝑚(𝑘) needs to be discussed.

Fractional interval and basepoint index is computed by interpolation control, discussed in next

section, and provided to interpolator for the computation of interpolant. Basepoint index refers

to the n-th sample 𝑥(𝑛𝑇) after which the interpolant is required and k-th fractional interval

𝜇(𝑘) refers to the exact location of the interpolant 𝑥 ((𝑚(𝑘) + 𝜇(𝑘))𝑇) from the k-th

basepoint index 𝑚(𝑘) as shown in the Figure 37.


𝑥((𝑘 − 1)𝑇𝑠 + �̂�) Unit Sample

Delay

𝑒(𝑘)

Matched Filter 𝑥(𝑘𝑇𝑠 + �̂�)

+ − sgn

sgn

Figure 36 - Mueller and Muller Timing Error Detector



4.4.2.1 PIECEWISE POLYNOMIAL INTERPOLATION

Polynomial interpolation, as the name suggests, depends on the polynomial and the number of

samples used for interpolation depends on the degree of the polynomial. Increasing the number

of samples used for interpolation increases accuracy, but makes the timing recovery system

computationally expensive and complex. Special cases of polynomial interpolation are linear,

quadratic and cubic interpolation which can also be computed using farrow structure. Quadratic

interpolation is usually not desirable because it uses three samples and the interpolant does not

come out to be in the middle of samples. Hence resulting filter is not symmetric, which is not

a very acceptable approach from the point of view of implementation. Farrow structure used

for interpolation offers less computations, which is feasible from implementation point of view.

4.4.2.1.1 LINEAR INTERPOLATION

Linear interpolation requires two samples 𝑥((𝑚(𝑘) + 1)𝑇) and 𝑥(𝑚(𝑘)𝑇) and fractional

interval 𝜇(𝑘) to compute the interpolant and is defined as,

𝑥 ((𝑚(𝑘) + 𝜇(𝑘))𝑇) = 𝜇(𝑘)𝑥((𝑚(𝑘) + 1)𝑇) + (1 − 𝜇(𝑘))𝑥(𝑚(𝑘)𝑇) (4.7)

This computation of interpolant can also be done with the help of filter. The interpolator can

be designed as a symmetric FIR filter ℎ(𝑛) with coefficients ℎ(−1) = 𝜇(𝑘) and ℎ(0) = 1 −

𝜇(𝑘).

Interpolator

Interpolation

Control

Matched Filter

𝑥 ((𝑚(𝑘) + 𝜇(𝑘))𝑇)

𝜇(𝑘) 𝑚(𝑘)

𝑥(𝑛𝑇)

Figure 37 - Interpolation



4.4.2.1.2 CUBIC INTERPOLATION

Cubic interpolation requires four samples 𝑥((𝑚(𝑘) + 2)𝑇), 𝑥((𝑚(𝑘) + 1)𝑇), 𝑥(𝑚(𝑘)𝑇) and

𝑥((𝑚(𝑘) − 1)𝑇) and fractional interval 𝜇(𝑘) to compute the interpolant and is defined in [35]

as,

𝑥 ((𝑚(𝑘) + 𝜇(𝑘))𝑇)

= (𝜇(𝑘)3

6−

𝜇(𝑘)

6)𝑥((𝑚(𝑘) + 2)𝑇)

− (𝜇(𝑘)3

2−

𝜇(𝑘)2

2− 𝜇(𝑘)) 𝑥((𝑚(𝑘) + 1)𝑇)

+ (𝜇(𝑘)3

2− 𝜇(𝑘)2 −

𝜇(𝑘)

2+ 1) 𝑥(𝑚(𝑘)𝑇)

− (𝜇(𝑘)3

6−

𝜇(𝑘)2

2+

𝜇(𝑘)

3)𝑥((𝑚(𝑘) − 1)𝑇)

(4.8)

This computation of interpolant can also be done with the help of filter. The interpolator can

be designed as a symmetric FIR filter ℎ(𝑛) with coefficients:

ℎ(−2) =𝜇(𝑘)3

6−

𝜇(𝑘)

6

ℎ(−1) = −𝜇(𝑘)3

2+

𝜇(𝑘)2

2+ 𝜇(𝑘)

ℎ(0) =𝜇(𝑘)3

2− 𝜇(𝑘)2 −

𝜇(𝑘)

2+ 1

ℎ(1) = −𝜇(𝑘)3

6+

𝜇(𝑘)2

2−

𝜇(𝑘)

3

4.4.3 INTERPOLATION CONTROL

The research works in [5] [6] [8] discusses some interpolation controls that can be used with

the feedback synchronization systems. Interpolation control uses the output of the loop filter



𝑣(𝑛) to estimate kth basepoint index 𝑚(𝑘) and k-th fractional interval 𝜇(𝑘). Loop filters are

discussed in next section.

4.4.3.1 BASEPOINT INDEX

After every N samples an interpolant is required, which is based on the indication of basepoint

index, usually done using a strobe signal. The generation of strobe signal can be organized and

aligned with basepoint index using a modulo-1 counter register. This register counter value is

increased or decreased by 1/N such that it overflows or underflows after every N samples, and

generates a strobe signal. Assuming a decrementing counter that underflows after every N

samples, the value of the counter 𝜂(𝑛) modifies according to following equation.

𝜂(𝑛 + 1) = (𝜂(𝑛) − (1 𝑁⁄ + 𝑣(𝑛))) 𝑚𝑜𝑑 1 (4.9)

Or the above equation can be written as,

𝜂(𝑛 + 1) = 1 + 𝜂(𝑛) − (1 𝑁⁄ + 𝑣(𝑛)) (4.10)

Whenever 𝜂(𝑛 + 1) gives a negative value, the index n is the basepoint index 𝑚(𝑘). This

makes the above equation as,

𝜂(𝑚(𝑘) + 1) = 1 + 𝜂(𝑚(𝑘)) − (1 𝑁⁄ + 𝑣(𝑚(𝑘))) (4.11)

4.4.3.2 FRACTIONAL INTERVAL

Fractional interval for corresponding basepoint index 𝜇(𝑚(𝑘)) is the second concern of

interpolation control and can be computed from the values of the counter register 𝜂(𝑚(𝑘)) and

𝜂(𝑚(𝑘) + 1) as,

𝜇(𝑚(𝑘)) =𝜂(𝑚(𝑘))

1−𝜂(𝑚(𝑘)+1)+𝜂(𝑚(𝑘)) (4.12)

4.4.3.3 DESIGN

The design of interpolation control can be made using equation 4.11 and 4.12 and is shown in

the Figure 38.



4.4.4 LOOP FILTER

Time synchronization system is a Phase Lock Loop (PLL) that tracks the phase and frequency

error with the help of loop filter and its parameters can be controlled to adjust the acquisition

time and tracking performance [36]. Proportional plus integrator loop filter uses the output of

the timing error detector and can be used to track phase and frequency error, defined as,

𝐹(𝑠) = 𝐾1 +𝐾2

𝑠⁄ (4.13)

Where K1 and K2 are the loop constants on which error acquisition time and performance can

vary and is discussed in detail by [35]. The above filter can be realized as shown in Figure 39.

Loop

Filter

𝑣(𝑛)

1/𝑁

−

+

Modulo-1

Register

𝜇(𝑘)

𝑚(𝑘)

Figure 38 - Interpolation Control

Timing Error

Detector

𝑣(𝑛)

Loop

Constant K2

Loop

Constant K1

Unit Sample

Delay

Figure 39 - Loop Filter


Cross Layer Time Synchronization 49

CHAPTER # 5

CROSS LAYER TIME SYNCHRONIZATION

Cross layer approach presented in this thesis saves the computation and communication cost

required for the application layer timing offset. It computes the physical layer timing frequency

offset and apply it to application layer which saves energy required to transfer time stamps.

This chapter presents the details of the proposed model.

5.1 CROSS LAYER APPROACH

Application layer clocks are usually timers that count the oscillations of crystal and maintain

two registers to define that how many oscillations of crystal are equal to one application layer

clock tick [3]. Clock used for symbol timing synchronization at physical layer also counts the

oscillations of the same quartz crystal. Both clocks at the physical layer and application layer

are derived from the oscillation of quartz crystal, as the devices with one hardware oscillator

implement every clock within that device as,

𝐶(𝑡) = 𝑘 ∫ 𝜔(𝑡)𝑑𝑡 + 𝐶(𝑡0)𝑡

𝑡0 (5.1)

Where t is real-time, 𝜔(𝑡) is angular frequency of oscillator and k is the constant of

proportionality [29] and this fact is exploited to perform the cross layer time synchronization.

Time synchronization at physical layer is discussed in detail by [5] [6] [7] [8] [35]. In [8] many

symbol timing synchronization systems are discussed with different modulation schemes,



interpolators, timing error detectors, loop filters and interpolation control. One such symbol

timing synchronization system is shown in Figure 40.

Piecewise

Parabolic

Interpolator

( )x nTz

-1z

-1

2

ˆ( )x nT

1K

2Kz

-112

z-1

Update

µ

ˆ( )se kT

( )v n( )W n

Zero-Crossing TED

Loop Filter

Modulo 1 Counter

Interpolation Control

ˆ( )sx kT

Figure 40 - Binary PAM Symbol Timing Synchronization System for Physical Layer

This synchronization system is for binary Pulse Amplitude Modulation (PAM) and based on

Zero-Crossing Timing Error Detector (ZC-TED) using a piecewise parabolic interpolator,

proportional plus integrator loop filter and modulo-1 counter interpolation control. It is

designed to track and compensate for the phase and frequency error of the physical layer clock.

The output of the matched filter 𝑥(𝑛𝑇) is fed to piecewise parabolic interpolator for k-th

interpolant, which is defined as,

𝑥 ((𝑚(𝑘) + 𝜇(𝑘))𝑇)

= (𝜇(𝑘)3

6−

𝜇(𝑘)

6)𝑥((𝑚(𝑘) + 2)𝑇)

− (𝜇(𝑘)3

2−

𝜇(𝑘)2

2− 𝜇(𝑘)) 𝑥((𝑚(𝑘) + 1)𝑇)

+ (𝜇(𝑘)3

2− 𝜇(𝑘)2 −

𝜇(𝑘)

2+ 1) 𝑥(𝑚(𝑘)𝑇)

− (𝜇(𝑘)3

6−

𝜇(𝑘)2

2+

𝜇(𝑘)

3)𝑥((𝑚(𝑘) − 1)𝑇)

(5.2)



Where 𝑚(𝑘) is basepoint index and 𝜇(𝑘) is the fractional change and these two values are

computed by modulo-1 counter interpolation control and fed to interpolator.

The output of the interpolator is processed by ZC-TED operating at 2 samples/symbol which

tries to find the zero crossing in the eye diagram and generates no error when perfectly aligned

[8] [35]. The timing error signal is given by,

𝑒(𝑘) = 𝑥 ((𝑘 + 12⁄ )𝑇𝑠 + �̂�) [𝑎(𝑘 − 1) − 𝑎(𝑘)] (5.3)

Where 𝑎(𝑘) and 𝑎(𝑘 − 1) are symbol decisions for binary PAM and defined as,

𝑎(𝑘 − 1) = 𝑠𝑔𝑛 𝑥((𝑘 − 1)𝑇𝑠 + �̂�) (5.4)

𝑎(𝑘) = 𝑠𝑔𝑛{𝑥(𝑘𝑇𝑠 + �̂�)} (5.5)

The output of the loop filter, with constants K1 and K2, is fed to modulo-1 interpolation control

to compute the estimate of fractional interval and basepoint index. K1 and K2 can be computed

using Kp and K0 (loop gains), Bn (noise bandwidth), Ts (symbol time), T (sample time), 𝑁 =

𝑇𝑠𝑇⁄ and loop parameter 𝜉 [5] [6] [8]. Tracking performance and acquisition time of the

synchronization system depends on the above parameters of loop filter. Modulo-1 counter

interpolation control uses the output of loop filter 𝑣(𝑛) to find the basepoint index 𝑚(𝑘) and

fractional interval 𝜇(𝑘). The fractional interval is computed using the modulo-1 counter values

𝜂 and the following equation,

𝜂(𝑛 + 1) = (𝜂(𝑛) − 𝑊(𝑛)) 𝑚𝑜𝑑 1 (5.6)

Where 𝑊(𝑛) = 1

𝑁+ 𝑣(𝑛). Whenever the value of 𝜂 underflows then 𝑛 = 𝑚(𝑘).

Now to find the fractional interval 𝜇(𝑘) for the computed basepoint index 𝑚(𝑘) we have,

𝜇(𝑚(𝑘)) =𝜂(𝑚(𝑘))

𝑊(𝑚(𝑘)) (5.7)

𝜇(𝑘) and 𝑚(𝑘) is now used to compute the next interpolant. Using the above iterative

synchronization system, the variations of fractional change 𝜇 can be used to compute the actual

frequency offset. Different methods for computation of frequency offset are illustrated by [5]



[6] [7] [8]. The frequency offset is computed here using the slope of the fractional change and

new sampling rate can be given by the equation below to achieve time synchronization at the

physical layer.

𝑓𝑠 = (2 + 𝑚)𝑓𝑑 (5.8)

Where 𝑓𝑠 is new sampling rate, 𝑓𝑑 is symbol rate and m is the slope of the fractional change.

Time synchronization at application layer can simply be modeled as transmission of master

node time stamp to other nodes and correction of phase and frequency when using FTSP. FTSP

is a very widely used time synchronization protocol at application layer because of the benefits

offered by it. Master node wraps its time stamp in a message and transmit message to all

receivers in the distributed network. This message instruct the receivers to note their clock

values and compare it with the time stamp received to perform synchronization. In this way,

FTSP plays a very vital role for synchronization at the application layer. Figure 41 shows time

synchronization at application layer using FTSP protocol in a network of two receivers.

Master node broadcasts its time stamp to both receivers. On the reception of timestamps, these

receivers compare their clock values to the received timestamps and hence are synchronized.

Synchronization accuracy can be increased by increasing number of time stamp broadcasts.

Increasing broadcasts, however, reduces the energy efficiency of the synchronization protocol.

Single timestamp broadcast can only help for the phase correction. Multiple timestamp

broadcasts are required to get frequency synchronization. Frequency error can be calculated by

Figure 41 - Time Synchronization at Application Layer using FTSP

Master Node

Receiver A

Receiver B

Timestamp Broadcast

1-Application Layer Timestamp Broadcast

2-Timestamp Received

2-Timestamp Received

3-Timestamp Compared

3-Timestamp Compared

4-Phase Offset Corrected

4-Phase Offset Corrected

5-Repeat Step 1-4 for Skew Correction

5-Repeat Step 1-4 for Skew Correction

Master Node Receiver A Receiver B



finding the slope of the line created by the time stamps. A simple method to find the slope or

frequency error 𝑓𝑒 is,

𝑓𝑒 =𝑦𝑛−𝑦1

𝑥𝑛−𝑥1 (5.9)

Where 𝑦𝑛 and 𝑦1 are the n-th and 1st timestamps of the receiver A, 𝑥𝑛 and 𝑥1 are the n-th and

1st timestamps of the receiver B. Least Square (LS) estimate [37] can give a better estimate of

frequency error. LS estimate can be applied to the timestamps exchanged to get the estimate of

straight line. Unlike the first method, LS uses all the timestamps to compute the slope and

hence more accurate. The slope of the line is frequency offset at the application layer.

Timestamps are used in LS estimate and error is minimized, which is given by,

𝑒 = ∑ (𝑦𝑖 − 𝑦�̂�)2𝑁

𝑖=1 (5.10)

Where 𝑦𝑖 are timestamps and 𝑦�̂� are points of computed straight line given by 𝑦 = 𝑚𝑥 + 𝑐 and

to find m and c the least square estimate of a straight line is,

[𝑚𝑐] = (𝑋𝑇𝑋)−1𝑋𝑇𝑌 (5.11)

Where X and Y corresponds to the timestamps of receiver A and receiver B.

Time synchronization has to be done at physical layer and application layer of any distributed

wireless networks. Whenever the time needs to be synchronized at two different nodes, it starts

from the synchronization at physical layer and then synchronize at the application layer. The

model proposed in this thesis, shown in Figure 42, enlightens that the heart of both layer's clock

is quartz crystal.



Figure 42 - Cross Layer Time Synchronization

Once the synchronization at the physical layer is achieved, frequency offset of physical layer

clock can be applied to the application layer clock which saves energy required to synchronize

at the application layer. The nodes, using the cross layer time synchronization is assumed to be

synchronized in phase or phase synchronization can be achieved by using one timestamp of

any application layer protocol like FTSP.

To elaborate the cross layer approach, flowcharts are shown in Figure 43. At physical layer,

symbol timing recovery is applied, frequency offset is estimated and applied to physical layer

clock. At application layer, timestamps are broadcast, frequency offset is estimated and applied

to application layer clock. In cross layer design, symbol timing recovery is applied, frequency

offset is estimated and applied to physical layer clock as well as application layer clock. The

physical layer model revised to show the cross layer model and is shown in Figure 44.



Figure 43 - Flowcharts of Time Synchronization at Different Layers

Figure 44 – Physical Layer and Application Layer Role in Cross Layer Model


Simulation, Experimentation and Results 56

CHAPTER # 6

SIMULATION, EXPERIMENTATION AND RESULTS

This chapter shows simulations, experimentations, and mathematical results of the central idea

presented in the previous chapter. It analyzes the cross layer time synchronization approach

based on the achieved results.

6.1 SIMULATION

Some of the simulation results that support the proposed cross layer design approach are

discussed here. These simulations just provide the proof of concept before the actual hardware

experimentation is discussed in the next section.

Simulations are done using MATLAB and consists of two synchronization systems, one at the

physical layer and one at the application layer. The physical layer clock synchronization is

simulated using the symbol timing synchronization. Binary PAM is used as the modulation

scheme at the transmitter side with symbols +1 and -1. 3000 random symbols are generated

with a symbol rate of 1000 symbols/sec. The sampling rate is set to be 8000 samples/sec. The

samples per symbol are computed to be 8. The binary PAM symbols are up-sampled by 8 and

pulse shaped using a square root raise cosine with 50 percent excess bandwidth and transmitted

over an ideal channel. It is assumed that a frequency offset of (1 −

901 900) = 1.111111 × 10−3⁄ is present between the sampling (physical layer) clocks of

transmitter and receiver. At the receiver side, the data after matched filter is down-sampled to

2 samples/symbol and fed to symbol timing synchronization system using ZCTED, piecewise



parabolic interpolator, proportional plus integrator loop filter and modulo 1 counter interpolator

control. The values that are assumed for loop filter are 𝐵𝑛𝑇𝑠 = 0.005, 𝜉 = 1 √2⁄ , 𝐾𝑝 =

2.7, 𝐾0 = −1, 𝑁 = 2. The noise bandwidth, loop filter parameters, etc. are adjusted to get the

optimal performance of the synchronization loop. They are directly related to the time used for

tracking and correction of error and also related to the jitter of the physical layer clock. If

different choices for these parameters are made than time required to track error and the output

jitter varies. The selected values are suitable for proposed cross layer approach. The physical

layer simulation results are shown in Figure 45 which are in term of fractional interval and

timing error.

The simulation results show the plot of fractional interval and now the frequency offset can

be computed, i.e. , equal to the slope 1/450 = 2.222222 × 10−3 divided by the factor used

for up-sampling, which is two here and hence the frequency offset is computed to be

1.111111 × 10−3. Furthermore, the clock jitter can be seen as small variations along the line

of fractional interval and it is Gaussian in nature. The mean of Gaussian distribution refers to

the phase offset of the clock.

Figure 45 - Timing Error and Fractional Interval Over 3000 Symbols at Physical Layer



Now same transmitter and receiver with this frequency offset are considered for the application

layer clock. Simulated application layer clock counts the oscillations of a generated sine waves

for transmitter and receiver having the frequency offset. These sine waves are related to the

output of hardware clock, i.e., oscillations of quartz crystal. Application layer clock of the

transmitter is assumed to be run for 500 seconds. The transmitter application layer clock starts

from 1 and counts till 100000 within 500 seconds whereas the receiver application layer clock

starts from 1 and counts till 99889 and they keep exchanging their clocks. Slope of the

estimated line is computed to be ((10000 − 1)/(99889 − 1)) in presence of no noise and

frequency offset is 1 − ((10000 − 1)/(99889 − 1)) = 1.111244 × 10−3 which is

approximately same as of physical layer frequency offset computed earlier. Hence, this

simulation shows that the frequency offsets at the physical layer (1.111111 × 10−3) and

application layer (1.111244 × 10−3) between clocks are related and close to each other as

they both are based on same hardware oscillator within a node of network. This proves that

application layer clock frequency adjustment can be made using physical layer clock frequency

offset and provides a proof of concept to cross layer time synchronization.

Few more simulations are performed. It is assumed that a hardware clock skew of -4.9751x10-3

is present between the sampling clocks of transmitter and receiver. The simulation results are

shown in Figure 46 which are in term of fractional interval.

Computed skew from above simulation is equal to the slope -1/101 = -9.90099x10-3 divided by

the up-sampling factor, i.e., -4.9505x10-3. It is known for the same transmitter receiver pair that

application layer clock skew is -4.9653x10-3 because if the transmitter and receiver clock runs

for 500 seconds, transmitter clock counts from 1 to 100000 and receiver clock counts from 1

to 100499, then skew is 1-((10000-1)/(100499-1)) = -4.9653x10-3. Skew estimated at physical

layer is applied to application layer clock of receiver which leaves a negligible error of

0.0148x10-3. The data symbols received also include transmitter’s application layer clock phase

Figure 46 - Slope of fractional interval shows negative skew of -4.9505x10-3



which can be used to correct receiver’s application layer clock phase. After phase and skew

correction at application layer, transmitter and receiver clock runs synchronously.

Some other simulations are also performed between various transmitter receiver pairs having

versatile skew offsets that are summarized as follows.

Simulation I Simulation II

Hardware Skew -4.9751x10-3 -2.4938x10-3 Tx Clock Values 1 to 100000 1 to 100000 Rx Clock Values 1 to 100499 1 to 100249 App Layer Skew -4.9653x10-3 -2.4838x10-3 Phy Layer Skew -4.9505x10-3 -2.4876x10-3 Error left 0.0148x10-3 0.0038x10-3 %age Error 0.298% 0.153% Simulation Result Figure 46 Figure 47

Simulation III Simulation IV

Hardware Skew -1.6639x10-3 -1.2484x10-3 Tx Clock Values 1 to 100000 1 to 100000 Rx Clock Values 1 to 100166 1 to 100124 App Layer Skew -1.6573x10-3 -1.2385x10-3 Phy Layer Skew -1.6667x10-3 -1.2438x10-3 Error left 0.0094x10-3 0.0053x10-3 %age Error 0.567% 0.428% Simulation Result Figure 48 Figure 49

Simulation V Simulation VI

Hardware Skew 1.2500x10-3 1.6667x10-3 Tx Clock Values 1 to 100000 1 to 100000 Rx Clock Values 1 to 99875 1 to 99833 App Layer Skew 1.2516x10-3 1.6728x10-3 Phy Layer Skew 1.2469x10-3 1.6667x10-3 Error left 0.0047x10-3 0.0061x10-3 %age Error 0.376% 0.365% Simulation Result Figure 50 Figure 51

Simulation VII Simulation VIII

Hardware Skew 2.5000x10-3 5.0000x10-3 Tx Clock Values 1 to 100000 1 to 100000



Rx Clock Values 1 to 99750 1 to 99502 App Layer Skew 2.5063x10-3 5.0050x10-3 Phy Layer Skew 2.5000x10-3 5.0000x10-3 Error left 0.0063x10-3 0.0050x10-3 %age Error 0.251% 0.099% Simulation Result Figure 52 Figure 53






Figure 50 - Slope of fractional interval shows positive skew of 1.2500x10-3






6.2 EXPERIMENTATION

Experimentation setup for the proposed model includes two Digital Signal Processing Kits

(TMS320C6713 DSK) explained in Appendix-A. The experimentation consists of two

synchronization systems, one at the physical layer and other at the application layer. The

frequency offset computed at both layers come out to be same which shows that the physical

layer frequency offset can be used to adjust the application layer clock. Keeping this in mind,

an experimental setup is created that uses two DSKs connected together as shown in Figure 54.

Figure 54 - Experimental Setup

DSK A acts as a transmitter and DSK B acts as a receiver. Both DSKs needs to be synchronized

in time. DSK A uses binary Pulse Amplitude Modulation (PAM) with symbols +1 and -1.

Symbols are generated with a symbol rate of 4000 symbols/sec. The sampling rate is set to be

16000 samples/sec. The samples per symbol are computed to be four and total samples are

22000. Binary PAM symbols are up-sampled by four and pulse shaped using a square root raise

cosine with fifty percent excess bandwidth and transmitted over the channel to DSK B. DSK

B initialize it’s processing from match filtering the data. Matched filter uses the square root

raise cosine with fifty percent excess bandwidth. Symbols are down sampled to two

samples/symbol and fed to the time synchronization system at the physical layer. Time

synchronization at DSK B involves piecewise parabolic interpolator, zero crossing timing error

detector, proportional plus integrator loop filter and modulo-1 decrement counter interpolation

control. The parameters that are needed for the loop filter for acquisition and tracking efficiency

are 𝐵𝑛𝑇𝑠 = 0.005, 𝜉 = 1√2

⁄ , 𝐾𝑝 = 2.7, 𝐾0 = −1,𝑁 = 2. A graph of the fractional interval is

obtained and shown in Figure 55. The slope of the fractional interval increases with time

showing the positive frequency offset. So there is a frequency offset between the clocks of

DSK A and DSK B.



Figure 55 - Timing Error and Fractional Interval over 22000 Symbols

This variation in fractional interval shows that clocks have the frequency offset and the slope

of the fractional interval is used to compute this offset. LS estimate is used to find the slope of

the fractional interval. This estimate improves by increasing the number of symbols transmitted

as shown in Figure 56.



Figure 56 - Physical Layer frequency Offset Computed for Various Number of Symbols Transmitted

LS is applied to the fractional interval graph using different number of transmitted symbols.

The result shows that estimate of frequency offset improves in accuracy by increasing the

number of transmitted symbols. The physical layer offset over 22000 symbols is found to

1.3139 ppm.

Clock jitter of DSK B is found by taking the histogram of the variations in clock and comes

out to be Gaussian as shown in Figure 57. These clock variations are also visible in fractional

interval plot shown above and hence fractional interval results can be used to visualize the

clock jitter.



Figure 57 - Clock Jitter

DSK A transmits its time stamps to DSK B. On the reception of time stamp message, DSK B

also note down its clock value. A total of twenty two timestamps are transmitted from DSK A

to DSK B. These timestamps are used to compute the frequency offset at the application layer.

Application layer frequency offset is estimated using LS estimate on the timestamps. Figure 58

corresponds to the application layer clocks of DSK A and DSK B running untethered.



Figure 58 - Application Layer Clocks of DSK A and DSK B Estimated using LS

Clock 1 is the clock of DSK A and clock 2 is the clock of DSK B. LS estimate is used to

estimate the frequency offset of the application layer clocks. The slope of the line corresponds

to the frequency offset of the application layer clocks running on DSK A and DSK B. Figure

59 shows the application layer frequency offset between the clocks of DSK A and DSK B

computed using different number of timestamps.



Figure 59 - Application Layer Frequency Offset computed using various Number of Timestamps

The frequency offset is computed here using two to twenty two numbers of timestamps and as

shown, increasing number of time stamp increases the accuracy of the computed frequency

offset. The application layer clock offset comes out to be 1.4557 ppm for twenty two

timestamps which is nearly same as the physical layer offset that is 1.3139 ppm.

Figure 60 shows a comparison of the physical layer frequency offset and application layer

frequency offset.



Figure 60 - Comparison of Application Layer and Physical Layer Frequency Offset

The frequency offset at the application layer and at physical layers converges to nearly same

value. If accuracy needs to be improved than greater number of timestamps are required to

converge the frequency offset to the physical layer frequency offset. This comparison shows

that the frequency offset at both layers of nodes is the same as expected and the physical layer

frequency offset can be applied to application layer clocks for the correction of clock

frequency. This approach saves the amount of energy required to distribute timestamps and

compute frequency offset at the application layer, as physical layer frequency offset can be

applied at application layer.

Few more experiments are performed on different set of DSKs. The existing skew of hardware

clocks of the used DSKs are computed with the help of multiple timestamps and applying

regression techniques. Over the exchange of 22 timestamps the computed skew is of

3.4501x10-6 as shown in Figure 61.



Proposed system is implemented on DSK Rx which first computes the physical layer clock

skew. The physical layer configuration are shown in table below.

Modulation Scheme Binary Pulse Amplitude Modulation

Symbols +1, -1

Total Symbols Generated 22000

Symbol Rate 4000 symbols/sec

Total Transmission Time 5.5 sec

Sampling Rate 16000 samples/sec

Samples per Symbol 4

Pulse Shaping Filter Square Root Raise Cosine

Excess Bandwidth 50%

Up-sampling factor 2

Using fractional interval data (shown in Figure 62), physical layer clock skew is estimated

which comes out to be 3.6042x10-6 shown in Figure 63. This estimated skew is applied for

correction of application layer clock skew of DSK Rx that has a hardware skew of 3.4501x10-6

which leaves a negligible error of 0.1541x10-6. Furthermore, the transmitted packet does

include the clock phase offset, which is used to correct application layer clock phase of DSK

Figure 61 - Hardware clock skew of used DSKs



Rx. Hence, one packet is enough to synchronize transmitter-receiver pair in both phase and

skew at physical layer as well as application layer.

Figure 62 - Fractional interval with skew of 3.6042x10-6

Figure 63 - Physical Layer Clock Skew Estimate for Experiment I



For 2nd experiment, using the same DSKs yields fractional interval and physical layer clock

skew of 3.3033x10-6 as shown in Figure 64 and Figure 65.


Figure 65 - Physical Layer Clock Skew Estimate for Experiment II



3rd and 4th experiment is conducted using a new set of DSKs acting as transmitting and

receiving DSKs. The hardware clock skew can be found by repeating the same procedure of

exchanging multiple timestamps and it comes out to be 1.4875x10-6 as shown in Figure 66.

The physical layer clock skew computed for 3rd experiment is 1.3809x10-6 shown in Figure 67

and Figure 68, and for the 4th experiment it is 1.3139x10-6 shown in Figure 69 and Figure 70.

Figure 66 - Hardware clock skew of used DSKs for experiment III

and IV




Figure 68 - Physical Layer Clock Skew Estimate for Experiment III



The experimentation results are summarized as follows.


Figure 70 - Physical Layer Clock Skew Estimate for Experiment

IV



Experiment I Experiment II

Hardware Skew 3.4501x10-6 3.4501x10-6

Phy Layer Skew 3.6042x10-6 3.3033x10-6

Error left at App Layer 0.1541x10-6 0.1468x10-6

Experiment III Experiment IV

Hardware Skew 1.4875x10-6 1.4875x10-6

Phy Layer Skew 1.3809x10-6 1.3139x10-6

Error left at App Layer 0.1072x10-6 0.1736x10-6

6.3 MATHEMATICAL ANALYSIS

This section provides the mathematical analysis for energy efficiency, Cramer-Rao Lower

Bound (CRLB), symbol rate and total symbols in cross layer packet and Bayesian estimate.

6.3.1 ENERGY EFFICIENCY

Cross layer design make any distributed system energy efficient. In this section, energy

efficiency of the proposed cross layer design is analyzed. Energy at the application layer is the

energy required to transmit timestamps. A timestamp transmission corresponds to one packet

transmission and the energy required to transmit one packet is the same amount of energy

required to transmit one timestamp. Keeping this in mind, energy consumption at the

application layer can be written as,

𝐸𝐴𝑃𝑃 = 𝐸𝑃 × 𝑁𝑃 (6.1)

Where 𝐸𝐴𝑃𝑃 is the energy at application layer, 𝐸𝑃 is the energy required to transmit one packet

and 𝑁𝑃 is the number of packets or timestamps required to achieve frequency error correction

at application layer clock. Equation 6.1 shows that increasing number of packets will increase

the energy requirements at the application layer whereas the accuracy of frequency offset

computation increases. Energy required per packet is defined in terms of total bits in a packet

and total bits in a sample as,

𝐸𝑃 =𝑁𝑏

𝑁𝑚× 𝐸𝑆 (6.2)



Where 𝑁𝑏 are the bits in one packet or time stamp, 𝑁𝑚 are the bits in one sample and 𝐸𝑆 is the

energy required to transmit one sample. 𝑁𝑏 holds a direct relation to 𝐸𝑃 which means that

increasing bits in a packet will increase the energy required per packet. 𝑁𝑚 holds inverse

relation to 𝐸𝑃 reveals that decrease in number of bits per sample will increase energy

requirement. Using equations 6.1 and 6.2, application layer energy can be written as,

𝐸𝐴𝑃𝑃 =𝑁𝑃𝑁𝑏

𝑁𝑚× 𝐸𝑆 (6.3)

Above equation shows that application layer energy will increase with the increase in energy

required to transmit one sample, number of packets and number of bits per packet.

Energy at the physical layer can be defined using energy required to transmit one symbol and

total number of symbols need to be transmitted,

𝐸𝑃𝐻𝑌 = 𝐸𝑠𝑦𝑚 × 𝑁𝑠𝑦𝑚 (6.4)

Where 𝐸𝑃𝐻𝑌 is the energy at physical layer, 𝐸𝑠𝑦𝑚 is the energy required to transmit one symbol

and 𝑁𝑠𝑦𝑚 are the total symbols. Increase in symbol energy or symbols will increase the energy

requirement at physical layer. 𝐸𝑠𝑦𝑚 is defined as,

𝐸𝑠𝑦𝑚 =𝑁𝑏𝑠𝑦𝑚

𝑁𝑚× 𝐸𝑆 (6.5)

Where 𝑁𝑏𝑠𝑦𝑚 are the number of bits in one symbol. Analyzing above equation yields that

energy per symbol also have a direct relation with sample energy and inverse relation with bits

in one sample. Whereas increase in bits per symbol increases energy required to transmit one

symbol. Using equations 6.4 and 6.5, energy at the physical layer is written as,

𝐸𝑃𝐻𝑌 =𝑁𝑠𝑦𝑚𝑁𝑏𝑠𝑦𝑚

𝑁𝑚× 𝐸𝑆 (6.6)

Above equation shows that physical layer energy will increase with the increase in energy

required to transmit one sample, number of symbols and number of bits per symbol.

Energy efficiency of the proposed cross layer design can be defined as a ratio of energies at the

application layer and physical layer,



𝐸𝑒𝑓𝑓 =𝐸𝐴𝑃𝑃

𝐸𝑃𝐻𝑌 (6.7)

Where 𝐸𝑒𝑓𝑓 is the energy efficiency. Using equation 6.3 and 6.6 in 6.7 gives,

𝐸𝑒𝑓𝑓 =

𝑁𝑃𝑁𝑏𝑁𝑚

×𝐸𝑆

𝑁𝑠𝑦𝑚𝑁𝑏𝑠𝑦𝑚

𝑁𝑚×𝐸𝑆

(6.8)

Or,

𝐸𝑒𝑓𝑓 =𝑁𝑃𝑁𝑏

𝑁𝑠𝑦𝑚𝑁𝑏𝑠𝑦𝑚 (6.9)

Equation 6.9 shows that energy efficiency will increase if number of packets increases.

Similarly decreasing number of symbols also ensure increase in energy efficiency. The increase

in efficiency is linear as the number of packets increased, as shown in Figure 71.

Figure 71 – Energy Efficiency

0 0.5 1 1.5 2 2.5

x 104

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Number of cross layer packets

Energ

y E

ffic

ieny



6.3.2 CRAMER-RAO LOWER BOUND AND SYMBOL RATE

Cross layer design ensures usage of one packet to synchronize at physical layer as well as

application layer. The packet must have enough symbols so that the receiver can lock the timing

frequency offset. This packet also have a time stamp of the sender so that receiver can also

synchronize in timing phase. The number of symbols in this packet can be found by exploiting

the fact that application layer clock jitter and physical layer clock jitter is the same because

both have the same hardware clock. The Cramer-Rao Lower Bound (CRLB) is the minimum

possible variance of the timing frequency error at the physical layer, which is given by equation

6.10 for the PAM systems [8].

1

𝑇2 𝐶𝑅𝐿𝐵(𝜏) =1

8𝜋2𝜉

1𝐸𝑠𝑁0

(6.10)

Where T is the symbol time, 𝐶𝑅𝐿𝐵(𝜏) is the variance when timing frequency error 𝜏 is

estimated, 𝜉 is the loop parameter and 𝐸𝑠 is the symbol energy. If R is the symbol rate than

equation 6.10 is written as,

𝐶𝑅𝐿𝐵(𝜏) =1

8𝜋2𝜉𝑅2

1𝐸𝑠𝑁0

(6.11)

LS approach is applied to N time stamps t[n] to estimate the timing frequency offset at the

application layer. It gives the minimum LS error, which is variance [37],

𝑣𝑎𝑟(𝑡) = ∑ (𝑡[𝑛] − 𝑡̅)2𝑁−1𝑛=0 −

(∑ 𝑛𝑡[𝑛]−𝑁

2(𝑁−1)�̅�𝑁−1

𝑛=0 )2

𝑁(𝑁2−1)

12

(6.12)

As the cross layer design suggests that variance of clocks at both layers is the same, hence

equating 6.11 and 6.12 gives,

1

8𝜋2𝜉𝑅2

1𝐸𝑠𝑁0

= ∑ (𝑡[𝑛] − 𝑡̅)2𝑁−1𝑛=0 −

(∑ 𝑛𝑡[𝑛]−𝑁

2(𝑁−1)�̅�𝑁−1

𝑛=0 )2

𝑁(𝑁2−1)

12

(6.13)

The above equation is written in term of symbol rate as,

𝑅 =1

𝜋 √𝑁(𝑁2−1)

2

3𝜉

𝐸𝑠𝑁0

𝐴 (6.14)



Where 𝐴 =𝑁(𝑁2−1)

12∑ (𝑡[𝑛] − 𝑡̅)2𝑁−1

𝑛=0 − (∑ 𝑛𝑡[𝑛] −𝑁

2(𝑁 − 1)𝑡̅𝑁−1

𝑛=0 )2

Equation 6.14 shows that the synchronization accuracy given by N timestamps at the

application layer can be achieved using cross layer design with symbol rate R. The required

symbol rate decreases by increasing symbol to noise energy 𝐸𝑠

𝑁0 and number of time stamps N

as shown in Figure 72.

Figure 72 - Required Symbol Rate for Cross Layer Approach

6.3.3 CROSS LAYER PACKET

Now if total transmission time is 𝑇𝑇, then number of symbols 𝑁𝑆𝑌𝑀 in one cross layer packet

is computed as,

𝑁𝑆𝑌𝑀 = 𝑅 × 𝑇𝑇 (6.15)

Using equation 6.14 and 6.15 we have,



𝑁𝑆𝑌𝑀 =𝑇𝑇

𝜋 √𝑁(𝑁2−1)

2

3𝜉

𝐸𝑠𝑁0

𝐴 (6.16)

Number of symbols required in cross layer packet decreases by increasing the 𝐸𝑠

𝑁0 which is

shown in Figure 73.

Figure 73 - Required Symbols for Cross Layer Packet

Equation 6.16 gives the number of symbols in one cross layer packet that are required for

timing frequency synchronization which achieves the accuracy of application layer time

synchronization using N time stamps. Figure 74 shows the relation of number of time stamps

at the application layer and total symbols required in one cross layer packet.



Figure 74 - Required Symbols for Cross Layer Packet with Respect to Timestamps used at Application Layer

The total symbols in one cross layer packet that can be used for timing frequency

synchronization as well as timing phase synchronization is written as,

𝑇𝑆𝑌𝑀 = 𝑁𝑆𝑌𝑀 + 𝑃𝑆𝑌𝑀 (6.17)

Where 𝑇𝑆𝑌𝑀 are total symbols, 𝑁𝑆𝑌𝑀 are the symbols used for timing frequency synchronization

and 𝑃𝑆𝑌𝑀are the symbols used for timing phase synchronization, which are equal to the number

of symbols in one time stamp. Using equations 6.16 and 6.17 we have,

𝑇𝑆𝑌𝑀 =𝑇𝑇

𝜋 √𝑁(𝑁2−1)

2

3𝜉

𝐸𝑠𝑁0

𝐴+ 𝑃𝑆𝑌𝑀 (6.18)

Figure 75 shows the structure of the cross layer packet.



Figure 75 - Cross Layer Packet

6.3.4 BAYESIAN ESTIMATION

The clock jitter shown in simulation and experimentation results come out to be Gaussian and

that’s why the probability density function (pdf) for the physical layer skew estimate is

Gaussian and is written as,

𝑝(𝑃) =1

√2𝜋𝜎𝑃2𝑒

−12𝜎𝑃

2⁄ (𝑃−𝜇𝑃)2

(6.19)

Knowing that the skew estimate of physical layer is applied for the correction of application

layer clock skew and assuming that N packets of proposed model are used to further increase

accuracy. Conditional pdf is given as,

𝑝(𝑥|𝑃) =1

(2𝜋𝜎2)𝑁

2⁄𝑒𝑥𝑝 [−

1

2𝜎2∑(𝑥[𝑛] − 𝑃)2𝑁−1

𝑛=0

] (6.20)

Where x[n] are the packets. If �̅� is the mean of application layer clock skew then,

𝑝(𝑥|𝑃) =1

(2𝜋𝜎2)𝑁

2⁄𝑒𝑥𝑝 [−

1

2𝜎2∑ 𝑥[𝑛]2𝑁−1

𝑛=0

] 𝑒𝑥𝑝 [−1

2𝜎2(𝑁𝑃2 − 2𝑁𝑃�̅�)] (6.21)

Now,

𝑝(𝑃|𝑥) =𝑝(𝑥|𝑃)𝑝(𝑃)

∫ 𝑝(𝑥|𝑃)𝑝(𝑃)𝑑𝑃 (6.22)

And,



𝑝(𝑃|𝑥)

=

1

(2𝜋𝜎2)𝑁

2⁄𝑒𝑥𝑝 [−

12𝜎2 ∑ 𝑥[𝑛]2𝑁−1

𝑛=0 ] 𝑒𝑥𝑝 [−1

2𝜎2 (𝑁𝑃2 − 2𝑁𝑃�̅�)]1

√2𝜋𝜎𝑃2exp [−1

2𝜎𝑃2⁄ (𝑃 − 𝜇𝑃)

2]

∫ (1

(2𝜋𝜎2)𝑁

2⁄𝑒𝑥𝑝 [−

12𝜎2 ∑ 𝑥[𝑛]2𝑁−1

𝑛=0 ] 𝑒𝑥𝑝 [−1

2𝜎2 (𝑁𝑃2 − 2𝑁𝑃�̅�)]1

√2𝜋𝜎𝑃2exp [−1

2𝜎𝑃2⁄ (𝑃 − 𝜇𝑃)

2]) 𝑑𝑃

(6.23)

Or,

𝑝(𝑃|𝑥) =

𝑒𝑥𝑝 [−12 (

1𝜎2 (𝑁𝑃2 − 2𝑁𝑃�̅�) +

1𝜎𝑃

2 (𝑃 − 𝜇𝑃)2)]

∫ (𝑒𝑥𝑝 [−12 (

1𝜎2 (𝑁𝑃2 − 2𝑁𝑃�̅�) +

1𝜎𝑃

2 (𝑃 − 𝜇𝑃)2)])𝑑𝑃 (6.24)

And is written as,

𝑝(𝑃|𝑥) =𝑒𝑥𝑝 [−

12𝑍(𝑃)]

∫ (𝑒𝑥𝑝 [−12𝑍(𝑃)]) 𝑑𝑃

(6.25)

If,

𝑍(𝑃) =𝑁

𝜎2𝑃2 −

2𝑁𝑃�̅�

𝜎2+

1

𝜎𝑃2(𝑃 − 𝜇𝑃)

2 (6.26)

Or,

𝑍(𝑃) = (𝑁

𝜎2+

1

𝜎2)𝑃2 − 2(

𝑁

𝜎2�̅� +

𝜇𝑃

𝜎2)𝑃 +

𝜇𝑃2

𝜎2 (6.27)

Now if,

𝜎𝑃|𝑥2 =

1

𝑁𝜎2 +

1𝜎𝑃

2

(6.28)

And,

𝜇𝑃|𝑥 = (𝑁

𝜎2�̅� +

𝜇𝑃

𝜎2) 𝜎𝑃|𝑥

2 (6.29)

Then equation 6.27 becomes,



𝐵𝑚𝑠𝑒(�̂�) = 𝜎2

𝑁⁄ (𝜎𝑃

2

𝜎𝑃2 + 𝜎2

𝑁⁄) (6.37)

If Np are the total samples and P[nP] are the samples used to estimate the skew, then mean

of the physical layer clock skew can be written as,

𝜇𝑃 = −6

𝑁𝑃(𝑁𝑃 + 1)∑ 𝑃[𝑛𝑃]

𝑁𝑃−1

𝑛𝑃=0

+12

𝑁𝑃(𝑁𝑃2 − 1)

∑ 𝑛𝑃𝑃[𝑛𝑃]

𝑁𝑃−1

𝑛𝑃=0

(6.38)

And,

𝜎𝑃2 =

1

𝑁𝑃∑ (𝑃[𝑛𝑃] +

6


𝑁𝑃−1

𝑛𝑃=0

𝑁𝑃−1

𝑛𝑃=0

−12

𝑁𝑃(𝑁𝑃2 − 1)

∑ 𝑛𝑃𝑃[𝑛𝑃]

𝑁𝑃−1

𝑛𝑃=0

)

2

(6.39)

As defined earlier, 𝜎 is the variance and �̅� is the mean of application layer clock skew

which can be written as,

�̅� = ∑𝑥[𝑚]

𝑁

𝑁−1

𝑚=0

(6.40)

Using equation 6.38-6.40 in equation 6.35, we have,

�̂�

=

1𝑁𝑃

∑ (𝑃[𝑛𝑃] +6


𝑁𝑃−1𝑛𝑃=0 −

12𝑁𝑃(𝑁𝑃

2 − 1)∑ 𝑛𝑃𝑃[𝑛𝑃]

𝑁𝑃−1𝑛𝑃=0 )

2𝑁𝑃−1𝑛𝑃=0 ∑

𝑥[𝑚]𝑁

𝑁−1𝑚=0

𝜎2

𝑁⁄ +1𝑁𝑃

∑ (𝑃[𝑛𝑃] +6



12𝑁𝑃(𝑁𝑃

2 − 1)∑ 𝑛𝑃𝑃[𝑛𝑃]


2𝑁𝑃−1𝑛𝑃=0

+

𝜎2

𝑁⁄ (−6


𝑁𝑃−1𝑛𝑃=0 +

12𝑁𝑃(𝑁𝑃

2 − 1)∑ 𝑛𝑃𝑃[𝑛𝑃]


𝜎2

𝑁⁄ +1𝑁𝑃

∑ (𝑃[𝑛𝑃] +6



12𝑁𝑃(𝑁𝑃

2 − 1)∑ 𝑛𝑃𝑃[𝑛𝑃]



(6.41)

And for Bayesian estimate, equation 6.37 can be re-written as,



𝐵𝑚𝑠𝑒(�̂�)

= 𝜎2

𝑁⁄

(

1𝑁𝑃

∑ (𝑃[𝑛𝑃] +6



12𝑁𝑃(𝑁𝑃

2 − 1)∑ 𝑛𝑃𝑃[𝑛𝑃]



𝜎2

𝑁⁄ +1𝑁𝑃

∑ (𝑃[𝑛𝑃] +6



12𝑁𝑃(𝑁𝑃

2 − 1)∑ 𝑛𝑃𝑃[𝑛𝑃]



)

(6.42)

According to the proposed method, knowing the skew estimate at the physical layer will

estimate the application layer clock skew estimate given by the above equation. Increasing

number of cross layer packets will increase the accuracy of the skew estimates.

6.4 COMPARISON WITH FTSP

Keeping the above-mentioned results in view, FTSP requires multiple timestamps to estimate

the frequency offset of the application layer clock. However, only one cross layer packet is

enough for the compensation of phase and frequency offset for the physical layer clock as well

as application layer clock.


Conclusion 87

CHAPTER # 7

CONCLUSION AND FUTURE WORK

Cross-layer time synchronization save extra computations required for multiple timestamps

exchange and proves well for the energy constrained environments. The experimentation

results show that the heart of both the physical layer and application layer clock is hardware

oscillator and that's why the frequency offset computed at the physical layer between two nodes

is the same as the frequency offset at the application layer and can be corrected directly using

physical layer clock frequency offset. Hence, there will be no need to use any multiple message

exchange algorithm on the application layer to set the application layer clock frequency offsets

and this will save energy and prove useful for energy constrained networks. This cross layer

design can be used in any distributed wireless network like Wireless Sensor Network,

Cognitive Radio Networks (CRN) and cooperative communication networks. Future

dimensions of this approach can be estimating offsets in multi user case, such as cooperative

communication. Nodes don't have to participate in synchronization procedure sequentially as

for higher layer synchronization and instead a cross layer approach can estimate all offsets in

simultaneous cooperative synchronization. Cross layer approach can also be amended to fulfil

the time synchronization requirement for coordination in every CRN. Efficient implementation

of CRN depends on time synchronization during phases of dynamic spectrum management.

Furthermore, time synchronization also overcome wireless channel issues such as shadow

fading and interference. Cross layer approach can also be modified and analyzed by using feed

forward time synchronization methods for the physical layer clock correction.


TMS320C6713 DSP Starter Kit 88

APPENDIX – A

TMS320C6713 DSP STARTER KIT

This appendix presents the details of the digital signal processing kit TMS320C6713 DSK used

for the experimentation of the proposed method.

A.1 DIGITAL SIGNAL PROCESSING CHIPS

Digital signal processing chips were introduced in the early 1980’s and current major DSP

manufacturers include Texas Instruments (TI), Motorola, Lucent/Agere, Analog Devices,

NEC, SGS-Thomson, and Conexant (formerly Rockwell Semiconductor) [38] [39]. These

programmable chips are suitable for high-speed discrete time signal processing algorithms.

DSP chips are highly reliable in comparison with analog components used to perform some

specific task and comes in small sizes.

Commercial floating point DSP chips are first introduced by AT&T and TI in late 80s [38]. In

late 90s, TI introduced the TMS320C67x series of floating point DSP chips. These chips are

widely in used in various fields [38] [39] as shown in the Figure 76.



Figure 76 - Applications of Digital Signal Processing Chips in Various Fields

Various Texas Instruments DSP are available. TMS320C1s, C2x and C24x series is low cost,

fixed point chip with 16bit word length and can be used in motor control and disk head

positioning, etc., whereas C5x, C54x and C55x series is power efficient with same

specifications and can be used in wireless phones and modems, etc., and the high performance

chips which are available for communications infrastructure, xDSL, imaging and video, etc.,

are of series C62x, C3x, C4x, C64x and C67x (32bit) [38] [39].

Telecom

Telephone line modems

Cellular telephones

Answering Machines

ADPCM transcoders

Digital speech interpolation

Broadband wireless systems

Voice/Speech

Speech digitization and compression

Voice mail

Speaker verification

Speech synthesis

Automotive

Engine control

Antilock brakes

Active suspension

Airbag control

System diagnosis

Control System

Head positioning servo systems in disk drives

Laser printer control

Robot control

Engine and motor control

Numerical control of automatic machine tools

Military

Radar and sonar signal processing

Navigation systems

Missile guidance

HF radio frequency modems

Secure spread spectrum radios

Secure voice

Medical

Hearing aids

MRI imaging

Ultrasound imaging

Patient monitoring

Instrumentation

Spectrum analysis

Transient analysis

Signal generators

Image Processing

HDTV

Pattern recognition

Image enhancement

Image compression and transmission

3D rotation

Animation



A.2 TMS320C6713 DSP

The TMS320C6713 DSP is a 32bit floating point DSP, which is available by Texas Instruments

with a kit known TMS320C6713 DSK (DSP Starter Kit) discussed in next section. Other

members of same family are TMS320C6701, TMS320C6711, TMS320C6722, TMS320C6726

and TMS320C6727. Figure 77 shows the block diagram of TMS320C6713 DSP.

A.2.1 CENTRAL PROCESSING UNIT

The Central Processing Unit (CPU) of TMS320C6713 DSP has a very long instruction word

(VLIW) architecture known as VelociTi. The CPU fetch packet includes eight 32 bit

instructions and has eight functional units for its processing. Eight functional units include four

arithmetic and logic units (ALUs) that can perform fixed and floating-point operations (.L1,

.L2, .S1, .S2), two ALUs that perform only fixed-point operations and responsible for all data

transfers between the register files and memory (.D1, .D2) and two multipliers that can perform

fixed or floating point multiplications (.M1, .M2) [38] [39]. This architecture supports IEEE

single and double precision floating point numbers. This CPU contains a vectored priority

interrupt controller. Interrupts according to priority order are RESET, non-maskable interrupt

(NMI) and twelve lower priority maskable interrupts INT4–INT15. Interrupts can be of timers,

McBSP serial ports, McASP serial ports, EDMA channels and host port interface [39].

Figure 77 - TMS320C6713 DSP [38]



A.2.2 MEMORY

TMS320C6713 DSP has an L1/L2 memory architecture consisting of a 4K-byte L1P Program

Cache (direct-mapped), a 4K-byte L1D Data Cache (2-way set associative), and an L2 memory

with 256K-bytes total. This DSP also provides a 32-bit External Memory Interface (EMIF)

which can be used with SDRAM, Flash, SBSRAM, SRAM and EPROM [38] [39].

A.2.3 ENHANCED DIRECT MEMORY ACCESS CONTROLLER

Enhanced direct memory access (EDMA) controller is used to transfer data between the L2

cache/memory controller and the peripherals.

A.2.4 SERIAL PORTS

Two bidirectional multichannel buffered serial ports (McBSP0 and McBSP1) are available

with the TMS320C6713 DSP that operates independently and can transfer 8, 12, 16, 20, 24, or

32 bit words. It also includes two multi-channel audio serial ports (McASP0 and McASP1)

which is also useful for non-audio data, e.g., transferring data between two DSPs.

A.2.5 MISCELLANEOUS INTERNAL PERIPHERALS

The TMS320C6713 DSP contains two 32-bit general-purpose timers and are used to time

events, count events, generate pulses and interrupt the CPU. Host Port Interface (HPI) provides

a 16-bit interface to a host. Two I2C serial ports are included for control purposes. General

purpose input/output (GPIO) module can be individually programmed to be inputs or outputs

[38].

A.2.6 INSTRUCTION SET

Instruction set include instructions for fixed and floating-point addition, subtraction, and

multiplication as well as for logical operations, circular buffering, and data loading and storing.

Complete instruction set is shown in following table.

Table 1 - Instruction Set

.L unit .M unit .S unit .D unit

ABS MPY ADD ADD

ADD MPYU ADDK ADDAB



ADDU MPYUS ADD2 ADDAH

AND MPYSU AND ADDAW

CMPEQ MPYH B DISP LDB

CMPGT MPYHU B IRP LDBU

CMPGTU MPYHUS B NRP LDH

CMPLT MPYHSU B REG LDHU

CMPLTU MPYHL CLR LDW

LMBD MPHLU EXT LDB

MV MPYHULS EXTU MV

NEG MPYHSLU MV STB

NORM MPYLH MVC STH

NOT MPYLHU MVK STW

OR MPYLUHS MVKH STB

SADD MPYLSHU MVKLH STH

SAT SMPY NEG STW

SSUB SMPYHL NOT SUB

SUB SMPYLH OR SUBAB

SUBU SMPYH SET SUBAH

SUBC MPYDP SHL SUBAW

XOR MPYI SHR ZERO

ZERO MPYID SHRU ADDAD

ADDDP MPYSP SSHL LDDW

ADDSP SUB

DPINT SUBU

DPSP SUB2

DPTRUNPC XOR

INTDP ZERO

INTDPU LDBU

INTSP LDH

INTSPU LDHU

SPINT LDW

SPTRUNC ABSDP

SUBDP ABSSP

SUBSP CMPEQDP

CMPEQSP

CMPGTDP

CMPGTSP

CMPLTDP

CMPLTSP

RCPDP

RCPSP

RSQRDP



RSQRSP

SPDP

A.3 TMS320C6713 DSP STARTER KIT

The TMS320C6713 DSK is a board designed to use TMS320C6713 DSP and shown in Figure

78.

Figure 78 - Block Diagram of the TMS320C6713 DSP Starter Kit (DSK) [38]

The major DSK hardware features given by [38] [39] are,

1. A TMS320C6713 DSP operating at 225 MHz.

2. An AIC23 stereo codec with Line In, Line Out, MIC, and headphone stereo jacks

3. 16 Mbytes of synchronous DRAM (SDRAM)

4. 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default configuration)

5. Four user accessible LEDs and DIP switches

6. Software board configuration through registers implemented in complex logic device

(CPLD)



7. Configurable boot options

8. Expansion connectors for daughter cards

9. JTAG emulation through on-board JTAG emulator with USB host interface or external

emulator


Project Codes 95

APPENDIX – B

PROJECT CODES

This appendix presents the main code for transmitting and receiving TMS320C6713 DSKs

used for the experimentation of the proposed method.

B.1 CODE AT TRANSMITTING NODE

#include "DSK6713_AIC23.h" //codec support

#include "ps_filter.h"

#include "stdio.h"

Uint32 fs=DSK6713_AIC23_FREQ_16KHZ; //set sampling rate

#define DSK6713_AIC23_INPUT_MIC 0x0015

#define DSK6713_AIC23_INPUT_LINE 0x0011

#define File_buffer_size 23

Uint16 inputsource=DSK6713_AIC23_INPUT_LINE; // select input

int ctr = 4;

int time_cntr=0;

FILE *fptr;

float App_buff[File_buffer_size];


Project Codes 96

int x_index = 0;

float y=0;

short xcirc[33];

int N=33;

int newest=-1;

int k,i;

int app_ctr = 0,j=0;

/*int x=0;*/

short outsample;

short hD[5]={1,1,1,1,1};

short scrambled_bit;

short upsampled_data[4] = {0,0,0,0};

short send_now=0;

int n1,t;

short bit_cntr=0;

interrupt void c_int11() //interrupt service routine

{

if(ctr==4)

{

/*scrambled_bit = 0 ^ hD[4] ^ hD[1];

for(i=4;i>=1;i--) hD[i] = hD[i-1];

hD[0] = scrambled_bit;*/

if (scrambled_bit == 0)

scrambled_bit = 1;


Project Codes 97

else

scrambled_bit = 0;

send_now++;

if (send_now == 995)

scrambled_bit = 1;


scrambled_bit = 1;


scrambled_bit = 0;


scrambled_bit = 0;


scrambled_bit = 1;

if (send_now==1000)

{

scrambled_bit = 1;

n1 = time_cntr;

}

if (send_now>1000)

{

App_buff[app_ctr] = get_ctr(); //time_cntr;

app_ctr++;

if (app_ctr == 23)

{

for (j=0;j<File_buffer_size;j++)


Project Codes 98

fprintf(fptr,"%f\n",App_buff[j]);

fclose(fptr);

}

send_now=0;

}

upsampled_data[0] = (2 * scrambled_bit)-1;

ctr = 0;

}

if(++newest == N) newest = 0;

xcirc[newest] = upsampled_data[ctr];

ctr++;

y=0;

x_index = newest;

for (k = 0; k < N; k++)

{

y += ps_filter[k]*xcirc[x_index];

--x_index;

if(x_index == -1) x_index = N-1;

}

outsample = y*10000;

output_left_sample(outsample); //output data

return;

}

interrupt void c_int14(void)


Project Codes 99

{

if (app_ctr < 20000)

{

App_buff[app_ctr] = time_cntr++;

}

else

{

for (j=0;j<File_buffer_size;j++)

fprintf(fptr,"%d\n",App_buff[j]);

fprintf(fptr,"done");

fclose(fptr);

stop_timer_intr();

}

return;

}

void main()

{

fptr = fopen("app_clock_tx16.txt","w");

time_intr();

comm_intr(); //init DSK, codec, McBSP

while(1); //infinite loop

}

B.2 CODE AT RECEIVING NODE

#include "DSK6713_AIC23.h" //codec support

#include "stdio.h"


Project Codes 100

#include "ps_filter.h"

Uint32 fs=DSK6713_AIC23_FREQ_16KHZ; //set sampling rate

#define DSK6713_AIC23_INPUT_MIC 0x0015

#define DSK6713_AIC23_INPUT_LINE 0x0011

//#define File_buffer_size 96

#define File_buffer_size_full 23

#define File_buffer_size 23000

Uint16 inputsource=DSK6713_AIC23_INPUT_LINE; // select input

int file_i=0,file_j=0,fullfile_i=0;

float buffer_full[File_buffer_size_full],buffer[File_buffer_size];

FILE *fptrfull,*fptr;

int time_cntr=0;

int x_index = 0;

float y=0;

float xcirc[33]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};

int N=33;

int newest=-1;

int k,i;

//float K1=-0.0238820228073318, K2=-0.000796067426911059; //Bn = 0.05

float K1=-0.00246091906713941, K2=-0.00000820306355713136; //Bn = 0.005

//float locked_K1=-0.00246091906713941, locked_K2=-0.00000820306355713136; //Bn =

0.005

//float K1 = -0.000493498052126176, K2 = -3.28998701417451e-07;//Bn = 0.001

//float K1 = -0.00490545953118523, K2 = -3.27030635412349e-05;//Bn = 0.01

short sps_control=0;


Project Codes 101

float sym_buffer[4] = {0,0,0,0};

float v[3] = {0,0,0};

float eta=0, eta_new=0, mu_next=0, mu, li_int_out=0;

short underflow=0, old_underflow=0;

float Bf[2] = {0,0};

float e=0, last_e=0;

float vp=0, b=0, Fz_out=0, Wn=0;

short rec_bit = 0;

short li_int_sign,Bf1_sign;

short hD[5] = {1,1,1,1,1};

short descrambled_bit;

short outsample;

float insample;

short pass100=0,lastsix_bits[6]={0,0,0,0,0,0},ic=0;

short timestamp_flag=0;

short stamp_cntr=0;

short t_stamps=0;

short rec_ok = 0;


{

insample = input_left_sample(); //input data

if ((insample>1000) || (rec_ok == 1))

{

rec_ok = 1;

insample = insample/5000; //5000


Project Codes 102

if(++newest == N) newest = 0;

xcirc[newest] = insample;

y=0;

x_index = newest;

for (k = 0; k < N; k++)

{

y += ps_filter[k]*xcirc[x_index];

--x_index;

if(x_index == -1) x_index = N-1;

}

/*buffer[file_i] = y;

file_i++;*/

sps_control++;

if (sps_control==2) //down sample to 2

{

sps_control=0;

// timing recovery

eta = eta_new;

mu = mu_next;

sym_buffer[0] = sym_buffer[1];sym_buffer[1] = sym_buffer[2];sym_buffer[2]

= sym_buffer[3];

sym_buffer[3] = y;

v[0] = sym_buffer[1];

v[1] = -0.5 * sym_buffer[3] + 1.5 * sym_buffer[2] - 0.5 * sym_buffer[1] - 0.5 *

sym_buffer[0];

v[2] = 0.5 * sym_buffer[3] - 0.5 * sym_buffer[2] - 0.5 * sym_buffer[1] + 0.5 *

sym_buffer[0];


Project Codes 103

li_int_out = (mu * v[2] + v[1]) * mu + v[0]; // interpolator

if (underflow == 1)

{

if (li_int_out <= 0)

rec_bit = 0;

else

rec_bit = 1;

pass100++;

if (timestamp_flag==1) // framing done

{

if (stamp_cntr == 0)

{

buffer_full[fullfile_i] = get_ctr(); //time_cntr

fullfile_i++;

}

stamp_cntr=32; //++;

if (stamp_cntr == 32)

{

timestamp_flag=0;

pass100=100;

stamp_cntr=0;

lastsix_bits[0]=0;

lastsix_bits[1]=0;

lastsix_bits[2]=0;

lastsix_bits[3]=0;


Project Codes 104

lastsix_bits[4]=0;

lastsix_bits[5]=0;

}

}

if ((pass100>=100) && (timestamp_flag==0))

{

for(ic=5;ic>=1;ic--) lastsix_bits[ic] = lastsix_bits[ic-1];

lastsix_bits[0] = rec_bit;

if ((lastsix_bits[0]==1) && (lastsix_bits[1]==1) &&

(lastsix_bits[2]==0) && (lastsix_bits[3]==0) &&

(lastsix_bits[4]==1) && (lastsix_bits[5]==1))

{ // match sequence for framing

timestamp_flag=1;

t_stamps++;

}

}

/*descrambled_bit = rec_bit ^ hD[4] ^ hD[1];

for(i=4;i>=1;i--) hD[i] = hD[i-1];

hD[0] = descrambled_bit;

buffer[file_i] = descrambled_bit;

file_i++;*/

/*buffer_full[fullfile_i] = rec_bit;

fullfile_i++;*/

}

if ((underflow == 1) && (old_underflow == 0)) //ZCTED

{


Project Codes 105

if(Bf[1]<0) Bf1_sign = -1;

else if(Bf[1]==0) Bf1_sign = 0;

else Bf1_sign = 1;

if(li_int_out<0) li_int_sign = -1;

else if(li_int_out==0) li_int_sign = 0;

else li_int_sign = 1;

e = Bf[0] * (Bf1_sign - li_int_sign);

}

else

e = last_e;

last_e = e; //Loop filter

vp = K1 * e;

b = b + e * K2;

Fz_out = vp + b;

Wn = 0.5 + Fz_out;

eta_new = eta - Wn;

if ((underflow == 0) && (old_underflow == 0))

{

Bf[0] = Bf[0];

Bf[1] = Bf[1];

}


{

Bf[1] = Bf[0];

Bf[0] = li_int_out;


Project Codes 106

}


{

Bf[1] = Bf[0];

Bf[0] = li_int_out;

}


{

Bf[1] = li_int_out;

Bf[0] = 0;

}

if(eta_new<0)

{

eta_new = eta_new + 1;

old_underflow = underflow;

underflow = 1;

mu_next = eta/Wn;

if (file_i < File_buffer_size)

{

buffer[file_i] = mu_next;

file_i++;

}

}

else

{


Project Codes 107

old_underflow = underflow;

underflow = 0;

mu_next = mu;

}

}

outsample = (short)(insample * 10000);

if ((file_i== File_buffer_size) && (fullfile_i== File_buffer_size_full))

{

for (file_j=0;file_j<File_buffer_size; file_j++)

fprintf(fptr,"%f\n",buffer[file_j]);

fclose(fptr);

file_i=0;

for (file_j=0;file_j<File_buffer_size_full; file_j++)

fprintf(fptrfull,"%f\n",buffer_full[file_j]);

fclose(fptrfull);

fullfile_i=0;

}

output_left_sample(outsample); //output data

}

return;

}


{

//time_cntr++;


Project Codes 108

return;

}

void main()

{

fptr = fopen("mu.txt","w");

fptrfull = fopen("app_clock_rx11.txt","w");

time_intr();

comm_intr(); //init DSK, codec, McBSP

while(1); //infinite loop

}

B.3 PULSE SHAPING FILTER USED

float ps_filter[33]={-0.005053, -0.001911, 0.005359, 0.008226, 0.001516, -0.008226, -

0.007503, 0.007734, 0.021221, 0.007734, -0.037513, -0.078421, -0.053052, 0.078421,

0.289316, 0.487248, 0.568310, 0.487248, 0.289316, 0.078421, -0.053052, -0.078421, -

0.037513, 0.007734, 0.021221, 0.007734, -0.007503, -0.008226, 0.001516, 0.008226,

0.005359, -0.001911, -0.005053};

B.4 CODES FOR VARIOUS GRAPHS

The saved file from the DSK output is processed in MATLAB for various simulation graphs.


Nomenclature 109

NOMENCLATURE

𝜔(𝑡) Angular frequency of oscillator

𝑚(𝑘) Basepoint index

𝜇(𝑘) Fractional interval

𝑎(𝑘) Binary PAM kth symbol

𝑒(𝑘) Timing error signal

𝑓𝑠 Sampling rate

𝑓𝑑 Symbol rate

𝑚 Slope of the fractional change

𝑓𝑒 Frequency error

𝑦𝑖 ith timestamp of transmitter

𝑥𝑖 ith timestamp of receiver

𝐸𝐴𝑃𝑃 Energy at application layer

𝐸𝑃 Energy required to transmit one packet

𝑁𝑃 Number of packets

𝑁𝑏 Bits per packet

𝑁𝑚 Bits per sample

𝐸𝑆 Energy required to transmit one sample

𝐸𝑃𝐻𝑌 Energy at physical layer

𝐸𝑠𝑦𝑚 Energy required to transmit one symbol

𝑁𝑠𝑦𝑚 Total symbols for transmission

𝑁𝑏𝑠𝑦𝑚 Bits per symbol

𝐸𝑒𝑓𝑓 Energy efficiency

𝑇 Symbol time

𝜏 Timing frequency error

𝜉 Loop parameter


Nomenclature 110

𝑅 Symbol rate

𝑇𝑇 Total transmission time

𝑇𝑆𝑌𝑀 Number of symbols per cross layer packet

𝑁𝑆𝑌𝑀 Symbols used for timing frequency synchronization

𝑃𝑆𝑌𝑀 Symbols used for timing phase synchronization


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