department of computer engineering tallinn university of technology estonia 8 th european workshop...

Department of Computer EngineeringTallinn University of Technology

Estonia

8th European Workshop on Microelectronics Education – EWME‘2010Darmstadt, May 10-12, 2010

E-Learning Environment for WEB-Based Study of Testing E-Learning Environment for WEB-Based Study of Testing

R.Ubar1, A.Jutman1, J.Raik1,

S.Kostin1, H.-D.Wuttke2

1Dept. of Computer EngineeringTallinn University of Technology

Estonia

2Dept. of Technical InformaticsTechnical University of IlmenauGermany

E-Learning Environment for WEB-Based Study of TestingEWME May 10–12, 2010 2

MotivationMotivation

ITRS: semiconductor test is already one of key problems in current generation of VLSI chips and its importance will be growing

There is a strong demand for well-educated specialists in the area of IC and microelectronics testing

Interactive training tools as addendum to LMS are needed to facilitate teaching process

TUT has a 15 years tradition in developing training tools in microelectronic testing

Students develop the software themselves under supervision of graduate students and senior personnel

8th European Workshop on Microelectronics Education – EWME‘2010

3

Motivation

Cutting Edge Research−Needs custom developed algorithms

and/or tools

PhD Students−Need to run their experiments

Undergraduate Students−Need introduction to the topic

Department−Needs training materials and research


4

Outline

Different layers of the platform

HW tools

PC-based tools

Web interface

E-Learning tools

Conclusions and discussion


5


Web

Tools

PC

Tools

Hardware

Tools


6

Main components of the platform

DefSim - an integrated measurement environment for physical defect study in CMOS circuits.

TurboTester – a research and training toolkit with extensive set of tools for digital test and design for testability

Web-based runtime interface for remote access to our tools

Java applets – illustrative e-learning software written specifically for the web

Other tools


7


Web

Tools

PC

Tools

Hardware

Tools


8

Defect Study using DefSim

DefSim is an integrated circuit (ASIC) and a measurement equipmrnt for experimental study of CMOS defects.

The central element of the DefSim equipment is an educational IC with a large variety of shorts and opens physically inserted into a set of simple digital circuits.

The IC is attached to a dedicated measurement box serving as an interface to the computer. The box supports two measurement modes - voltage and IDDQ testing.

http://www.defsim.com


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− Standard industrial CMOS technology

− Area 19.90 mm2

− Approx. 48000 transistors− 62 pins− JLCC68 package

A built-in current A built-in current monitor for monitor for IIDDQDDQ testing testing is implemented in each is implemented in each block.block.

DefSim IC details


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NAND2 cell with floating gate NAND2 cell with floating gate

VDD

GND

QA

B

X

Implementation of defects


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VDD

GND

QA

B

NAND2 cell with D-S short (missing NAND2 cell with D-S short (missing poly) poly)

• Altogether there are over 500 different defects on the chip

• Implemented defects are shorts and opens in metal and poly layers

• To be close to the silicon reality each cell is loaded and driven by standard non-inverting buffers

Implementation of defects


12

DefSim in the classroom

With DefSim you can

Observe the truth table of correct circuit Observe the truth table of defective circuit Obtain defect/fault tables for all specific

defects Define test patterns automatically or manually Activate IDDQ and voltage measurements Study behavior of bridging and open faults Study and compare different fault models


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“Plug and Play” – dedicated hardware and software

DefSim lab environment


14


Web

Tools

PC

Tools

Hardware

Tools


15Used in 100+ institutions in 40+ countries

Design ErrorDiagnosis

TestGenerators

BISTEmulator

Design TestSet

FaultTable

Test SetOptimizer

FaultyArea

LogicSimulator

Defect Library

HazardAnalysis

Data

Specifi-cation

MultivaluedSimulator

FaultSimulator

http://www.pld.ttu.ee/tt

PC-Based Toolkit – Turbo Tester


16Used in 100+ institutions in 40+ countries

Design ErrorDiagnosis

TestGenerators

BISTEmulator

Design TestSet

Levels:GateMacroRTL

FaultTable

Test SetOptimizer

Methods:BILBOCSTPHybrid

FaultyArea

Circuits:CombinationalSequential

LogicSimulator

Formats:EDIFAGM

Defect Library

HazardAnalysis

Data

Specifi-cation

Algorithms:DeterministicRandomGenetic Multivalued

Simulator

Fault models:Stuck-at faultsPhysical defects

FaultSimulator

http://www.pld.ttu.ee/tt

PC-Based Toolkit – Turbo Tester


17

FreewareFreewareDownloadable via the WebDownloadable via the WebWindows, Linux, UNIX/SolarisWindows, Linux, UNIX/SolarisEDIF design interfaceEDIF design interfaceATPGs, BIST, simulators, test ATPGs, BIST, simulators, test

compactioncompactionProvides homogeneous environment Provides homogeneous environment

for research and trainingfor research and training

Turbo Tester: Basic Facts


18


Web

Tools

PC

Tools

Hardware

Tools


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BIST Analyzer: covered topics

Test Pattern Generators (PRPG):−LFSR−Modular LFSR −Cellular Automata−GLFSR−Weighted TPG−etc.

Combined Techniques (PRPG + Memory):

−Reseeding−Multiple polynomial BIST−Hybrid BIST−Bit-Flipping BIST−Column matching BIST−etc.

BISTControl

Unit

Circuit Under Test (CUT)

Test Pattern Generator (PRPG) ........

........

Output ResponseAnalyzer (MISR)

BIST

Memory

Typical BIST Architecture


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•Embedded generators (PRPG) and their properties

•PRPG optimization methodologies and algorithms

•Combined BIST solutions (PRPG+memory)

•Fault detection and diagnosis in BIST

BIST Analyzer: covered topics


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BIST Analyzer


23


Web

Tools

PC

Tools

Hardware

Tools


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Web Interface


25


Web

Tools

PC

Tools

Hardware

Tools


26

E-Learning software on DFT

http://www.pld.ttu.ee/applets


27

Essential supplement to the university lectures

Accessibility over InternetVisual content (“Living Pictures”)Comprehensive examplesBetter organization of teaching materialsBased on free educational softwareDistance learning & computer aided

teachingEasy to implement in other universitiesConstantly updated

Benefits of e-learning software


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Test Generation

ErrorDiagnosis

Built-InSelf-Test

Design forTestability

Test andDiagnostics

RTL Designand Test

BoundaryScan

Applet on Basics of Test &

Diagnostics

Applet on RTL Design and

Test

Applet on Boundary Scan

Standard

Schematic& DD Editor

TurboTester

Group of Applets on Control Part Decomposition

E-Learning SoftwareJava

AppletsTurboTester

Scenario 4Scenario 4Design forDesign forTestabilityTestability

Scenario 3Scenario 3Built-InBuilt-In

Self-TestSelf-Test

Scenario 2Scenario 2ErrorError

DiagnosisDiagnosis

Scenario 1Scenario 1Test Test

GenerationGeneration

Scenario 4Scenario 4Design forDesign forTestabilityTestability

Scenario 3Scenario 3Built-InBuilt-In

Self-TestSelf-Test

Scenario 2Scenario 2ErrorError

DiagnosisDiagnosis

Scenario 1Scenario 1Test Test

GenerationGeneration

SupportingMaterials

Learning Scenarios

Web based tools for classroom, home and exams

Tools for laboratory research


29

E-Learning Software

Logic level diagnostics System level test & DfT

Software for classroom, home, labs and exams:

http://www.pld.ttu.ee/applets

Boundary Scan


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• manual test pattern generation assisted by the applet• generation of pseudo-random test vectors by LFSR• fault simulation & study of fault table• combinational fault diagnosis using fault tables• sequential fault diagnosis by guided probing

Applet on basics of test


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• design of a data path and control path (microprogram) on RT level• investigation of tradeoffs between speed of the system & HW cost• RT-level simulation and validation• gate-level deterministic test generation and functional testing• fault simulation• logic and circular BIST, functional BIST, etc.• design for testability

Applet on RT-level design and test


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• Simulation of operation of TAP Controller Simulation of operation of TAP Controller • Illustration of work of BS registersIllustration of work of BS registers• Insertion and diagnosis of interconnection faultsInsertion and diagnosis of interconnection faults• Design/editing of BS structures using the BSDL languageDesign/editing of BS structures using the BSDL language• Design/description of the target board using several Design/description of the target board using several

chipschips

Applet on Boundary Scan


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An applet targetedAn applet targetedat binding all the at binding all the applets and the applets and the

Turbo TesterTurbo Tester

Supported Supported interface interface formats are:formats are:AGMAGMDWGDWGVHDLVHDLGIFGIFEDIF?EDIF?PostScript?PostScript?

Design forDesign forTestabilityTestability

Applet onApplet onBasics of Test Basics of Test & Diagnostics& Diagnostics

Applet onApplet onRTL DesignRTL Design

and Testand Test

Applet onApplet onBoundary ScanBoundary Scan

StandardStandard

SchematicSchematic& DD Editor& DD Editor

AGM, DWGAGM, DWG

AGM, GIFAGM, GIF

AGMAGM

AGM,AGM,GIFGIF

Main functions of the applet are:Main functions of the applet are:• gate-level schematic editorgate-level schematic editor• SSBDD editorSSBDD editor• schematic schematic ↔ SSBDD on-the-fly ↔ SSBDD on-the-fly converterconverter• different format reader/converterdifferent format reader/converter

Schematic and DD editor


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Design Specification

Design Implementation

Test Vector File

Test Vector File

Verification Results

XTimport Tool

ATPG

Circuit Schematic

Human Being

Diagnostic Vectors

Report File

Prediag Tool

Verification Tool

Circuit Netlist

Intermediate Diagnosis

Vecmanager ToolFinal

Diagnosis

Turbo Tester tools and formats

Other

Example of a lab work scenario


35

Conclusions

The main features of the platform:

•Research engine + training software

•Layered structure

•HW and SW components

•Remote access

•Distance learning and e-learning

•Computer-aided teaching

•Freeware


36

Conclusions


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Our Tools on the Web

The Turbo Tester home page

http://www.pld.ttu.ee/tt/

The Turbo Tester web-server page

http://www.pld.ttu.ee/webtt/

DefSim home page

http://www.defsim.com

Java applets home page

http://www.pld.ttu.ee/applets/

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