department microelectronics - lirmm.fr d... · few words about lirmm and the microelectronics...

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MICROELECTRONICSActivity Report 2013

Department

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Microelectronics Department – 2013 Activity Report

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Few Words about LIRMM and the Microelectronics Department • LIRMM • The Microelectronics Department

Staff members • Key numbers • List of members

Organization

Summary of 2013 Activities • TEST OF INTEGRATED CIRCUITS & SYSTEMS • ADAPTATION & RESILIENCE • EMERGING TECHNOLOGIES & MEMS • SECURITY • BIOMEDICAL INTEGRATED CIRCUITS & SYSTEMS

Some Key Features of the Microelectronics Department • Role and Involvement at the International and National Levels • International Academic Cooperation • National and European Research Projects • Industrial Relationships • ISyTest – A Joint Lab between LIRMM and NXP • Lafisi – A Joint Lab between LIRMM and POLITO • Technological Platforms

Sample Gallery

Table of Contents


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Few Words about LIRMM

Montpellier Laboratory for Informatics, Robotics and Microelectronics (LIRMM) is a research laboratory supervised by both Montpellier University (Université Montpellier 2) and the French National Center for Scientific Research (CNRS). With a staff of 405 people (including permanent and temporary employees, as well as Ph.D. and Post-Doc students), LIRMM is one of the most important academic laboratories in France. Its research activities position the LIRMM at the heart of Information and Communication Technologies (ICT) and sciences. The spectrum of research activities covered by LIRMM is very broad, and includes:

•Algorithms,databases,informationsystems,softwareengineering,artificialintelligence, networks,arithmetic,optimization,naturallanguageandbioinformatics,

•Designofmechanicalsystems,modeling,identification,controlandperception,

•Designandverificationofintegrated,mobileandcommunicatingsystems

The combination of these skills results in interdisciplinary academic or industrial research projects conducted at national and international levels.One of the LIRMM strengths is that each field of scientific expertise covers theory, tools, experiments and applications. The research works generally find applications in a great diversity of domains, such as biology, chemistry, telecommunications, health, environment, agronomy, etc., as well as in domains directly related to the own lab activities: informatics, electronics, and automation.LIRMM is a laboratory dedicated to «produce” knowledge (more than 300 international publications per year) and educate future researchers (Masters, PhDs, post-docs), and is involved in a strong economical “dynamic”: industrial partnerships, innovative start-ups, national and international scientific leadership, etc.

The laboratory is organized in three departments: Informatics,RoboticsandMicroelectronics.

www.lirmm.fr

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Few Words about LIRMM Few Words about the Microelectronics DepartmentThe Microelectronics department is specialized in the research of innovative solutions to model, design and test complex integrated circuits and systems. Such systems are characterized by a high complexity, elevated performances, a high heterogeneity, and a 2D or 3D integration into a single package.

The expertise of the Department covers the following strategic topics:

•Designfortestabilityandtestofintegratedcircuitsandsystemstodetectfaultydevices aftermanufacturingandimprovereliabilityduringthelifecycle. •Designhigh-performancesandrobustIntegratedCircuitsandSystems •Designandmethodsforemergingtechnologies(MRAM,3D…)andmicro-systemsbased on sensors and actuators; •Secureddesignfortheconfidentialityandintegrityofcommunications (inbankingtransactionsforexample); •Designofcircuitsforthehealthandmedicaldomains,neuro-stimulationsystems implantedthehumanbodyordevicesfortreatmentordiagnosis.

The research activities are multidisciplinary and require skills in computer science, mathematics, physics, life sciences, etc. This allows the research team to provide answers to the various and numerous scientific, societal and economical challenges of today and tomorrow Microelectronics.

To conduct these research activities, the Department relies on a hundred of persons, including full-time researchers, professors, PhD students, post-doc students, research engineers and technicians. Owing to its high-level scientific production, its academic collaborations, its implication in numerous national and international research programs, its participation to the creation of start-up companies, and its activities of transfer and valorization towards the industry sector, the Department is now recognized as an essential actor in the landscape of the French and international scientific research in Microelectronics.

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Staff: 93 PeopleDuring the year 2013, the Microelectronics Department was composed of 31 permanent researchers (from University Montpellier 2, CNRS and INRIA), , 3 Post-Doctoral students, 50 PhD students, 9 research engineers, technicians and administrative staff and a dozen of Master students.

Head of DepartmentPatrick Girard, CNRS Research Director

Deputy-HeadsofDepartmentSerge Bernard, CNRS ResearcherLaurent Latorre, Associate Professor at Montpellier University

Fullresearchersandprofessors(31)Florence Azais, CNRS ResearcherNadine Azemard-Crestani, CNRS ResearcherPascal Benoit, Associate Professor at University of MontpellierSerge Bernard, CNRS ResearcherYves Bertrand, Professor at University of MontpellierAlberto Bosio, Associate Professor at University of MontpellierGuy Cathebras, Professor at University of MontpellierMariane Comte, Associate Professor at University of MontpellierCopello Ost Luciano, Associate Professor at University of MontpellierDenis Deschacht, CNRS Research DirectorGiorgio Di Natale, CNRS ResearcherLuigi Dilillo, CNRS ResearcherSophie Dupuis, Associate Professor at University of MontpellierMarie-Lise Flottes, CNRS ResearcherGalliere Jean-Marc, Associate Professor at University of MontpellierGamatié Abdoulaye, CNRS ResearcherPatrick Girard, CNRS Research DirectorDavid Guiraud, INRIA Research DirectorLaurent Latorre, Associate Professor at University of MontpellierFrédérick Mailly, Associate Professor at University of MontpellierPhilippe Maurine, Associate Professor at University of MontpellierPascal Nouet, Professor at University of MontpellierSerge Pravossoudovitch, Professor at University of MontpellierMichel Renovell, CNRS Research DirectorMichel Robert, Professor at University of MontpellierBruno Rouzeyre, Professor at University of MontpellierGilles Sassatelli, CNRS Researcher DirectorFabien Soulier, Associate Professor at University of MontpellierAida Todri-Sanial, CNRS ResearcherLionel Torres, Professor at University of MontpellierArnaud Virazel, Associate Professor at University of Montpellier

Researchengineers,technicians and administrativestaff(9)Thierry Gil, CNRS research engineerRégis Lorival, CNRS research engineerPierre Amadou, research engineer at Montpellier University Laurent De Knyff, technician at Montpellier UniversityLudovic Guillaume-Sage, technicianOlivier Potin, research engineerFlorent Bruguier, research engineerJérémie Salles, research engineerVirginie Feche, secretary

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Staff: 93 People OrganizationResearch activities carried out by the Microelectronics Department are organized within two major research project teams:

•SysMIC : Design and Test of Microelectronic Systems •DEMAR :DeambulationandArtificialMovement(jointteambetweenLIRMMandINRIA, andjointteambetweenRoboticsandMicroelectronicsdepartments)

The overall objective of the SysMIC team is to propose innovative solutions to model, design and test today’s and tomorrow’s integrated circuits and systems. The overall challenges that are addressed are: complexity, performances, power consumption, heterogeneity (digital, analog, RF, memory, MEMS, FPGA, etc.), reliability and robustness (ageing, impact of environment), manufacturing related issues (variability, high defect density), communications (network-on-chip, wireless, sensor networks), and emerging technologies (physical phenomena to understand, to model and to integrate).

The overall objective of the DEMAR team is to propose complete Functional Electrical Stimulation (FES) systems based on the patients’ demand discussed with the medical staff. The overall challenges that are addressed are: selectivity for stimulation and recording, power management, complexity and heterogeneity, physiological constraints, and safety for the patient (dependable systems). The main research area is the Development of Micro-Circuits for Neuro-Prothesis.

SysMIC

Informatics Microélectronics Robotics

DEMAR

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Research of the Microelectronics Department is organized into 5 main topics:

•TestofIntegratedCircuitsandSystems •Adaptive&Resilience •EmergingTechnologies&MEMS •Security •BiomedicalIntegratedCircuits

Test of Integrated Circuits and Systems to develop Design-for-Test techniques for complex systems (to ease test application and increase test efficiency), to develop fault models, methods, algorithms and tools to test manufacturing defects and deal with reliability issues. The topic includes:

•NewStrategiesforAlternateTestingofAnalogandRFCircuits •AnalogNetworkofConvertersTestTechnique •Low-CostTestingofAnalog/RFICsusingstandarddigitalAutomatedTestEquipment(ATE) •TestofLowPowerSRAMMemories •VariabilityAwareSRAMTest •MemoryTestthroughCUBE-satellite(MTCUBE) •PathDelayTestinthePresenceofPowerSupplyNoise,GroundBounceandCrosstalk •PowerModelingandEstimationTechniques •AFunctionalPowerEvaluationFlowforDefiningTestPowerLimitsduringAt-SpeedDelayTesting •ImprovingDefectLocalizationAccuracybymeansofEffect-CauseIntra-CellDiagnosis at Transistor Level •Testinfrastructurefor3DstackedICs •Pre-bondThroughSiliconViaTest

Adaptive & Resilience to explore and design systems with adaptive or resilient capabilities to preserve performances (power consumption, robust to process variations, resilient external disturbance and defect…). The topic includes:

•Self-AdaptiveCircuitforNearFieldCommunication(NFC) •DataMiningTechniquesforSystemMonitoring •ProcessandAgingCharacterizationinFPGACircuits •Built-in-SelfRepairArchitectureforAnalog-to-DigitalConverters •EffectsofRadiationsonElectronics •RobustnessImprovementofDigitalCircuitsusingFaultTolerantArchitectures

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Emerging Technologies & MEMS. The objective is to develop solutions to exploit the new capabilities of emerging technologies and to develop innovative solutions to promote the integration of low-cost MEMS devices. The topic includes:

•PowerManagementinFD-SOICircuits •Magnetic-RAM-baseddesign •TestandReliabilityofMagneticRandomAccessMemories •SSTAframeworkforprocessvariabilitymonitoring •ReliabilityandPerformanceofThrough-Silicon-Viasin3DICs •PhysicalDesignandReliabilityIssuesofThree-DimensionalICs •Power&Thermal-AwareWorkloadAssignmentof3DMPSoCs •DefectModelinginNanometricCMOSTechnologies

Security to improve the hardware security during processing, storage and intra-chip communication. The topic includes:

•BulkBuilt-inCurrentSensors(BBICS)forDetectionofTransientsFaults •Faultattacks:ModelingandSimulation •Scan-basedTestofSecureDevices •ProtectedTestAccessMethodforSecureDevices •HardwareSecurityandTrust •TrustworthyManufacturingandUtilizationofSecureDevices

Biomedical Integrated Circuits. The objective is to develop innovative portable or implanted solutions to offer palliative solutions for sensory-motor disabilities and sensor to detect and help for treatment of pathology. The topics include:

•NewPassiveandNon-InvasiveSensorforGlaucomaDiagnosis •Self-AdaptiveSystemforintraocularpressuremeasurement •Abiomechanicalemulatorofeye •ValidationofNewMultipolarElectrodeArchitectureforENGRecording •Multichannel,programmableandimplantableacquisitionsystemforbioelectricsignals •ImplantforFunctionalElectricalStimulation •Implantedmedicaldevicesself-adaptivetofibrosis

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Summary of 2013 activities

TESTOFINTEGRATEDCIRCUITS&SYSTEMS

ADAPTATION&RESILIENCE

EMERGINGTECHNOLOGIES&MEMS

SECURITY

BIOMEDICALINTEGRATEDCIRCUITS&SYSTEMS

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TEST OF INTEGRATED CIRCUITS & SYSTEMS

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ADAPTATION & RESILIENCE

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EMERGING TECHNOLOGIES & MEMS

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SECURITY

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BIOMEDICAL INTEGRATED CIRCUITS & SYSTEMS

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New Strategies for Alternate Testing of Analog and RF Circuits H. AYARI, S. LARGUECH, F. AZAIS, S. BERNARD, M. COMTE, V. KERZERHO, M. RENOVELL

Contact : [email protected]

Project/Partners: ENIAC JU ELESIS Topic: Analog /RF Testing Collaboration with NXP Semiconductors

The conventional approach for testing analog and RF circuits is specification-‐based testing, which involves the verification of all specifications listed in the data sheet. This approach offers good test quality but at the price of very high testing costs. Indeed, measurements of analog/RF parameters are usually complex and require expensive and sophisticated test instruments, making the cost of ATE equipment prohibitive. In addition, measurements of analog/RF parameters usually require dedicated test setup, resulting in extremely long test times due to a sequential measurement approach.

Figure 1. Classical synopsis of the indirect test strategy

A promising solution to reduce analog/RF testing costs is to develop indirect or alternate test methods. The basic idea is that the analog or RF circuit specifications are not directly measured but, instead deduced from a set of “easy-‐to-‐measure” parameters that are correlated with the circuit specifications. More precisely, the idea is to learn during a training phase the mapping between indirect measurements and circuit specifications. This dependency can then be modeled through regression functions. During the testing phase, only the indirect low-‐cost measurements are performed and specifications are predicted using the regression model built in the

learning phase. Figure 1 summarizes the synopsis of the indirect test strategy.

Despite the substantial test cost reduction offered by this strategy and a number of promising results reported in the literature, its deployment in industry is today limited, mainly because of a lack of confidence in test efficiency. Our objective is to develop new implementations that preserve the low-‐cost features of the indirect test strategy by that offer improved confidence in test efficiency. In particular we have proposed a new implementation that exploits model redundancy. The idea is to build different regression models for each specification during the training phase, and then to verify prediction consistency between the different models during the production testing phase. In case of divergent predictions, the devices are removed from the alternate test tier and directed to a second tier where further testing may apply. Another aspect of our research work deals with the selection of the indirect measurements and we have performed a comparative analysis of different selection strategies.

Figure 2. New implementation of the indirect test strategy

References: [1] H. Ayari, F. Azaïs, S. Bernard, M. Comte, V. Kerzerho, O. Potin, M. Renovell, “Implementing model redundancy in predictive

alternate test to improve test confidence”, ETS’13: European Test Symp., p.1 (poster), Mai 2013. [2] S. Larguech, F. Azais, S. Bernard, M. Comte, V. Kerzerho, M. Renovell, “Development of Robust Indirect Testing Method for

Analog or RF Integratred Circuits”, Colloque National GDR SOC/SIP, Juin 2013. [3] S. Larguech, F. Azais, S. Bernard, M. Comte, V. Kerzerho, M. Renovell, “A Comparative Analysis of Indirect Measurement

Selection Strategies for Analog/RF Alternate Testing,” TVHSACW13: IEEE Int’l Workshop on Test and Validation of High-‐Speed Analog Circuits, September 2013

[4] H. Ayari, F. Azaïs, S. Bernard, M. Comte, V. Kerzerho, M. Renovell, “Enhancing Confidence in Indirect Analog/RF Testing against the Lack of Correlation between Regular Parameters and Indirect Measurements,” Accepted at Microlelectronics Journal (MEJO), doi: 10.1016/j.mejo.2013.12.006.

Process throughbuilt regression

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Low-‐Cost Testing of Analog/RF ICs using standard digital Automated Test Equipment (ATE) F. AZAIS, S. DAVID-‐GRIGNOT, L. LATORRE Contact: [email protected]

Project/Partners: ENIAC JU ELESIS Topic: Analog /RF Testing Collaboration with NXP Semiconductors

The production test of analog and RF devices is one of the major challenges for the development of modern microelectronic products. The test of these devices traditionally involves dedicated instruments to perform the acquisition or generation of analog signals. Compared to traditional digital resources, the cost of these instruments is extremely high.

Moreover analog/RF devices are often tested twice, at the wafer-‐level and again at the package-‐level. Implementing a quality test at wafer-‐level is extremely difficult due to probing issues, while the inability to perform multi-‐site testing due to a small count of available test resources decreases the throughput. Our objective is to propose a test solution applicable with low-‐cost test equipment that provides wafer-‐level test coverage and permits multi-‐site testing for analog/RF signals. The fundamental idea is to complement a standard digital ATE with signal processing techniques so that it permits the analysis of analog/RF signals. More precisely, the idea is to use the comparator of a standard digital ATE channel to sample the analog/RF signal. This comparator acts as a 1-‐bit digitizer and converts the amplitude and/or frequency information of the analog signal in timing information into the resulting bit stream. Post-‐processing algorithms can then be developed to retrieve this information.

Figure 1 illustrates the principle of data capture using a digital ATE channel. The Device Under Test (DUT) output is connected to the input of a digital channel that includes a programmable comparator, a latch, and a memory. The channel comparator together with the latch are used as a 1-‐bit digitizer operating at the ATE clock frequency and the resulting bit stream is stored in the ATE memory; data are then processed offline to retrieve the analog/RF signal characteristics.

This approach has been investigated to reduce the cost of industrial phase noise test for analog/RF signals [1]. This kind of measurement is traditionally done by sampling the analog/RF signal with expensive digitizers located in the industrial tester; FFT is then performed on these digitized samples to get the signal spectrum and phase noise is computed by subtracting the carrier level to the noise level.

The proposed strategy permits to realize phase noise measurement using only digital test resources. For this, a dedicated post-‐processing algorithm has been developed that permits to compute the analog signal phase noise characteristic from the properties of the captured serial bitstream. The method has been patented [2] and validated both in simulation and experimentally with the setup shown in figure 2.

Figure 1: Analog/RF data capture with digital ATE.

Figure 2: Experimental setup for phase noise measurement.

References: [1] David-‐Grignot S., Azais F., Latorre L., Lefevre F., "Analog Measurements based on Digital Test Equipment for

Low-‐Cost Testing of Analog/RF Circuits", IEEE European Test Symp. (ETS’13), p.1 (poster), Avignon, France. [2] David-‐Grignot S., Azais F., Latorre L., Lefevre F., "Method and apparatus for measuring phase noise",

Patent Application No. 81582852EP01, filed October 17, 2013

CPost-‐

ProcessingAlgorithm

Analog/RF Signal ATE

Memory

Analog/RF Signal Characteristics

Regular Digital Pin Electronics

DUT/ATE SynchronisationATE Clock

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RF Source(Agilent N9310A)

AWG(Agilent 33120A)

White Noise

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Yokogawa Oscilloscope

DedicatedAlgorithm

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Signal GenerationConventional PN Measurement

Low-‐Cost Measurement with digital ATE

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Test of Low Power SRAM Memories L. ZORDAN, A. BOSIO, L. DILILLO, P. GIRARD, S. PRAVOSSOUDOVITCH, A. TODRI, A. VIRAZEL Contact : [email protected]

Project/Partners: Intel Mobile Communications Topic: Test, Low-‐Power, SRAMs

With the growing demand of hand-‐held devices, power dissipation has emerged as a major design concern. Simultaneously, technology scaling is shrinking device features as well as lowering the supply and threshold voltages, which cause a significant increase of leakage currents. Within System-‐On-‐Chips (SOCs), embedded memories are the densest components, hence arising as the main contributor to the overall SOC static power consumption.

The main goal of this work is to produce new generic and efficient test solutions for low power SRAMs. This is a new topic that offers research perspectives to a wide range of industrial applications. We started by studying the failure mechanisms that occur in nanometric technologies used for this type of memories, as well as their impact on current test solutions.

The SRAM used in this work embeds power switch (PS) blocks connected to the core-‐cell array and the peripheral circuitry. Such PS blocks are implemented through a network of PMOS transistors structured in N segments. Core-‐cell array PS segments have four transistors, whereas peripheral circuitry PS segments have two transistors. Signals connected to the gate of each PMOS in a segment are generated by the PM control logic, as shown in Figure 1, according to the power mode selected through primary inputs ("SLEEP" and "PWRON"). Signals Ctrl_CC0 to Ctrl_CC1 control the transistors of the core-‐cell array PS segments, while Ctrl_PC0 and Ctrl_PC1 control the transistors of the peripheral circuitry PS segments.

Figure 1. Power Mode control logic

Three power modes can be distinguished: (1) active mode, (2) deep-‐sleep mode, and (3) power-‐off mode. In active (ACT) mode, all PMOS transistors are activated. In this case, the whole memory is connected to the main supply rail VDD, which enables the SRAM to perform operations. In both deep-‐sleep (DS) and power-‐off (PO) modes, all PMOS transistors are deactivated, thus the SRAM is no longer connected to the main supply rail. In DS mode, a voltage regulation system generates a fixed voltage level Vreg, lower than the nominal VDD, to be provided to the core-‐cell array. The lower voltage Vreg still ensures data retention. In PO mode, the power supply voltage of the whole memory is shut off such that core-‐cells are no longer able to retain data.

We characterized the SRAM behavior in presence of resistive-‐open defects affecting the PM control logic primary outputs, as shown in Figure 1. We observed that all injected defects induce a delay on the activation of the PMOS they affect during wake-‐up (WU) phase from DS or PO mode to ACT mode. Def1 to Def3 and Def5 cause rush-‐in currents during WU phase, whereas Def6 leads to malfunctioning of operations executed after WU.

References:

[2] Zordan Y., Bosio A., Dilillo L., Girard P., Todri A., Virazel A., Badereddine N., “On the Reuse of Read and Write Assist Circuits to Improve Test Efficiency in Low-‐Power SRAMs”, IEEE International Test conference, DOI: 10.1109/TEST.2013.6651927, 2013

[3] Zordan Y., Bosio A., Dilillo L., Girard P., Todri A., Virazel A., Badereddine N., “A Built-‐in Scheme for Testing and Repairing Voltage Regulators of Low-‐Power SRAMs”, IEEE VLSI Test symposium, DOI: http://dx.doi.org/10.1109/VTS.2013.6548894 , 2013

[4] Zordan Y., Bosio A., Dilillo L., Girard P., Todri A., Virazel A., Badereddine N., “Test Solution for Data Retention Faults in Low-‐Power SRAMs”, Design, Automation & Test in Europe, DOI: http://dx.doi.org/10.7873/DATE.2013.099 , 2013

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Variability Aware SRAM Test E. I. VATAJELU, L. DILILLO, A. BOSIO, P. GIRARD, S. PRAVOSSOUDOVITCH A. TODRI, A. VIRAZEL

Contact: [email protected]

Project/Partners: INTEL Mobile Communications Topic: SRAM test, process variability

With continuous device scaling, increased variability, increased leakage power and decreased robustness and reliability have become major challenges in CMOS design. In general, an SRAM memory cell design struggles to achieve a balance between cell area, robustness, speed and yield. Reducing the cell area contributes to the improvement of speed and power consumption but leads to a deceased robustness due to process variability. This variability is related to the manufacturing process and causes the dimensions and characteristics of the circuit after fabrication to be different from those it was designed for. Apart from process variability issues the memory cell is also prone to manufacturing defects which mainly consist of impurity deposition like dust particles. These types of defects at the layout level of the chip often behave like resistive defects (resistive‐opens or bridges) at the electrical level. Such defects can cause faults in the SRAM operation. Another increasingly important issue when dealing with scaled technologies is the premature aging of the circuit. The aging affects both defect size and variability level. The presence of a resistive‐open defect on an interconnect induce a local increment of the heat (hot spot) due to Joule effect. In such condition the phenomenon of electromigration takes place and the resistive open defect grows. Moreover, aging effects like Hot Carrier Injection (HCI), radiation induced damage and Bias Temperature Instability (BTI) can cause reliability degradation. Our objective is to analyze the behavior of SRAM memories under the influence of the above mentioned phenomena [1] and to devise suitable test strategies to maximize defect coverage. An optimum

test sequence is sought‐after, which assures 100% fault coverage with high defect coverage. The stress conditions during test need also be carefully chosen to maximize defect coverage without over testing the memory [2] and evaluate the impact on Soft Error Rate [3]. To that end, we have statistically analyzed the resistive‐open defects in SRAM core‐cell taking into account the effects of random process variability the core‐cells and the IO circuitry. Results shown that under variability, the minimum defect value detected with maximum probability is over 2X larger than the minimum value detected in nominal conditions (Fig. 1). By testing under various stress conditions, we have shown that design for test techniques should aim to boost the variability effect while the SRAM memory is in test mode.

References: [1] Elena I. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine, “SRAM Read Access Failures Due to Concurrent Variability in the Core Cells and Sense Amplifier,” IEEE Design & Technology of Integrated Systems (DTIS), 2013. [2] Elena I. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine, "Analyzing Resistive‐Open Defects in SRAM Core Cell under the Effect of Process Variability," IEEE European Test Symposium (ETS), 2013.

[3] E. I. Vatajelu,G.Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, Serge Pravossoudovitch, A. Todri, A. Virazel, F. Wrobel, F. Saigné, "On the Correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM Cell", IEEE Defect and Fault Tolerance (DFT) Symposium, NY, USA, October, 2013.

Figure 1. SRAM core‐cell failure probability under random process variability assuming resistive open

defects at different locations.

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Memory Test through CUBE-satellite (MTCUBE) V. GUPTA, G. TSILIGIANNIS, L. DILILLO, A. BOSIO, P. GIRARD, S. PRAVOSSOUDOVITCH, A. TODRI, A. VIRAZEL


Project/Partners: 3D-PLUS, ESA, CSU Montpellier, IES Topic: Memories, Space environment, Cube-satellite

Since the middle of the 1970s, the effect of the natural radiation environment on the embedded electronic components in satellite is known. Two main failure effects have been observed. The first one is related to the dose effects, corresponding to a slow degradation of the devices electrical parameters. The second one is related to the single events effects (SEE), due to energetic particles, which are able to induce a parasitic current in a device. This current may generate soft errors (SEs). SEs do not produce any permanent effect in the devices, but they can be source of major malfunction in the device itself and in the system in which it is placed.

In this project, we mainly focus on SEs and partially on dose effects. In particular, we concentrate our attention on the effects of space radiation on memories. In electronic systems, memories are the most diffuse devices and, at same time, they are among the components that are the most prone to fault due to their high density, in terms of layout, and because they are designed at the limit of technology. The most common and studied memory type in literature is SRAM, and recently we analyzed two SRAMs with different technology nodes 90nm and 65nm. We made radiation experiments on these SRAMs with heavy ions at RADEF (FINLAN) that included static and dynamic mode tests. During static (retention) mode test, no operations are applied to the memory, while during the dynamic mode the memory is constantly accessed for read/write operations. During the read/write actions many cells endure an electric stress, with a consequent noise margin reduction, that makes them more sensible to particle induced swap. In the case of static mode test, a known pattern is written in the cell array and, after a predefined time of exposure, the SRAM is read back to check for errors.

Nowadays, new types of memory are under development. Magnetic memories MRAMs,

Ferroelectric memories (FeRAMs), Phase-change memories (PRAMs) and Oxide Resistive memories (OxRAMs) are few examples of the many new and promising non-volatile memory technologies. MRAM and FeRAM technologies are particularly interesting since they already present an operation speed comparable to SRAMs. We intend to explore the viability of these two types of devices together with a FLASH (NAND based) memory in space applications, and thus we will run experiments similar to those made with SRAMs.

Moreover, we are currently generating an actual space experiment by mean of a test card placed in a cube-satellite, see Fig1. Cubesats are nano-satellites that suggest today an interesting alternative to large orbital systems. Produced at lower cost, they may be launched by small-sized rockets operated by specialized companies or as a secondary payload on Vega or Soyuz. The collected data will be compared to experiments realized at ground level in order to improve the efficiency of the prediction tool developed during the project, as well as to validate both the physical models and the new test methods for each memory type and technology. Guidelines for electronic devices intended to space applications will be also provided.

References: [1] G. Tsiligiannis, L. Dilillo, V. Gupta, A. Bosio, P. Girard, A. Todri, A. Virazel, H. Puchner, A. Bosser, A. Javanainen, A. Virtanen, F. Wrobel, L. Dusseau and F.Saigné “Efficient Dynamic Test Methods for COTS SRAMs Under Heavy Ion Irradiation”, submitted at IEEE Nuclear and Space Radiation Effects Conferencee, Paris, FRANCE, 2014

Fig 1. Views of the cubesat

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Path Delay Test in the Presence of Power Supply Noise, Ground Bounce and Crosstalk A. ASOKAN, A. TODRI-‐SANIAL, A. BOSIO, L. DILILLO, P. GIRARD, S. PRAVOSSOUDOVITCH, A. VIRAZEL


Project: ELESIS, ENIAC Program Topic: Delay Testing, Speed Binning

As technology scales down, the effects of power supply noise and ground bounce are becoming significantly important. In the existing literature, it has been shown that excessive power supply noise can affect the path delay, while ground bounce is either neglected or assumed similar to power supply noise. Our work performs a detailed study of combined and uncorrelated power supply noise and ground bounce and their impact on the path delay. Our analyses show that different combination of power supply noise and ground bounce can lead to either delay speed-‐up or slow-‐down.

Our objective is to generate test patterns such that the combined effects of power supply noise and ground bounce are considered on circuit delay analysis. The impact of noise on delay is highly depended on the applied input patterns. Our research seeks to provide mathematical models to represent the circuit based on the physical extracted data after the circuit is placed & routed with power/ground grids. We propose close-‐form mathematical models to capture the impact of input patterns on path delay in the presence of power supply noise and ground bounce. We use a simulated annealing (SA) based approach to find patterns that maximize the critical path delay. In contrast to previous works which initially aim to find patterns for maximum supply noise and then compute delay, our method targets directly to find the worst case delay which might not necessarily occur under worst case power supply noise due to the speed-‐up/slow-‐down phenomena. Our method generates patterns that sensitize the path and also cause such power supply noise and ground bounce that leads to the maximum path delay.

Figure 1 shows a sample two buffer circuit and its power and ground networks. As the gates are placed in different locations on the chip, the amount of power supply noise and ground bounce that they experience can vary significantly among them. Such variations on the power and ground networks lead to variations on the path delay, which can be either a speed-‐up or slow-‐down effect.

Gate 1

Gate 2

VDD

VDD

VDD VDD

GND GND

GND

GND

Path under investigation

(a)

Lpkg

LgridRgrid

Grid segments

RpkgPackage

Ground network

Gate 1

Gate 2Rpwr1 Lpwr1

Rgnd1 Lgnd1Rgnd2 Lgnd2

C4 bumps

Power network

Rpwr2 Lpwr2

(b)

Figure 1. (a) An illustration of gate placement on chip and (b) representative model for two-‐stage buffer circuit used for path delay analysis in the presence of power supply noise and ground bounce.

References:

[1] A. Todri, A. Bosio, L. Dilillo, P. Girard, A. Virazel, “Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation,” IEEE Transactions on VLSI Systems (VLSI), vol. 21, no.5, pp.958-‐970, 2013. [2] A. Asokan, A. Todri-‐Sanial, A. Bosio, L. Dilillo, P. Girard, A. Virazel, “Path Delay Test in the Presence of Multi-‐Aggressor Crosstalk, Power Supply Noise and Ground Bounce,” submission at IEEE DDECS.

20


Pre-‐bond Through Silicon Via Test G. DI NATALE, M.L. FLOTTES, Y. FKIH, B. ROUZEYRE, H. ZIMOUCHE


Project/Partners: MASTER-‐3D/CEA-‐LETI Topic: 3D-‐SIC, Test

It is acknowledged that 3D ICs production requires tiers to be tested before stacking in order to provide know-‐good-‐dies (KGDs) to the stacking process and thus guarantee the stacking yield. When tiers are interconnected by means of Through Silicon Via (TSVs), these vertical interconnections built in tiers must be tested as well since their eventual manufacturing defects would result in faulty 3D ICs after stacking. The test approaches currently under development rely either on contact/contactless communication with TSVs from an ATE, or on BIST schemes. Contact-‐based probing of TSVs arrays of some µm at array pitches of some tens of µm without damaging TSVs tips and thinned wafers is still a challenge. Contactless probing techniques on the other hand require the implementation of extra logic and possible antennas leading to considerable area overhead. Limitations of contact/contactless probing solutions have led to consider Built-‐In Self-‐Test (BIST) approaches as alternative solutions. TSVs are then used as capacitive loads and the deviation of their expected equivalent RC parameters are detected by indirect measures, namely the delays required for charging or discharging the nets connected to their front ends, the only ends accessible before wafer thinning and bonding. Electrical modelling of such TSVs using R, L, and C elements has been presented in recent years in the literature. L and R components are generally neglected in the pre-‐bond phase and a simplified model based on the predominant parasitic capacitance C between the TSV and the substrate is considered for fault-‐free TSVs. The figure depicts electrical modelling of potential TSV manufacturing defects (oxide pin-‐holes, voids, and break). We currently explore two BIST approaches for TSV pre-‐bond testing. Both are designed to be robust to PVT variations.

In the first approach [1], ring oscillators are created from TSVs drivers and receivers and extra inverters. Their oscillation period is captured thanks to extra binary counters that use the oscillating signal as clock. As TSV manufacturing defects change the propagation delay of the ring oscillator nets, TSV parameter deviations are detected through the deviation of the expected ring’s oscillation periods. We propose to use one ring oscillator per TSV but one counter for frequency measurement on all TSVs in order to limit area overhead. TSVs are thus tested iteratively. PVT impact is limited by computing relative frequency variations instead of using direct measurement. The BIST scheme provides comparison of oscillation frequencies and accept/reject a TSV Under Test (TUT) according to a user given threshold on the expected relative frequency variation. In the second approach [2-‐3], the BIST circuitry is used to charge/discharge and sense the TSV top-‐end voltage. Thanks to the integration of one BIST circuitry per TSV, this low area approach is able to test all TSVs at the same time and can detect small capacitance deviations under PVT variations. In addition, the proposed test scheme detects micro-‐void defects and, to some extent, pin-‐hole defects. The two approaches must be further explored in order to define detection threshold, implementation costs and diagnostic facilities for each of them.

(SiO2)

CBreak

TSV TSV

M1 M1

Silicon Substrate

(Si)(Cu) (Cu)

(1-‐d)C

dC

R Void

CTSV(Cu)

Rpin-‐hole

M1

Break Void pin-‐hole

(SiO2)

C

TSV

M1

Silicon Substrate

(Si)

(Cu)

(a) (b)

TSV Electrical Fault Models

References: [1] Y Fkih, P Vivet B Rouzeyre, G Di Natale, M-L Flottes, “3D IC BIST for pre-bond test of TSVs using Ring Oscillators”, 11th IEEE

International NEWCAS Conference, June 16-19, 2013, Paris. [2] TSVs Pre-Bond Testing: a test scheme for capturing BIST responses, Giorgio Di Natale, Marie-lise Flottes, Bruno Rouzeyre, Hakim

Zimouche, Fourth IEEE Int’ Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 3D-TEST, 12-13 Sept. 2013 [3] A BIST Method for TSVs Pre-Bond Test, Giorgio Di Natale, Marie-lise Flottes, Bruno Rouzeyre, Hakim Zimouche, IEEE In’t Design &

Test Symposium 2013, 16-18 décembre 2013, Maroc.

21


A Functional Power Evaluation Flow for Defining Test Power Limits during At-‐Speed Delay Testing M. VALKA, A. BOSIO, L. DILILLO, P. GIRARD, S. PRAVOSSOUDOVITCH, A. TODRI A. VIRAZEL Contact : [email protected]

Project/Partners: Politecnico di Torino Topic: Power-‐Aware Test

Nowadays, electronic products present various issues that become more important with CMOS technology scaling. High operation speed and high frequency are mandatory requests. On the other hand, power consumption is one of the most significant constraints due to large diffusion of portable devices. These needs influence not only the design of devices, but also the choice of appropriate test schemes that have to deal with production yield, test quality and test cost. Testing for performance, required to catch timing or delay faults, is therefore mandatory, and it is often implemented through at-‐speed scan testing for logic circuits. At-‐speed scan testing consists of using nominal system clock period between launch and capture for each delay test pattern, while a longer clock period is normally used for scan shifting. In order to test for transition delay faults, two different schemes are used in practice during at-‐speed scan testing: Launch-‐off-‐Shift (LOS) and Launch-‐off-‐Capture (LOC).

Although at-‐speed scan testing is mandatory for high-‐quality delay fault testing, its applicability is severely challenged by test-‐induced yield loss, which may occur when a good chip is declared as faulty during at-‐speed scan testing. Both schemes (LOS and LOC) may suffer from this problem, whose the major cause is Power Supply Noise (PSN), i.e., IR-‐drop and Ldi/dt events, caused by excessive switching activity (leading to excessive power consumption) during the launch-‐to-‐capture cycle of delay testing schemes. In order to deal with this problem, dedicated techniques mainly based on test pattern modification or power-‐aware Design-‐for-‐Testability (DfT) have been proposed.

Despite the fact that reduction of test power is mandatory to minimize the risk of yield loss, some experimental results have proven that too much test power reduction might lead to test escape and reliability problems because of the under-‐stress of

the circuit during test. So, in order to avoid any yield loss and test escape due to power issues during test, test power has to map the power consumed during functional mode. To this purpose, the knowledge of functional power for a given CUT is required and may be used as a reference for defining the power consumption (upper and lower) limits during power-‐aware delay test pattern generation for LOS or LOC.

In this work, we propose a framework (depicted in Figure 1) where functional patterns are generated to maximize the switching activity of a given design, so that they can be further used to determine the test power limits during at-‐speed delay testing.

Figure 1 Proposed Framework

An evolutionary optimization tool (i.e. automatic Test Pattern generator) starts by generating assembly programs, thus forming a population of programs; then, a logic simulator evaluates every test program to further provide to the evolutionary optimizer a feedback value representing the test program goodness. This value, also known as fitness value, is computed by measuring the switching activity of the gate-‐level design (i.e. Power Analysis Engine (PAE)). The evolutionary optimizer improves test programs by mimicking the Darwinian concepts of evolution. The higher the fitness value, the better the test program is.

References:

[1] P. Bernardi, M. De Carvalho, E. Sanchez, M. Sonza Reorda, A. Bosio, L. Dilillo, M. Valka, P. Girard, “Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption”, Journal of Low Power Electronics, Volume 9, Number 2, pp. 253-‐263, August 2013.

52

Automa'c)TP)generator)

Power1hungry)Program)

Logic)Simulator)

PAE)

Energy)informa'on)

Gate1level)descrip'on)

Gate)ac'vity)

Feedback)value)

22


23


Test infrastructure for 3D stacked ICs G. DI NATALE, M.L. FLOTTES, Y. FKIH, B. ROUZEYRE

Contact :[email protected]

Project/Partners: CEA/LETI Topic: 3D test 3-‐Dimensional (3D) integration is an emerging technology where multiple layers of planar 2D devices (tiers) are stacked and interconnected using so called Through Silicon Vias (TSVs). Besides footprint advantages, the potential benefits of 3D integration can include higher device speed, smaller overall cost, lower power consumption, larger bandwidth, and it will allows heterogeneous designs. Unfortunately, die stacking also presents new challenges. Among them, test and testability must be redefined for 3D.

In particular, the test strategy must be specifically defined to cope with this fabrication process. When test steps are expected at different level of the stacking process (pre-‐bond, mid-‐bond, and post-‐bond testing), they should be enabled by the same test infrastructure for cost reduction. Moreover, introduction of TSVs for inter-‐die interconnection requires specific test steps for these elements. Test wrappers must also be defined for isolation and test access to the different dies.

In 2011, we started a new research axis, in collaboration with CEA Leti, continuing within the framework of the european project MASTER3D for the definition of a complete 3D Dft. Assuming that the 3D circuit can be accessed only from the bottom (bottom layer), additional TSVs are needed to drive test data from the bottom die to upper dies, and boundary scan cells are used to form a die level wrapper either based on IEEE 1500 or IEEE 1149.1 standard.

We studied different test standards including: IEEE 1149.1, IEEE 1500, IEEE 1149.7, and P1687 showing advantages and drawbacks of each one for 3D circuits. We also proposed some extensions for coping with mid-‐bond, pre-‐bond and final test relying on the usage of switch with die detectors

We are currently developing such infrastructures with related test-‐scheduling strategies, in particular based on P1687 (see Fig.1). This architecture relies on the usage of die detectors allowing pre-‐, mid-‐ and post-‐ bond testing. One of the advantages of P1687 is the retargeting of test patterns.

Fig1. P1687 based test architecture

Fig2. Chiplet DFT bloc diagram

We are also currently looking at the application of such architecture for 2.5 D circuits using active interposers:

Fig3. Extension to 2.5 D circuits

Our future work will deal with the test scheduling taking into account not only test bandwidth but also power and thermal issues which are specific to 3D circuits. The scheduling method will also consider the manufacturing step in which the circuit is being tested (partial or final stack).

References:

Y. Fkih, P.l Vivet, B. Rouzeyre, M.-‐L. Flottes , G. Di Natale , J. Schloeffel, “3D Design For Test Architectures Based on IEEE P1687 ”, 3DTEST’13 workshop, September 2013 Y. Fkih, P.l Vivet, B. Rouzeyre, M.-‐L. Flottes , G. Di Natale "A JTAG based 3D DfT architecture using automatic die detection", "Prime" Conference 2013, Villach, Austria, June 24th-‐27th, 2013

24


25


Self-‐Adaptive Circuit for Near Field Communication (NFC) F. AZAIS, S. BERNARD, M. COMTE, M. DIENG, V. KERZERHO, M. RENOVELL


Project/Partners: NXP Semiconductors Topic: RFID, NFC, self-‐adaptive systems As a result of the evolution of different applications like access control, ticketing, payment and e-‐documents, the deployment of Near Field Communication (NFC) devices has been growing rapidly for several years. In particular, a variety of mobile phones equipped with NFC technology to enable such applications have emerged.

Due to the wide range of devices and applications, a predefinition of antenna geometry and corresponding electrical parameters is difficult. Each device shows different antenna physical characteristics; moreover each application for a given device shows different needs in terms of achievable distance… Therefore, each integrator associates the NFC IC with its own antenna for each device. Current NFC transmission modules require the antenna circuitry to be manually matched with the integrated circuit (IC) (see EMC filter and matching blocks on fig. 1). This step is crucial to maximize the emitted magnetic field and, therefore, to maximize the read range and the quality of the transmitted signal. According to the ISO 14443 standard, only well-‐matched reader devices fulfill the standard requirements and thus enable interoperability. Manual matching of the antenna characteristics is a rather lengthy and complicated procedure. Moreover, the matching can be done only once at the device design level, regardless of the communication mode (reader, card or peer-‐to-‐peer) and regardless of the secondary antenna influence on the primary antenna characteristics. Therefore, the design-‐level matching is not optimal as far as the application and environment will detune the antenna in operation.

Figure 1: NFC system: reader (left) / card (right) coupling

To summarize, NFC technology is associated with an antenna that can have different physical characteristics (shape, size…) and that is influenced

by environment and application. Our goal is to develop a technique to allow the NFC IC to adapt itself to these different antennas and environments in order to optimize its performances in terms of communication and power consumption.

The first step in our investigation is to study the physical phenomena associated with these antennas. The goal is to predict the variations of the antenna current and magnetic field by a mathematical model. The major difficulty of this exercise is to identify the effects associated with the coupling phenomenon (mutual inductance) between different antennas when the NFC system communicates with another device. When the primary and secondary are coupled, that modifies the antenna characteristics based on the coupling coefficient, which depends on the shapes, sizes, relative position, etc. Before defining a complete model of the NFC system, we developed an accurate model of the first main part of this system: the reader antenna. Figure 2 shows the comparison between our model and existing model (simulation FEM is the reference) regarding the antenna resistance.

Figure 2: Antenna resistance model

The second step of this study concerns the means to monitor and control the antenna performances via a self-‐calibration. The NFC circuitry should be able to adapt itself to its own antenna characteristics, which may differ from one application to another.

References: [1] Dieng M., Comte M., Bernard S., Kerzérho V., Azaïs F., Renovell M., Kervaon T., Pugliesi-‐Conti P.H., “Accurate

and Efficient Analytical Electrical Model of Antenna for NFC Applications”, NEWCAS’13: 11th IEEE International New Circuits and Systems Conference, 2013.


26


Data Mining Techniques for System Monitoring P. BENOIT, M. NAJEM, G. SASSATELLI, L. TORRES


Topic: Power Monitoring, Data Mining

The ever-increasing integration densities make it possible to configure multi-core systems composed of hundreds of blocks that may influence overall consumption differently. Observing total consumption is not sufficient to accurately assess internal circuit activity to be able to deploy effective adaptation strategies. One way to address this challenge is to monitor the application workload being executed, estimate the resulting dissipation and adjust the core performance on the fly. The use of power monitors is one way to obtain instant information about core consumption.

Figure 1: Example of run-time power estimation using PMF.

To achieve accurate low-cost on-chip dynamic power monitoring, we need to model instantaneous power. For this purpose, the idea is first to observe the behavior of the circuit and the power consumed.

After testbench execution, a database of events and power is created. The database is then used to define event counter positions and to produce the power models. The corresponding CAD flow is exemplified in Figure 1. In this work, the appropriate signals are selected using Data Mining techniques from the WEKA open-source tool. Our approach is based on a generic method that is able to produce a power model for any block-based circuit. We evaluated and validated our approach on a SoC RTL model implemented on FPGAs. A power model and monitors are automatically generated to achieve the best tradeoff between accuracy and overhead.

In [1], a new monitoring technique that tracks power consumption at fine-grain level using a minimum of monitored events was also investigated. To avoid the time-dependency inherent to this kind of features, we used a dynamic modeling approach based on Hidden Markov Models. Power variations are smoothed when using static monitors because of long interval readings, whereas our dynamic approach is designed to detect critical variations. The dynamic model has many proven advantages over a static approach. RAM and MAC components were used as test-cases, and the results obtained are very promising: average and maximum energy are estimated with an error around 5%. For a memory controller and a MAC unit, only one probe is used leading to a very limited area overhead.

References:

[1] Imen Mansouri, Pascal Benoit, Lionel Torres, Fabien Clermidy: Fine-Grain Dynamic Energy Tracking for System on Chip. IEEE Trans. on Circuits and Systems 60-II(6): 356-360 (2013)

Method for Dynamic Power Monitoring on FPGAs

Authors Name/s per 1st Affiliation (Author) line 1 (of Affil iation): dept. name of organization

line 2: name of organization, acronyms acceptable Line 3: City, Country

line 4: e-mail: [email protected]

Authors Name/s per 2nd Affiliation (Author) line 1 (of Affil iation): dept. name of organization

line 2: name of organization, acronyms acceptable line 3: City, Country

line 4: e-mail: [email protected]

Abstract—The ever-increasing integration densities make it possible to configure multi-core systems composed of hundreds of blocks on existing FPGAs that may influence overall consumption differently. Observing total consumption is not sufficient to accurately assess internal circuit activity to be able to deploy effective adaptation strategies. In this case distributed monitoring techniques are required. This paper presents a CAD flow for high-level dynamic power estimation on FPGAs. The method is based on the monitoring of toggling activity for relevant signals by introducing event counters. The appropriate signals are selected using the Greedy Stepwise filter. Our approach is based on a generic method that is able to produce a power model for any block-based circuit. We evaluated our contribution on a SoC RTL model implemented on Spartan3, Virtex5, and Spartan6 FPGAs. A power model and monitors are automatically generated to achieve the best tradeoff between accuracy and overhead.

Keywords: FPGA; System-on-chip; Power Modeling; System Monitoring;

I. INTRODUCTION Energy efficiency is one of the main challenges facing

hardware and software designers. Different techniques ranging from silicon to application abstraction level must be applied to efficiently reduce power consumption. The power consumed is due to switching (dynamic power) and leakage (static power), and therefore depends on many different parameters, including power supply voltage, circuit frequency, load equivalent capacitance, activity, but also temperature and transistor characteristics including threshold voltage. Many techniques can be used to reduce the dynamic power, e.g. pipeline or asynchronous design styles, but also multi power-supply designs, voltage-frequency islands (VFI), Dynamic Voltage Frequency Scaling (DVFS), etc. FPGA circuits provide both software flexibility and hardware efficiency, but there is still room for further improvement of the energy efficiency of these technologies.

Today, it is possible to configure MPSoCs with multiple heterogeneous processing elements in a single FPGA device. To achieve the greatest run-time energy savings, the system needs to be monitored in a distributed manner. We propose a complete generic method for monitoring dynamic power. We estimate power consumption by monitoring events on some strategic nets at the RTL-level. For this purpose, event counters (EC) are added to the design to monitor net events. In this way, the instantaneous power can periodically be

estimated by the system itself (either by a dedicated SW service or a simple finite state machine).

In this paper, we present our method by applying it to a System on Chip (SoC) RTL design. Once the events counters position is generated and after collecting its values, the processor can estimate the dynamic power consumed by the entire circuit. Consequently, several power-aware techniques can be used (task mapping, scheduling, frequency/voltage scaling) in order to reduce the dynamic power.

Our contributions are the following: A method to estimate the instantaneous dynamic

power at high-level using Xpower; A generic flow to extract events from signals at the

RTL-level, which can be applied to any block-based circuit;

A statistical technique for power modeling and selection of the nets;

An evaluation of the proposed method, which shows an average error of 4% for power estimation compared to simulations, with 7% overhead.

The remainder of this paper is organized as follows. In Section II, the limitations of most relevant power estimation techniques are discussed to highlight the need for this work. Section III is devoted to power modeling method and tools. Section IV describes the experiments and in the Section V we present our conclusion with suggestions for future research.

Figure 1: Example of run-time power estimation using PMF.

Power Modeling Flow

Statistical Analysis

Power Events

General Purpose Processor

$IINTERRUPT

CTRL TIMER$D

Bus

UARTRAM

System On Chip

General Purpose Processor

$I

INTERRUPTCTRL

TIMER$D

Bus

UART RAM

C0

C1 C2

C3P = f(Ev)

Run-time Power Estimation

Co-processor

Co-processor

Power Monitors(Number/Position)

Power ModelP= f(Ev)

27


Process and Aging Characterization in FPGA Circuits P. BENOIT, F. BRUGUIER, L. TORRES Contact: [email protected]

Project/Partners: UFRGS, KIT Topic: Aging, Variability, FPGA

Variability has become a major issue in the semiconductor market due to its impact on manufacturing yields, performance and power consumption. A fine management of these physical variations is a key to success for more reliable technologies. Besides, aging is a natural process that any integrated circuit suffers during its lifetime. The effects of aging can be seen as the degradation of a circuit in terms of its performance and also an increase in the leakage current.

Figure 1: Floorplan of the test-‐design in a Spartan-‐6 FPGA.

To measure the process variability and the impact of aging on FPGA, we have developed an innovative characterization method based ElectroMagnetic emanations Analysis (EMA). In this method, the RO (Fig. 1) is successively placed in each CLB of the FPGA. Each RO oscillates at a specific frequency, which is directly related to Process, Voltage and Temperature (P,V,T). Voltage is controlled using a high precision DC power supply. The temperature is fixed using a thermal chamber. The variations between two different positions of the sensor are due to process variations. During measurement, a near-‐field EM probe, placed over the chip, captures the EM emissions generated by the RO inside the chip. The signal from the sensor is amplified by a low noise amplifier and digitalized using an oscilloscope. An FFT

is realized to obtain the frequency of each RO and then chip cartography is built. The whole measurement system is illustrated in Fig. 2.

In order to analyze the effect of aging in FPGAs, it is possible to perform aging acceleration. This one is achieved by exposing the FPGA to an elevated temperature and core voltage. For this purpose, the core is supplied by a voltage above its nominal value using an external power supply. The FPGA is heated to using a thermal chamber, while a stress-‐design is in operation (to maintain a switching activity at given locations). The FPGA is configured with as array of Ring Oscillators (RO) as depicted in Fig. 1. The RO is manually placed and routed, ensuring an identical physical implementation of all ROs. Generally, the aging period refers to 10 days, including 7 days of effective aging and 3 days of recovery, required to clear the effects of reversible aging. To measure the impact of aging on FPGA, the circuit is characterized before and after aging using the ElectroMagnetic method.

Figure 2: EMA Analysis.

The method was successfully applied to various technologies, such as SRAM FPGAs, but also Flash Based FPGAs [1].

Reference:

[1] Jimmy Tarrillo, Jorge Tonfat, Fernanda Lima Kastensmidt, Ricardo Reis, Florent Bruguier, Morgan Bourree, Pascal Benoit, Lionel Torres: Using electromagnetic emanations for variability characterization in Flash-‐based FPGAs. ISVLSI 2013: 109-‐114

28


Built-‐in-‐Self Repair Architecture for Analog-‐to-‐Digital Converters S. BERNARD, F. AZAIS, M. COMTE, O. POTIN, V. KERZERHO, M. RENOVELL


Topic: ADC, design, correction

The semiconductor industry tends to constantly increase the performances of developed systems with an ever shorter time-‐to-‐market. In this context, the conventional strategy for mixed-‐signal component design, which is based only on analog design effort, will no longer be suitable.

In order to combine ADC performance with short time-‐to-‐design, an alternative solution is the correction of Integral Non-‐Linearity (INL). As presented in Figure 1, the developed solution consists in using a post-‐processing correction table, also called Look-‐Up-‐Table (LUT).

Figure 1: LUT-‐based correction of ADC

The efficiency of this technique is obviously based on the quality of the table used to correct the non-‐linearity. The table is usually computed using measurements of the Integral Non-‐Linearity (INL) of the ADC. INL is a conventional test parameter generally measured using a histogram-‐based method. This method has demonstrated its effectiveness for a long time but its main drawback is the huge amount of sampling required to compute the INL. As ADC resolution increases, test time also increases. With the rapid increase of ADC resolution, it is going to be difficult to implement this method. This is why we propose alternative techniques to avoid the need for a histogram-‐based method to measure INL.

Based on our test vehicle, a 12-‐bit Folding-‐and-‐interpolating ADC, we have successfully validated a static correction table.

The study of the robustness [1] of the proposed technique has shown that the domain of validity is very large and covers the ADC application field. The robustness validation of the approach consisting in varying several functional (sampling frequency, converting frequency) and environmental (temperature) parameters has demonstrated that the correction is optimized when the operating conditions are the same as the conditions settled for the computation of the correction table.

Based on this observation, we proposed a solution for “on-‐line” self-‐calibration of ADC with the on-‐chip capability of computing and filling the LUT (cf. Figure 2).

Figure 2: LUT-‐based self-‐correction of ADC

By completing the LUT ‘in situ’, i.e. directly in the application, the corrected codes are computed according to the input signal dynamic, aging and environment conditions. Indeed the calibration is performed with an integrated adaptive signal generator providing an input signal tuned according to the application. The whole correction scheme is proved to be effective through extensive simulations.

Current developments focus on the minimization of the embedded resources used to compute the correction table. Software and hardware solutions are investigated in order to reduce the table’s size as much as the requirements on the performances of the embedded instrument

References: [1] V. Kerzérho, S. Bernard, F. Azaïs, M. Comte, O. Potin, C. Shan, G. Bontorin, M. Renovell, “A novel

implementation of the histogram-‐based technique for measurement of INL of LUT-‐based correction of ADC”, Microelectronics Journal, Volume 44, Issue 9, September, pp. 840–843, 2013.

29


Effects of Radiations on Electronics G. TSILIGIANNIS, L. DILILLO, A. BOSIO, P. GIRARD, S. PRAVOSSOUDOVITCH, A. TODRI, A. VIRAZEL


Project/Partners: ANR Hamlet /CNES, IES, ATMEL Topic: Radiation and electronics

Radiation effects are a major concern not only for electronic systems in radiation harsh environments such as the space but for common electronics at sea level as well. Impinging particles may alter the bits stored in the memory array (Single Event Upset –SEU, or Multiple Bit Upsets –MBUs) or generate temporary voltage pulses in logic circuitry (Single Event Transients, SETs).

Our work was focused on the study of particle-induced effects on several types of memories such as SRAMs, MRAMs and FRAMs at experimental and simulation level.

A 90nm 32Mbit and a 65nm 16Mbit SRAMs were tested with different particles radiation and with different stimuli, in order to define which algorithm and test conditions are the most efficient [1]. The experiments were performed at the TSL (Sweden) and ISIS (UK). Figure 1 gives a picture of the experimental setup at ISIS facility.

During the similar irradiation campains, we tested a 4Mbit MRAM. For the purposes of the experiments, we ran the tests while the memory was in both the static and dynamic mode. At the end of the experiments, no upsets have been observed. This can be explained with the architectural characteristics of the Magnetoresistive Tunnel Junction (MTJ), which is the storage element of the tested MRAM. The MTJ does not have any electrical characteristics, and thus it cannot be affected by the transient currents induced by neutrons [2].

Besides the characterization of electric devices, we also demonstrate that it is possible to create SRAM based monitors and that they are efficient for monitoring the intensity of particle fluence at mixed environments such as the ones of H4IRRAD and LHC (CERN, CH). In particular, we analyzed the device’s

response to different positions on the mixed-field environment in terms of cross section and its evolution over time taking into account the received total ionization dose. The results show that these monitors can be used as quantitative monitors for the sensing of radiation levels under mixed environments, see Fig. 2 [3].

Figure 1: one SRAM and two MRAMs being irradiated at the TSL facilities in Uppsala, Sweden.

Figure 2: Fluence evolution over time of three monitors at H4IRRAD (CERN).

References: [1] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Todri-‐Sanial, A. Virazel, J. Mekki, M.

Brugger, F. Wrobel, F. Saigné, “SEU Monitoring at a Mixed-‐Field Radiation Environment at CERN”, European Conference on Radiation and its Effects on Components and Systems, Oxford, UK, septembre 2013..

[2] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel,S. S. McClure, A. D. Touboul, F. Wrobel, F. Saigné “Testing a Commercial MRAM under Neutron and Alpha Radiation in Dynamic Mode”, IEEE Transaction on Nuclear Science, DOI 10.1109/TNS.2013.2239311, 2013

[3] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel, J. Mekki, M. Brugger, F. Wrobel, F. Saigné, “An SRAM Based Monitor for Mixed-‐Field Radiation Environments”, in press, IEEE Transaction on Nuclear Science, 2014

30


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33


Power Management in FD-SOI Circuits Y. AKGUL, P. BENOIT, L. TORRES, D. PUSCHINI, S. LESECQ


Project/Partners: CEA LETI Topic: FPSOI, Low Power, Local Control

Embedded systems need ever increasing computational performances. Since they have limited energy resources, power consumption has to be minimized. Dynamic Voltage and Frequency Scaling (DVFS) techniques combined with Body Biasing techniques decrease the power consumption of a chip by providing just enough computational performance to the chip so as to finish the task at its deadline (Figure 1). A Power Mode (PM) is defined with the clock frequency F applied to the chip and the power P consumed by the chip. Executing tasks with the 2 neighbor frequencies of the target frequency should minimize the power consumption. Unfortunately, this choice is not always optimal since the set of available PMs may not fulfill the convexity property anymore when 3 actuators are considered. In this work, a method is proposed to tackle this issue. PMs are selected to form a discretely convex subset.

Figure 1: Schematic of an island with 3 actuators. d is the deadline and Nc is the number of clock cycles.

Different situations may appear when executing a task on a given Processing Element (PE):

• If the target frequency Ftarget is available on the PE and if the PM corresponding to Ftarget belongs to the discretely convex subset S, the PM is applied directly in order to execute the task;

• If the target frequency Ftarget is available on the PE and if the PM corresponding to Ftarget does not belong to the discretely convex subset S, the 2 PMs in the discretely convex subset S surrounding Ftarget are applied in order to execute the task;

• If the target frequency Ftarget is not available on the PE, the 2 PMs that surround Ftarget and which are in the discretely convex subset S are applied.

To be energy efficient, the task has to be performed with PMs belonging to a convex set. The method proposed in [1] overtakes this problem by selecting the PMs that form a discretely convex subset as depicted in Figure 2. Our method takes into account the behavior induced by FDSOI technologies as tuning parameters have effects on the convexity of the power/speed curve (e.g. Vbb). Obtained results on different circuits have proved the power management methodology. They attest that executing tasks with PMs in the discretely convex subset permits to save up to 30% of power consumption.

Figure 2: Set of PMs in the (F, P ) plane. Red crosses correspond to PMs in the discretely convex subset.

Reference:

[1] Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Pascal Benoit, Lionel Torres: Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing. PATMOS 2013: 199-206


34

Microelectronics Department – 2012 Activity ReportMicroelectronics Department – 2013 Activity Report

35


Test and Reliability of Magnetic Random Access Memories J. AZEVEDO, A. VIRAZEL, A. BOSIO, L. DILILLO, P.GIRARD, S. PRAVOSSOUDOVITCH, A. TODRI


Project/Partners: ANR EMYR / Crocus, CEA Topic: MRAM, Memory testing

Magnetic Random Access Memory (MRAM) is an emerging technology with high data processing speed, low power consumption and high integration density compared with Flash memories. Moreover, these memories are non-‐volatile with fair processing speed and reasonable power consumption when compared to Static RAMs (SRAMs). Another important feature of MRAM is that the fabrication process is completely compatible to CMOS technology.

MRAMs are Spintronic devices that store data in Magnetic Tunnel Junctions (MTJs). A basic MTJ device is usually composed of two ferromagnetic (FM) layers separated by an insulating layer. One of the FM layers is pinned and acts as a reference layer. The other one is free and can be switched between, at least, two stable states. These states are parallel or anti-‐parallel with respect to the reference layer. When it is in the parallel state, the MTJ offers the minimum resistance (Rmin) while the maximum resistance (Rmax) is obtained when anti-‐parallel. The difference between Rmin and Rmax, quantified by the Tunnel Magneto Resistance (TMR), is high large to be sensed during the read operation.

“0”

“1”

Antiparallel, Rmax

Parallel, Rmin

FM

FMFM

FM

Figure 1: Basic MTJ device schematics in two stable states

A read operation consists in determining the MTJ’s magnetization state and can be performed by voltage or current sensing across the MTJ stack. A write operation can be performed using magnetic fields or spin polarized current and depends on MRAM technologies: FIMS (Field Induced Magnetic

Switching), Toggle Switching, TAS (Thermally Assisted Switching) and CIMS (Current Induced Magnetic Switching).

Thermally Assisted Switching is an alternative switching method for MRAMs proposed by Spintec and industrialized by Crocus Technology. TAS approach offers several advantages. The selectivity problem is reduced since only heated MTJs are able to switch and all other MTJs remain in their stable state as they remain below their blocking temperature.

This work is funded by the French national research agency under the framework of the ANR-‐10-‐SEGI-‐007 EMYR (Enhancement of MRAM Memory Yield and Reliability) project. In this project, our goal was to analyzing the impact of defects (resistive, bridging and capacitive) on the TAS-‐MRAM functioning. Electrical simulations have been performed using the MTJ model developed by Spintec that allows any read/write operation sequences.

Figure 2: Capacitive defect injection

References:

[1] J. Azevedo, A. Virazel, Y. Cheng, A. Bosio, L. Dilillo, P. Girard, A. Todri adn J. Alvarez-‐Herault, “Performance Characterization of TAS-‐MRAM Architectures in Presence of Capacitive Defects”, International Conference on Advances in Systems Testing and Validation Lifecycle, 2013.

[2] J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, J. Alvarez-‐Herault and K. McKay, “A Complete Resistive-‐Open Defect Analysis for Thermally Assisted Switching MRAMs", IEEE Transaction on Very Large scale Integration Systems, 2013.

36


SSTA framework for process variability monitoring N. AZEMARD, R.KHAYRALLA Contact : [email protected]

Project/Partners: I3M, CEA Grenoble Topic: Models and methods for circuit design With the « More Moore » and low power trends, optimizing or only well predicting the final performances of digital circuits become more and more difficult. Indeed, variability and hardness to model accurately transistor behavior impede the dimension scaling benefits. Current design methodologies generally use guard margins to prevent from the incertitude generated by these limits and to guarantee functional yield. But as we go in the nanometer era, the use of margin is not efficient anymore, because of an increasing over-‐design, limiting optimizations and decreasing both parametric and functional yield.

In order to increase the robustness to uncertainty during the design levels and to have better performance analysis, we propose a SSTA Framework Based on Moments Propagation (Figure1). We introduce a new statistical PDF propagation approach built on two concepts in probability theory: conditional mean and conditional variance. Our objective is to develop a simple and practical timing approach considering effect of structure correlations, input slope and output load variations. Such objective causes the introduction of new way to do cells timing characterization: log-‐normal distribution based model as input signal and inverters as charge.

We have implemented the specific methodology called SSTA (Statistical Static Timing Analysis). The SSTA engine allows computing cell-‐to-‐cell and path-‐to-‐path delay correlations. Numerical results show that path delay means and standard deviations computed by this engine have relative errors less than 5% and 10%. We could verify that this SSTA flow allows performing statistical analysis on timing performances and accurately observing process variation effects on delays.

We attempt to tackle the problem never been mentioned: estimate of structure correlations, which comes from the fact that output signal of one cell is input signal of the next stage.

More, face to the success of the tree first editions of the specific workshop on CMOS variability (VARI 2010,2011 and 2012) organized in 2010 in Montpellier, in 2011 in Grenoble and in 2012 in Sophia-‐Antipolis, we have decided to continue this workshop. The fourth edition has been held in Germany, to Karlsruhe on September 4-‐9, 2013 It has been organized by the Karlsruhe Institute of Technology (KIT) in collocation with PATMOS 2013, a reference workshop on Power and timing modeling, optimization and simulation. The LIRMM has been co-‐chairman of this VARI edition. The VARI meeting answers to the need to have an European event on variability, where industry and academia meet to discuss. The VARI objective has to provide a forum to discuss and investigate the CMOS variability problems in methodologies and tools for the design of upcoming generations of integrated circuits and systems. The technical program has focused on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization of variability.

References: [1] Z.WU, P.MAURINE, N.AZEMARD, G.DUCHARME, "Delay correlation-‐aware SSTA based on conditional moments", Microelectronics Journal, Vol.43, Issue 4, April 2012, p.263-‐276.

[2] N.AZEMARD, Z.WU, P.MAURINE, G.DUCHARME, "Statistical Cells Timing Metrics Characterization", FTFC'2012, June 6-‐8, 2012, Paris, France.

[3] N.AZEMARD, Z. WU, P. MAURINE, G. DUCHARME," Statistical Timing Characterization”, S0C 2012, October 11-‐12, 2012,Tampere, Finland.

[4] N.AZEMARD, "VARI Workshop Overview", DCIS’2012, XXVII Design of Circuits and Integrated Systems Conference, November 28-‐30, 2012, Avignon, France.

SSTA flow

37


1

Reliability and Performance of Through-Silicon-Vias in 3D ICsC. METZLER, A. TODRI-SANIAL, A. BOSIO, L. DILILLO, P. GIRARD, A. VIRAZEL


Project: MASTER-3D, CATRENE Program Topic: TSV failure mechanisms, fault modeling

Three-dimensional integration is a fast emerging technology that enables multilayered circuit implementation. Through-Silicon-Vias (TSVs) provide short and fast interconnects between tiers and depending on the fabrication orientation they can connect: (i) face-to-face, (ii) face-to-back, (iii) back-to-face, and (iv) back-to-back between any two adjacent tiers. Manufacturing advancements have led to fine pitch TSVs and thinned silicon for die stacking. Depending on the 3D processing technology, multi-tier stacking can be performed on chip to chip, chip to wafer or wafer to wafer. Recent advancement on TSV development have led to production of TSVs in different ranges of dimensions.

Despite the manufacturing advancements, 3D integration is still immature. The multitude of manufacturing steps pre and post bond can introduce a lot of undesirable effects that can alter TSV performance or even cause such defects that can lead to TSV failure. Defects are physical aberrations due to partial or porous metal lines. Depending on the process sequence and 3D integration schemes (via last, first or middle) TSV fabrication process includes the following steps: TSV drilling, deposition of isolation and seed layer, filling (electroplating metal), wafer thinning, wafer planarization and bumping. TSVs are usually made of copper, and the process of electroplating the metal is likely to cause resistive opens where TSV channel is not completely filled or partly broken. This is also portrayed in Fig. 1a and Fig. 1b. A broken TSV can cause discontinuity on a signal line that may affect the chip latency or even completely interrupt the electrical connection between two nodes and causing a strong open. However, open defects can also still connect the

signal line’s two end points, but only weakly or referred to as a weak open. Weak open introduces a higher than expected but finite resistance on the TSVs, which lets the circuit to function but with degraded performance in the form of signal delay. Thus, it is imperative to ensure robustness and resiliency of TSVs for reliable operation of 3D ICs. In addition, it is important to detect chips with resistive open defects early on before shipping to maintain product reliability. In this work, we examine failure mechanisms on TSVs by employing models as shown in Fig. 1c and propose appropriate fault models. Additionally, dedicated test techniques are investigated for capturing open defect TSVs.

References: [1] C. Metzler, A. Todri, A. Bosio, L. Dilillo, P. Girard, A. Virazel, “Resistive-Open Defect Analysis for Through-Silicon-Vias,” IEEE European Test Symposium, pp. 183-183, 2012. [2] C. Metzler, A. Todri, A. Bosio, P. Girard, A. Virazel, "Resistive-Open Defect Analysis for Through-Silicon-Vias," IEEE Conference on Design of Circuits and Integrated Systems (DCIS), 2012. [3] C. Metzler, A. Todri-Sanial, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Vivet, M. Belleville, "Computing Detection Probability of Delay Defects in Signal Line TSVs," accepted at IEEE European Test Symposium (ETS), 2013.

(c)

Figure 1. Illustration of resistive open defects in TSVs, (a) open defect, (b) resistive defect, and (c) TSV model.

Insulator

InsulatorLayer(SiO2)

Si Substrate

Break (Open Defect)

NMOS

PolySi

n+ n+

Metal Layer

TSV

Insulator

InsulatorLayer(SiO2)

Si Substrate

Impurity (Resistive Defect)

NMOS

PolySi

n+ n+

Metal Layer

TSV

(a) (b)

38


Physical Design and Reliability Issues of Three-‐Dimensional ICs A. TODRI-‐SANIAL, A. BOSIO, L. DILILLO, P. GIRARD, A. VIRAZEL


Partners: Univ. of Massachusetts, USA Topic: Power and Thermal Integrity of 3D ICs

Recent advancements in semiconductor processing technologies have enabled three dimensional circuit design and implementation of heterogeneous systems in the same platform, i.e. Flash, DRAM, SRAM placed atop logic devices and microprocessor cores. 3D integration results in shorter interconnect lengths, greater device density and enhanced performance. However, the densely packed vertical tiers introduce significant power and thermal integrity challenges compared to 2D integration.

Due to the increased power density and greater thermal resistance to heat sink, thermal integrity is a crucial challenge for reliable 3D integration. High temperatures can degrade the reliability and performance of interconnects and devices. Power/ground network resistivity is a function of temperature, thus at nodes with high temperature, voltage droop values become even worse. Furthermore, the large amount of current on power and ground networks flowing for significant amount of time can ultimately elevate the temperature and cause Joule heating phenomena and electromigration. Thus, voltage droop and temperature are interdependent and should be considered simultaneously during analysis. Fig.1a shows an illustration of a 3D system where voltage droop tends to increase for tiers further away from package (controlled-‐collapse chip-‐connection (C4) bumps) and close to heat sink while temperature increases for tiers further away from heat sink and near to package pins.

The objective of this work is to investigate power and thermal integrity issues in 3D ICs by performing a

comprehensive electro-‐thermal analysis. Additionally, fast and accurate RLC models are developed for studying TSVs, power/ground networks, package pins and switching circuits. Our electro-‐thermal analysis provides detailed voltage droop and thermal map for each tier as shown in Fig 1.b. Based on the analysis results, optimization of power/ground and clock networks can be performed while ensuring power and thermal integrity.

Heat Sink

Isolation layer

Tier 4

Tier 1

Tier 2

Tier 3

Top metal layers

Bottom metal layers

(a)

(b)

Figure 1. (a) Illustration of a four tier 3D IC, and (b) tier based voltage/temperature distributions, voltage droop and thermal maps generated from electro-‐thermal analysis tool.

References:

[1] A. Todri, S. Kundu, P. Girard, A. Bosio, L. Dilillo, A. Virazel, “A Study of Tapered 3D TSVs for Power and Thermal Integrity,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 2, pp. 306-‐319, 2013.

[2] A. Todri-‐Sanial, S. Kundu, P. Girard, A. Bosio, L. Dilillo, A. Virazel, “Globally Constrained Locally Optimized 3-‐D Power Delivery Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2013.2283800, 2013.

39


Power & Thermal-‐Aware Workload Assignment of 3D MPSoCsY. CHENG, A. TODRI-‐SANIAL, A. BOSIO, L. DILILLO, P. GIRARD, A. VIRAZEL


Partner: CEA-‐LETI Topic: power and thermal analysis of tasks in 3D MPSoCs

Due to aggressive technology scaling, billions of transistors can be fabricated on a single die. However, interconnects on chip cannot scale very well with transistors, and it is difficult to increase frequency further when processor operating frequency approaches several Gigahertz. Moreover, power consumption also becomes a bottleneck of processor design. As a result, single processor cannot afford to increase performance and functionality requirements. Multiprocessor System-‐on-‐Chip (MPSoCs), which integrates IP module, FPGA, hardware accelerator and processors together, provides a cost effective way to tackle this problem. At the same time, three dimensional integration technology emerges to reduce interconnect delay and power consumption. Combining both technologies can provide more functionalities and higher performance within given power budget. In addition, 3D MPSoCs can integrate modules fabricated by disparate processes effectively. Therefore, 3D MPSoCs draw much attention from both academia and industrial fields.

3D MPSoCs, however, also bring several new challenges. Among others, power supply noise (PSN) is a big concern threatening signal integrity, performance and reliability, especially for shared power delivery networks. Compared with 2D counterparts, 3D MPSoCs power supply current becomes much larger, and causes more severe IR drop. Moreover, due to power/ground TSV parasitics, power supply noise manifests large variations among different tiers, and can propagate from one tier to other ones through TSVs [4]. These distinguish characteristics require further investigations to suppress PSN magnitudes for 3D MPSoCs. On the other hand, thermal dissipation has become a prominent issue for 3D MPSoCs. Stacking structure

prevents effective heat removal of bottom tiers from the heat sink. High temperature can degrade system performance, cause thermal runaway, and increase package cost.

Previous works are either on purely circuit level or high system level, and cannot fill the gap between different design levels and capture the close relations among power supply noise, thermal gradient and workload characteristics. In this work, we integrate circuit-‐level PSN estimation, system level thermal evaluation and workload assignment together effectively.

(a)

(b)

Fig 1. (a) Workload list to be assigned to general-‐purpose cores, and (b) different assignment schemes that can impact power and thermal integrity of 3D ICs.

References: [1] Y. Cheng, A. Todri-‐Sanial, A. Bosio, L. Dilillo, P. Girard, A. Virazel, “Power Supply Noise-‐Aware Workload Assignment for Homogeneous 3D MPSoCs with Thermal Consideration,” accepted at IEEE/ACM ASP-‐DAC, 2014. [2] Y. Cheng, A. Todri-‐Sanial, A. Bosio, L. Dilillo, P. Girard, A. Virazel, “A Novel Method to Mitigate TSV Electromigration for 3D ICs,” accepted at IEEE ISVLSI 2013.

40


41


3-‐axis Thermal Convective Accelerometer H.B. NGUYEN, F. MAILLY, L. LATORRE, P. NOUET Contact: [email protected]

Topic: Integrated Sensors

Thermal convective accelerometers are based on fluid motion induced by free convection in a closed cavity. The sensing principle is well known and many examples of single or dual-‐axis CMOS-‐compatible MEMS implementation can be found in the literature for measuring in-‐plane accelerations. All these sensors are based on a differential temperature measurement between two thermal detectors placed symmetrically on both sides of a suspended micro-‐heater. However, due to their conventional planar geometry, a third sensing axis for the measurement of out-‐of-‐plane accelerations seems difficult to add on a single CMOS die and with a simple post-‐process. Since it is not easy to add out of plane temperature detectors to implement a differential out-‐of-‐plane sensing axis, we have proposed to measure the common mode temperature of existing x and y detectors. This principle is illustrated in figure 1 which is a vertical cross section of the cavity. Note that, without acceleration, the initial shape of hot bubble, represented by one isotherm in light grey, is not symmetric across the (xOy) sensing plane due to the asymmetry of top and bottom cavity parts. Therefore, a positive acceleration stretches the hot bubble in the z direction, the resulting hot bubble cross section is smaller in the sensing plane and a temperature decrease is measured. On the other side, a negative acceleration tends to flatten the hot bubble leading to a temperature rise in the sensing plane. This working principle was confirmed by a FEM study using ANSYS [1]. Based on this study, a prototype was designed. CMOS 0.35μm technology from AutriaMicroSystems (AMS) was chosen for monolithic fabrication of both sensing cell and conditioning electronics (figure 2). Bulk micromachining is then achieved with a TMAH post-‐process to release suspended parts. The silicon cavity area is 1mm2 and the micro-‐heater is embedded in the central suspended square plate. Thermal detectors are placed on medians of the square cavity. For x and y axis, 4 resistive sensors are used for each direction and then, full Wheatstone bridge configurations can

be used for these two sensing directions. For z-‐axis detection, only two sensing resistances are used and two reference resistances are added on silicon substrate, since the signal is not differential.

Figure 1: Representation of the sensor working principle for the detection of out-‐plane acceleration

Figure 2: Picture of the etched CMOS die

References:

[1] H.B. Nguyen, F. Mailly, L. Latorre, P. Nouet, “FEM study of a 3-‐axis thermal accelerometer based on free convection in a microcavity”, Modeling & Simulation of Microsystems (MSM 2012), Microtech Conference & Expo 2012, Santa Clara, CA, June 18th –21th, 2012.

[2] H.B. Nguyen, F. Mailly, L. Latorre, P. Nouet, Design of a Monolithic 3-‐axis Thermal Convective Accelerometer, Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS (DTIP2013), p. 235-‐238, Barcelona, Spain, April 16th – 18th, 2013.

42

Microelectronics Department – 2013 Activity Report 1

Low-Cost Electrical Test & Calibration of MEMS Accelerometers

F. AZAIS, F. MAILLY, P. NOUET Contact: [email protected]

Project/Partners: ENIS, University of Sfax, Tunisia Topic: MEMS Testing MEMS are multi-domain systems that find an increasing use in a number of applications. In particular, their deployment for high-volume and low-cost applications is expected to keep on growing. In this context, there is of great interest to reduce test and calibrations costs, which represent an important part of the total manufacturing costs. Indeed due to their multi-domain nature, they usually require the application of physical test stimuli to verify their specifications, necessitating specific and sophisticated test equipment much more expensive than a standard ATE. Moreover, MEMS devices are generally quite sensitive to manufacturing process variations and calibration is often required to achieve satisfactory yield.

An interesting approach is to develop electrical-only test and calibration techniques. A number of solutions have been proposed in the last decade for various types of MEMS such as accelerometers, magnetic field sensors, or pressure sensors. This project focuses on test and calibration of MEMS accelerometers’ sensitivity, which is the most challenging specification to measure without applying a calibrated acceleration. MEMS capacitive accelerometers were addressed in previous work; present activities concern MEMS convective accelerometers (see fig.1).

Figure 1: MEMS convective accelerometer.

First, a behavioral model that permits to handle faults related to manufacturing process has been developed, taking into account not only the classical CMOS process scattering but also imperfections related to the etching process. This model can be used in system-level simulation to evaluate different test and calibration strategies. Then, several electrical-only solutions have been investigated that exploit the correlation between device sensitivity and relative deviation of Wheatstone bridge equivalent impedance for different biasing conditions. In particular, an original scheme based on the adjustment of the power dissipated in the heating element has been developed. The test and calibration procedure relies only on impedance measurements, which can be performed with standard electrical test equipment. The procedure involves a preliminary step to reject devices affected by strong defects, and then an iterative search on the appropriated heater power level. A simple on-chip circuitry based on a pulse modulated generator is integrated within the circuit to permit the adjustment of the power level through digital programming (see fig.2).

Figure 2: Circuit implementation for electrical sensitivity calibration using PDM generator.

References: [1] A. Rekik, F. Azaïs, F. Mailly, P. Nouet, M. Masmoudi, Self-test and self-calibration of a MEMS convective

accelerometer, Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS (DTIP2013), p. 239-242, Barcelona, Spain, April 16th – 18th, 2013.

[2] A.A. Rekik, F. Azaïs, F. Mailly, P. Nouet, Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective Accelerometers, doi: 10.1007/s10836-013-5423-7, Journal of Electronic Testing: theory and applications, Volume 30, Issue 1 (2014), p. 87-100.

heater

detectors

sensing direction

without acceleration

under acceleration

RD1 RD2RH

RREF1 RREF2

VddN-bit register

N-bit ML-LFSR

Programming Word

Clock

N-bit comparator

Vdd

PDM generator

43

Microelectronics Department – 2013 Activity Report 1

Low-‐Power Front-‐End for Resistive Sensors L. LATORRE, F. MAILLY, P. NOUET Contact: [email protected]

Topic: Integrated Sensors

Interest for cheap and low-‐power integrated sensors is constantly growing with the development of low-‐cost portable consumer products and Wireless Sensor Networks (WSN). The use of standard CMOS technology together with cheap wet-‐etching post-‐process enables the batch fabrication of monolithic multi-‐sensor circuits that include accelerometers, magnetometers, microphones, pressure sensors, and temperature sensors. The design of such low-‐cost multi-‐sensors system is limited by a set of fabrication constraints that makes the use of capacitive sensing very difficult if not impossible. Therefore, resistive sensing is generally considered using either the piezoresistivity of polysilicon for mechanical devices or the temperature dependence of integrated resistors for thermal applications (including thermal accelerometers).

Resistive sensing is commonly valued for its low cost and ease of implementation but suffers from poor performance regarding the power consumption and the signal-‐to-‐noise ratio. In this context, we have proposed and patented an innovative circuit for the conditioning of resistive sensors that addresses the above mentioned issues. This so-‐called “Active Bridge” (figure 1) structure aims at providing amplification and limited noise contribution while using the same current to bias both sensing elements and amplification circuitry.

The Active Bridge main features are a high gain and high output impedance at very low biasing current (typically in the µA range or below). The implementation of a feedback circuitry is necessary to address gain and process mismatch issues.

Both analog (i.e. continuous time) and digital (i.e. ΣΔ) feedback schemes have been investigated in various applications (inertial sensing, magnetic sensing). A digital output, high-‐resolution, micro-‐power, temperature sensors based on complementary temperature coefficient of resistors in an Active Bridge has been also developed and characterized.

𝑣𝑣!"# = −4𝑔𝑔!𝐼𝐼! 𝑟𝑟!"! ∕∕ 𝑟𝑟!"! ∆𝑅𝑅!""

Figure 1: Architecture of the “Active Bridg”

Figure 2: CMOS Temperature sensor based on the Active Bridge and polysilicon thermistors

References:

[1] Hacine S., Mailly F.,Latorre L., Nouet P., "Study of a high-‐resolution and low-‐power CMOS temperature sensor”, IEEE 10th International Conference on New Circuits and Systems Conference (NEWCAS), Montreal, Quebec, 17-‐20 June, 2012, pp. 205-‐208. DOI : 10.1109/NEWCAS.2012.6328992

[2] E. M. Boujamaa, P. Nouet, F. Mailly, L. Latorre, Circuit for Amplifying a Signal Representing a Variation in Resistance of a Variable Resistance and Corresponding Sensor, US Patent 8,487,701 B2, July 16, 2013.

R0+ΔR1

Vdd

R0+ΔR1

R0-‐ΔR2

R0-‐ΔR2

VoutMP1 MP2

MN1 MN2

44

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45


46

SECURITY

47


Bulk Built-‐in Current Sensors (BBICS) for Detection of Transients Faults G. DI NATALE, M.L. FLOTTES, B. ROUZEYRE, Contact : [email protected]

O. POTIN(*), R. P. BASTOS(*) Topic: Attacks, Sensors, Fault Tolerance

Project/Partners: . National – FUI 2010 Calisson2/ J.-‐M. DUTERTRE(*) ENSMSE – Gardanne

. P-‐SOC INS2I CNRS . Europe – Catrene -‐ CT302 TOETS

Natural phenomenon such as alpha particles and cosmic neutrons may be responsible of transient voltage variations on circuit’s internal nodes. When the transient is captured in a memory element, the so-‐called transient fault (TF) provokes a soft error (SE). This well-‐known phenomenon is all the more significant since recent and deep-‐submicron technologies are more sensitive, even at ground level. In addition to natural phenomenon, transients may also be the consequence of fault attacks perpetrated on circuits dedicated to digital security. The faulty behavior is used in this case to reveal confidential information (e.g. the encryption key of a crypto-‐processor). In any case, natural or intentional transients must be detected as soon as possible in order to launch recovery operations. In order to cope with these faulty transients, we explore sensor-‐based solutions, namely Bulk Built-‐In Current Sensors (BBICSs). BBICSs are connected to the bulk and used to detect anomalous transient currents flowing between reverse biased drain junction and the bulk. These currents, negligible in fault-‐free scenarios, are much higher during faulty scenarios, i.e. in case of laser illumination or particles’ strikes. These transient currents are used to switch BBICS cells to a faulty state, the flag rose in this case can be used to launch a recovery system or to reset the chip according to the application. Last year, further optimizations of the BBICS implementation have been investigated to end up in a single BBICS for monitoring both PMOS and NMOS

bulk currents with a reduced area overhead compared to previous solutions [1]. We also explored recovery schemes for dealing with detection of short-‐to-‐ long duration transient faults in logic design. We proposed a new recovery infrastructure dedicated to asynchronous concurrent error detection schemes as BBICS. It requires less resources and lower latency than existing similar strategies [2].

Several versions of the proposed BBICS sensors are currently under production for further experimentations (evaluation of the sensors under real laser attacks).

References: [1] A New Recovery Scheme against Short-‐to-‐Long Duration Transient Faults in Combinational Logic, R. Possamai Bastos, G.

Di Natale, M. Flottes, F. Lu, B. Rouzeyre, Journal of Electronic Testing (JETTA), Springer, June 2013, Volume 29, Issue 3, pp 331-‐340.

[2] A Bulk Built-‐in Sensor for Detection of Fault Attacks, Rodrigo Possamai Bastos, Frank Sill Torres*, Jean-‐Max Dutertre, Marie-‐Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, IEEE International Symposium on Hardware-‐Oriented Security nad Trust (HOST’13), pp 51-‐54.

(*) Olivier Potin is a Research Engineer at LIRMM, under a fixed-‐term contract. Rodrigo Possamai Bastos was post-‐doc at LIRMM and now Assistant Professor at TIMA laboratory, since Oct. 2012. Jean-‐Max Dutertre is Assistant Professor at ENSMSE, CMP Gardanne.

Recovery scheme based on two latches to sample results of asynchronous CED mechanisms (e.g. BBICS)

SECURITY

48


[Texte]

Fault attacks: Modeling and Simulation G. DI NATALE, M.L. FLOTTES, F. LU, B. ROUZEYRE Contact: [email protected]

Topic: Laser Attacks, Fault Modeling, Fault Simulation

Fault simulation is a standard method for the evaluation of testability and reliability of digital integrated circuits and, more recently, for the evaluation of countermeasures against fault attacks in secure circuits. Modern hardware devices (such as cellular phones, e-tablets, credit cards) require security and privacy protection. For achieving the high security level, secure protocols and strong encryption algorithms are widely studied. However, the hardware that implements the secure algorithms and protocols is becoming the focus of attacks. Among all types of attacks performed on the hardware part of the system, fault attacks have proven to be very effective. By provoking an error during an encryption process, the secret key may be retrieved. Fault simulation is therefore the solution for validating the effectiveness of countermeasures inserted to cope with this type of attacks, without the need of actually producing an integrated circuit to perform real (and expensive) fault attacks. tLIFTING is a delay-annotated open-source simulator able to perform both logic and fault simulation for single/multiple stuck-at faults, Single Event Upset

(SEU) and Multiple Bit Upset (MBU), and Single/ Multiple Event Transients (SET/MET) and even at electrical level. It automatically performs multi-level simulations (0-delay logic level, delay-annotated logic level, or electrical level) to study the effect of the fault on the whole system. In particular, it split the execution of the whole simulation in 5 steps: in the first step the whole circuit is logically simulated (without timing effects) to discover its state. A timing-annotated logic simulation is then executed for the period corresponding to the effect of the fault. This allows generating the input stimuli for the sub-part of the circuit affected by the fault. This sub-part is simulated at spice level, by injecting the fault. The spice simulation’s result is used to create a fault list that is re-injected in the logic simulator to know the effect of the fault at system level.

References:

[1] Feng Lu, Giorgio Di Natale, Marie-Lise Flottes and Bruno Rouzeyre, “Laser-Induced Fault Simulation”, 16th Euromicro Conference on Digital System Design (DSD 2013), Spain, 4-6 September, 2013

1 tLI FTI NG: A Mult i- level Delay- annotated Fault Simulator f or Digit al Circuits

Giorgio Di Natale, Marie- Lise Flot tes, Feng Lu, Bruno Rouzeyre

CONTACTS: [email protected]; [email protected]; [email protected]; [email protected]

MULTI PLE LEVEL FAULT SI MULATI ON PROCESS

Timed Simulation Fault injection

Step1

Step2

Step3

Step4

Step5

tLI FTING Simulation (logic-level) Hspice (transistor-level)

Without delay With delay Step 1: Whole circuit Logic-level simulation without delay from start to the first r ising edge before fault injection

Registers states

Step 2: Whole circuit Logic-level simulation with delay from the first rising edge before fault injection to the first rising edge after fault injection

Faulted sub-circuit

and Stimuli

Step 3: Sub-circuit Transistor-level fault simulation with fault model

Logic-level Timed Fault

List

Step 4: Whole circuit Logic-level fault simulation with delay

Step 5: Whole circuit Logic-level simulation without delay for the remaining time

Registers states

Univ. Montpellier II/CNRS - France

g1 I1 I2

g2

g5

g3

g6 ADD21

g4

I3

O1

O2

O2

Fault sim ulat ion

g1 I1 I2 g2

g5

g3

g6 ADD21

g4

I3

O1

O2

O2

Logic sim ulat ion

Basic Sim ulator

Circuit netlist (.v)

Delay-annotated file

(.sdf)

Stimuli

Logic-level Timed Fault List

Simulation Report

Fault Report

ARCHI TECTURE of tLI FTI NG FAULT SI MULATOR

Fault injection parameters

Hspice LEGEND

Fault Modeling

Verilog Library (.v)

NAND INV

INV ADD21

NAND NAND N+ N+

P-substrate

Drain Gate Source

Laser: Energy; Center; Diameter; Start & End time

Physical

Fault m odel Layout

Drain

Source

Gate Bulk

Ifault

Fault

* example: Laser Induced Faults

Character ist ics Mixed-mode multi-level simulation:

- 0-delay gate-level - delay-annotated gate-level - transistor-level Fault types:

- Single/Multiple Event Transient (SET/MET) - Single Event Upset (SEU) / Multiple Bit Upset (MBU) - Stuck-at Electrical behavior modeling

Applicat ions Fault simulation:

- Single/Multiple Event Transient (SET/MET) - Single Event Upset (SEU) / Multiple Bit Upset (MBU) - Stuck-at Secure circuits: fault attacks

- Fault attacks ( Laser, EM, ...) - Evaluation of countermeasures Reliability evaluation

Layout (.lef & .def)

Sub-

circ

uit

des

crip

tion

Sub-

circ

uit

sti

mul

i

Sub-circuit netlist

Electrical fault model

Gate model with fault

Stimuli for sub-circuit

Tem p files for hspice

Transistor- level net list w ith fault m odel

1 t LI FTI NG: A Mult i- level Delay- annotated Fault Simulator f or Digit al Circuits

Giorgio Di Natale, Marie- Lise Flot tes, Feng Lu, Bruno Rouzeyre

CONTACTS: [email protected]; [email protected]; [email protected]; [email protected]

MULTI PLE LEVEL FAULT SI MULATI ON PROCESS

Timed Simulation Fault injection

Step1

Step2

Step3

Step4

Step5

tLIFTING Simulation (logic-level) Hspice (transistor-level)

Without delay With delay Step 1: Whole circuit Logic-level simulation without delay from start to the first rising edge before fault injection

Registers states

Step 2: Whole circuit Logic-level simulation with delay from the first r ising edge before fault injection to the first r ising edge after fault injection

Faulted sub-circuit

and Stimuli

Step 3: Sub-circuit Transistor-level fault simulation with fault model

Logic-level Timed Fault

List

Step 4: Whole circuit Logic-level fault simulation with delay

Step 5: Whole circuit Logic-level simulation without delay for the remaining time

Registers states

Univ. Montpellier II/CNRS - France

g1 I1 I2

g2

g5

g3

g6 ADD21

g4

I3

O1

O2

O2

Fault sim ulat ion

g1 I1 I2 g2

g5

g3

g6 ADD21

g4

I3

O1

O2

O2

Logic sim ulat ion

Basic Sim ulator

Circuit netlist (.v)

Delay-annotated file

(.sdf)

Stimuli

Logic-level Timed Fault List

Simulation Report

Fault Report

ARCHI TECTURE of tLI FTI NG FAULT SI MULATOR

Fault injection parameters

Hspice LEGEND

Fault Modeling

Verilog Library (.v)

NAND INV

INV ADD21

NAND NAND N+ N+

P-substrate

Drain Gate Source

Laser: Energy; Center; Diameter; Start & End time

Physical

Fault m odel Layout

Drain

Source

Gate Bulk

Ifault

Fault

* example: Laser Induced Faults

Character ist ics Mixed-mode multi-level simulation:

- 0-delay gate-level - delay-annotated gate-level - transistor-level Fault types:

- Single/Multiple Event Transient (SET/MET) - Single Event Upset (SEU) / Multiple Bit Upset (MBU) - Stuck-at Electrical behavior modeling

Applicat ions Fault simulation:

- Single/Multiple Event Transient (SET/MET) - Single Event Upset (SEU) / Multiple Bit Upset (MBU) - Stuck-at Secure circuits: fault attacks

- Fault attacks ( Laser, EM, ...) - Evaluation of countermeasures Reliability evaluation

Layout (.lef & .def)

Sub-

circ

uit

des

crip

tion

Sub-

circ

uit

sti

mul

i

Sub-circuit netlist

Electrical fault model

Gate model with fault

Stimuli for sub-circuit

Tem p files for hspice

Transistor- level net list w ith fault m odel

49


Scan-‐based Test of Secure Devices J. DA ROLT, G. DI NATALE, ML. FLOTTES, B. ROUZEYRE

Contact : [email protected] Topic: Test of Secure Devices

Insertion of scan chains is the most common technique to ensure full observability and controllability of sequential elements in an integrated circuit. However, when the chip deals with secret information, the scan chain can be used as back door for accessing secret (or hidden) information, and thus jeopardize the overall device security. A common industrial practice to avoid scan-‐based attacks is to physically disconnect the scan chains after production testing by blowing fuses located at both ends of the scan chains. However, this solution impedes the testing of those devices requiring being tested after manufacturing. In particular, the correct behavior of the secure circuits should be validated after the introduction of the secret key, which can be programmed at any time of the circuit’s lifecycle.

We have recently proposed a smart test controller that exploits the following observations: • The scan-‐based test of digital circuits follows a predefined scheme: input vectors are shifted-‐in via the scan-‐in (with scan-‐en asserted), one functional clock cycle is applied (also known as capture cycle, with scan-‐en not asserted), and output responses are shifted-‐out via scan-‐out (while, at the same time, the next input vector is shifted in).

• Known attacks are based on the fact that the circuit is first run in normal mode for a certain number of clock cycles in order to bring the circuit to a desired state (for instance in the AES, the circuit is run up to the first encryption round). Then the scan chain is used to observe the state of the circuit in that moment.

The principle of the proposed controller relies on the masking of the scan-‐out signal in such a way that it does not deliver any sensitive data until the whole scan chain is first freshen. The controller reads the scan-‐en signal and, based on its value, it forces to 0 the OUT_en signal that drives a 2-‐bit AND gate whose other input is the CUT’s scan-‐out.

The controller is automatically armed at power-‐on (Normal state). Once it is armed, OUT_en is forced to 0 in order to filter any shift-‐out operations. In this

initial state, a down-‐counter is set to #L, i.e., the number of scan flip-‐flops in CUT. After #L consecutive clock cycles with scan-‐en asserted, the controller is disarmed. During the Flushing state, the controller is still armed (OUT_en=0) to prevent the observation of the scan chain content after a normal execution (i.e. scan attacks). After disarming the controller, OUT_en is set to 1 so that any scan operation is performed without masking. The controller allows one or two capture cycles (to allow stuck-‐at-‐ and delay-‐fault testing) without re-‐arming OUT_en.

The controller allows identifying two execution modes: normal and test (MODE signal). Nevertheless, it does not require any additional signal to force one of the two modes since the detection of the mode is performed automatically: the Normal state is the normal mode, while all the other states define the test mode. the controller automatically detects. The execution mode may be possibly used when two secret keys are used.

This controller can be inserted into the design at the very end of the design, thus not perturbing the overall design flow. It is also transparent to the tester because it does not modify the classical and standard test procedures. The area introduced by the controller is meaningless.

References:

[1] J.Da Rolt, G.Di Natale, M.-‐L.Flottes, B.Rouzeyre, “A Smart Test Controller for Scan Chains in Secure Circuits”, IEEE International On-‐Line Testing Symposium 2013 (IOLTS,13), July 2013

CUTS_en

S_in

S_outSecretKey

normal test

KNormal KTest

Smart ControllerOUT_en

MODES_en

S_en

S_in

S_out

NormalOUT_en = 0MODE = normalCOUNTER = #L

S_en=0

FlushingOUT_en = 0MODE = testCOUNTER --

S_en=1

S_en=0 and COUNTER>0

Stuck-At-CaptureOUT_en = 1MODE = testCOUNTER=0

COUNTER=0

Delay-CaptureOUT_en = 1MODE = testCOUNTER=0

S_en=0

ShiftingOUT_en = 1MODE = testCOUNTER=0

S_en=1S_en=0

S_en=1

S_en=0

S_en=1

S_en=1

50


Protected Test Access Method for Secure Devices J. DA ROLT, G. DI NATALE, ML. FLOTTES, B. ROUZEYRE Partners: Catholic University of Leuven

Contact : [email protected] Topic: Test of Secure Devices

As far as security is a concern, usual design-‐for-‐testability techniques such as the insertion of scan chain may prove to be a backdoor for hackers since they ensure full control and observation of the internal states of a device. In order to protect access to test mode, we sought to provide security features to the IEEE 1149.1 JTAG interface by including a Schnorr-‐based secure test protocol, and to provide an efficient hardware implementation of the protocol using elliptic curve cryptography.

We solved the inherent key-‐management problem of existing Symmetric-‐Key Cryptography (SKC) based secure JTAG approaches using Public-‐Key Cryptography (PKC). Specifically, if SKC is used for securing JTAG, there will be a common master secret key for all products or a large secret-‐key database needs to be maintained at the tester/updater side, which are not good options for mass electronic products. PKC implementations are inherently more hardware expensive and slower than SKC based approaches. Therefore it is a challenging task to incorporate PKC in a resource-‐constrained environment like JTAG. We used an enhanced version of ECC-‐based Schnorr Protocol as the public-‐key cryptographic protocol in our secure JTAG test scheme. Various public-‐key implementations, such as RSA or ECC, may be used to solve the key-‐management problems present in previous secure JTAG approaches. We chose ECC as it offers the same security as RSA, with much smaller area footprint. Area overhead is of critical importance, since we are constrained in terms of silicon area required to incorporate security features into JTAG, owing to the small test interface available in most applications. Similarly, various protocols using ECC may been used. We chose the Schnorr protocol as it is provably secure and allows efficient implementation on space-‐constrained hardware.

Our proposed architecture is shown in Figure. The ordinary JTAG circuitry is enclosed within dotted lines, and it is divided into its two main components:

the TAP finite state machine and the instruction decoder.

The Schnorr controller performs the Schnorr protocol. It interacts with a modified JTAG instruction decoder, ECC module, and a 192-‐bit random number generator. The base point coordinates (curve parameters) are fetched from an external non-‐volatile memory. The system is supposed to be locked in the beginning. In order to unlock it, the tester must manipulate the JTAG inputs to enter the new ‘UNLOCK’ instruction. Then, the instruction decoder informs the Schnorr controller to start the protocol, by means of the ‘request_unlock’ signal. As soon as the authenticity of the test server is verified, the Schnorr controller activates the ‘release_unlock’ signal, informing the instruction decoder that other instructions can now be performed. For instance, if the system is unlocked, the design under test (DUT) boundary scan register can be controlled. Meanwhile, when ‘release_unlock’ signal is not active, the instruction decoder sets the multiplexer ‘MUX1’ to always select the output from the multiplexer ‘MUX2’, which is controlled by the Schnorr controller, impeding the shift out of any DUT specific register.

The hardware implementation showed that the whole circuit could be synthesized in less than 25K gates.

References:

[1] Amitabh Das, Jean Da Rolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, Giorgio Di Natale, Marie-‐Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede, “Secure JTAG Implementation Using Schnorr Protocol”, Journal of Electronic Testing (JETTA), Springer, DOI: 10.1007/s10836-‐013-‐5369-‐9.

following Fermat’s little theorem. However, in affine coordi-nates inversion is performed at every iteration of the pointmultiplication algorithm. Thus, a dedicated inversion unitbased on extended Euclidian algorithm is implemented whichalso helps efficient execution of ECDSA on our secure JTAGscheme. Here we provide implementation details for bothdesigns which provide better design variations and the usercan opt for one of them in practice.

5 Secure JTAG Implementation

5.1 Integration of the ECC-processor with JTAG

An important contribution in our paper is the integrationof the ECC based Schnorr controller and ECC pointmultiplier with the JTAG interface along with the othermodules. This has been done in a seamless manner so asnot to affect the timing aspects of the IEEE 1149.1 JTAGstandard, and also keeping the behavior of the TAP finitestate machine (illustrated in Appendix F) unchanged.

Our proposed architecture is shown in Fig. 1. The ordinaryJTAG circuitry is enclosed within dotted lines, and it is dividedinto its two main components: the TAP finite state machine andthe instruction decoder. The Schnorr protocol (described inAppendix A), as well as the ECDSA signature authenticationare performed by the Schnorr controller, placed in the center ofFig. 1. It interacts with a modified JTAG instruction decoder,ECCmodule, and a 192-bit random number generator (a LinearFeedback Shift Register). The base point coordinates (curveparameters) are fetched from an external non-volatile memory.

The system is supposed to be locked in the beginning. Inorder to unlock it, the tester must manipulate the JTAG inputs toenter the new ‘UNLOCK’ instruction. Then, the instructiondecoder informs the Schnorr controller to start the protocol, bymeans of the ‘request_unlock’ signal. As soon as the authentic-ity of the test server is verified, the Schnorr controller activatesthe ‘release_unlock’ signal, informing the instruction decoderthat other instructions can now be performed. For instance, if thesystem is unlocked, the design under test (DUT) boundary scanregister can be controlled. Meanwhile, when ‘release_unlock’signal is not active, the instruction decoder sets the multiplexer‘MUX1’ to always select the output from the multiplexer‘MUX2’, which is controlled by the Schnorr controller, imped-ing the shift out of any DUT specific register.

During the protocol execution, the communication withtest server consists of using the Schnorr shift registers(192 bits) to shift in and out information required for theprotocol. For instance, the transmission of the intermediatevalues, ‘Ta’ and ‘Tb’ (Protocol in Appendix A) is performedby means of shifting out the value ‘Ta’ (or ‘Tb’) once the ECCpoint multiplication is finished. It is important to notice thatthe shifting is always controlled by the test server, and that thetiming for executing point multiplications depends on thescalar multiplier. It means that the Schnorr controller mustinform the test server that it has finished each operation of theprotocol. This synchronization is achieved by always addingone flip-flop at the end of the Schnorr shift register that is setto’1’ if the information in the shift register is valid, otherwisethe multiplexer ‘MUX2’ selects the TDI input and the syn-chronization flip-flop is set to ‘0’. Thus, the test server keepson shifting at least this one bit to detect that the Schnorr

TAPFSM

192-bit PRNG

NVM(for curve parameter

Storage)

Schnorrcontroller

ECCpoint multiplication

&modular multiplication

Instruction register

SynchronizationFlip-Flop

TMSTCK

TRST

TDO

Schnorr shift registers

private key

shift_ir / pause_ir/ update_ir / capture_ir

shift_drpause_drupdate_drcapture_dr

instruction decoder

request_unlockrelease_lock

TDI DUT Boundary scan

DUT specific registers

MUX2

MUX1

Fig. 1 JTAG-ECC controllerintegration architectural blockdiagram

198 J Electron Test (2013) 29:193–209

51


Hardware Security and Trust G. DI NATALE, S. DUPUIS, M. L. FLOTTES, B. ROUZEYRE


Project/Partners: HOMERE (Hardware trOjans : Menaces et robustEsse des ciRcuits intEgrés), FUI AAP14 COST Action IC -‐ 1204 Trustworthy Manufacturing and Utilization of Secure Devices

Topic: Digital Security, Trust, Hardware Trojans

Hardware Trojans (HTs) are malicious circuit’s alterations introduced to change an integrated circuit (IC) expected functionality when deployed in the field. The goal of such alterations can be to introduce a hidden functionality, reduce the IC’s reliability, let leak sensitive information or cause a denial of service. HTs can be designed to be always on, i.e. able to affect the infected circuit at any time, or they may require an internal or external trigger to become active. Outsourcing design or fabrication services to external facilities as well as using third-‐party Intellectual Property (IP) cores are common practices that make ICs increasingly vulnerable w.r.t these HTs. Due to the diversity of possible implementations, activation and effects on the IC’s functionality, the detection of HTs is a very challenging task. Recently, numerous detection approaches have been published for post-‐silicon trust validation. Most of them assume that the design, layout and testing steps are trusted, while the fabrication facility is the only untrusted step of the design flow. HT detection approaches can be destructive or not; for the latter ones, detection mechanisms can be applied at test time or run-‐time. Non-‐destructive methods are divided into two categories: side-‐channel analysis [1] and logic testing. Our work focuses on logic testing, in which the

principle is to stimulate the input ports of an IC and monitor its outputs. If an erroneous behavior of the IC is observed, it can be inferred that a HT has been inserted in the IC. However, traditional ATPG testing may not be sufficient to detect HTs which are indeed stealthy in nature i.e. mostly inactive unless they are triggered by a “rare value”. The main goal is therefore to be able to activate potential HTs. We have proposed a procedure to identify circuit sites where a possible HT may easily be inserted [2]. The selection of the sites is based on the assumption that a potential HT is triggered (i) by nodes with a rare value (i.e. that are very rarely ‘0’ or very rarely ‘1), (ii) in paths that are not critical in terms of delay, and (iii) combining multiple gates that are close one to the other in the circuit’s layout, and close to available space. To find nodes with a rare value, we have developed two tools. The first one computes the probability of each node to be ‘0’ or ‘1’ (cf. fig. 1). The second one is based on simulation results and calculates the number of ‘0’, ‘1’, rising and falling of each node, as well as the different values taken by a given set of nodes. To identify non critical path, we have developed a tool that calculates the slack time of each node (cf. fig.2).

Figure 1. Probability computation.

Figure 2. Slack time computation.

References: [1] S. Dupuis, G. Di Natale, M.-‐L. Flottes, B. Rouzeyre, “On the effectiveness of Hardware Trojan Horses

Detection via Side-‐Channel Analysis” (to be published in Information Security Journal: A global perspective)

[2] G. Di Natale, S. Dupuis, M.-‐L. Flottes, B. Rouzeyre, “Identification of Hardware Trojans triggering signals”, First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2013)

(1/2, 1/2)

(1/2, 1/2)

(1/2, 1/2)

(1/2, 1/2)

(1/2, 1/2)

(1/2, 1/2)

(1/2, 1/2)

(1/2, 1/2)

(3/4, 1/4)

(3/4, 1/4)

(3/4, 1/4)

(15/16, 1/16)

(15/16, 1/16)

(255/256, 1/256)(3/4, 1/4)

(0, 0)

(0, 1)

(0, 1)

(0, 2)

(0, 2)

(ASAP, ALAP)

(0, 0)

SLACK

0

0

1

(1, 1)0

0(1, 1)

2

0(2, 2)

2

0(3, 3)

(4, 4)0

(3, 3) 00(2, 2)

1

52


Trustworthy Manufacturing and Utilization of Secure Devices

G. Di Natale, S. Dupuis, M.-‐L. Flottes, B. Rouzeyre Contact: [email protected]

Topics: Secure Devices, Test and Security, Hardware Trojans, Fault Attacks

Hardware security is becoming increasingly important for many embedded systems applications ranging from small RFID tag to satellites orbiting the earth. Its relevance is expected to increase in the upcoming decades since secure applications such as public services, communication, control and healthcare will keep growing. The vulnerability of hardware devices that implement cryptography functions (including smart cards) has become the Achille’s heel in the last decade. Therefore, the industry is recognizing the significance of hardware security to combat semiconductor device counterfeiting, theft of service and tampering.

We lead a COST action (TRUDEVICE, IC1204) to create a European network of competence and experts on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization.

COST is an intergovernmental framework for European Cooperation in Science and Technology, allowing the coordination of nationally-‐funded research on a European level. As a precursor of advanced multidisciplinary research, COST plays a very important role in building a European Research Area (ERA). It anticipates and complements the activities of the EU Framework Programmes, constituting a “bridge” towards the scientific communities of emerging countries. It also increases the mobility of researchers across Europe and fosters the establishment of scientific excellence. COST does not fund research itself but provides a platform for European scientists to cooperate on a particular project and exchange expertise.

This Action aims at a practical design and manufacturing flow that keeps the balance between the level of protection against threats and the above-‐mentioned characteristics. Five scientific areas targeted by this Action cover aspects of trustworthiness and security during manufacturing, test and device’s lifetime, while the last area focuses on validation. The five areas are: Area 1: Manufacturing test of secure devices Area 2: Trustworthy manufacturing of secure devices Area 3: Fault attack detection and protection Area 4: Reconfigurable devices for secure functions Area 5: Validation, Evaluation, and Fault Injection

The main objectives of this Action are (i) the knowledge creation to respond to new issues, and (ii) the consolidation of the scientific excellence in the target domain through the integration of the research skills of the participants. From a scientific perspective, this project targets the following goals: • To provide solutions for required but conflicting

relationships between Testability and Security. • To define secure protocols to protect the access

to necessary test infrastructures and to design secure access controllers

• To study new mechanisms for devices identification and authentication based on the usage of Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs)

• To address issues related to counterfeiting and Hardware Trojan insertion and to propose new methods and algorithms for their identification

• To define new architectures able to detect faults and to resist to fault attacks

From the networking point of view, this Action is anticipated to aid towards the development of early-‐stage faculty researchers into experts in their respective fields, and improve the knowledge and skills of Ph. D. students and post-‐doctoral fellows, which will enable them to perform high-‐quality research. Moreover, it will support mobility between participating research centers, both of senior researchers to foster exchange of ideas through short term visits, and of junior researchers/PhD students to enable the exchange of technical knowledge through longer term visits.

The project has been approved in June 2012 and it started on 12th December 2012. It will last for 4 years and, so far, it includes more than 50 institutions coming from 22 different countries. More details can be found at:

http://www.cost.eu/domains_actions/ict/Actions/IC1204

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Microelectronic Department - 2010 Activity Report 1

New Passive and Non-Invasive Sensor for Glaucoma Diagnosis A. DELUTHAULT, S. BERNARD, F. SOULIER, V. KERZERHO Contact : [email protected]

Project/Partners: Ophtimalia,

Topic: Sensor, RF, Medical devices

Glaucoma being an ocular pathology and the second cause of blindness in people over the age of 50, the aging of the world population will lead to further increase the number of patients greatly visually impaired by this disease. In most cases, glaucoma is associated with an increase in Intra Ocular Pressure (IOP). In this work funded within the ANR-TecSan project MATEO, we are developing disposable eye lenses including a specific pressure sensor to measure IOP all day long. The instrumented lens will communicate by radio frequency to an electronic chip located on glasses arms and daily information would thus be available for ophthalmologists to improve diagnoses. The system consists of a sensor implanted on a lens and an external reader on the glasses, see figure 1. The system is therefore based on inductive coupling between the coils L1 and L2 respectively representing the reader and the embedded sensor. So any parameter variation on the lens induced by a mechanical deformation of the cornea will be converted into a frequency shift, detectable while measuring either the impedance magnitude or phase. The challenges are multiple. Firstly, the sensor design must offer the maximum sensitivity due to the small deformation of the cornea (less than 3µm). Secondly, it should be coupled with the integrated antenna on a small transparent polymer lens. Thirdly, electronics should deal with a composite signal degraded by strong interferences to extract data and provide a reliable and accurate IOP measurement. We propose implementations of signal processing and high-level architecture of the active integrated circuit,

under high constraints in terms of area overhead, power consumption, robustness, testability and safety. Moreover, we develop algorithms for measurement data extraction. Finally, a key point remains the integration of auto-test techniques to guarantee the reliability of the system. The aims are both to analyze the system before delivery and adapt it to environment variations by an auto-calibration process. First experimental results on big eye demonstrate the direct correlation between our system and a reference measurement by TonoVet as the figure 2 illustrates.

Figure 2: Comparison between our system and reference measurement on pig eye IOP.

Figure 1: Principle of the wireless communication (sensor in the lens and reader on glasses)


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Self-‐Adaptive System for intraocular pressure measurement A. DELUTHAULT, S. BERNARD, F. SOULIER, V. KERZERHO Contact : [email protected]

Project/Partners:SACSO/Ophtimalia, NXP, TIMA


In the context of high performance systems and critical applications, the objective of the SACSO project is to design Self-‐Adaptive Systems, which are able to monitor the surrounding environment and adapt themselves to different scenarios and requirements. In other words, a Self-‐Adaptive System must be able to provide the required high performances regardless the application mode and despite the changing environmental conditions. The MATEO project has been introduced to develop a lens based intraocular pressure measurement sensor to provide 24 hours measurement and therefore better diagnoses However, such a measure must be self adapted to the patient and to his environment for different reasons. The variability of the anatomical, biomechanical and physiological indicators must be taken in consideration for an accurate standard IOP measurement and are more numerous and important for a lens based measurement. The various possible environments or activities can impact on above indicators or the system it-‐self. We found several indicators (Blood pressure, heart rate, eye blinking, eye blinking rate, cornea thickness, sclera thickness, lachrymal fluid dynamics, ocular motion, body position, temperature and air concentration) that we have categorized (disturbing/informant, systemic/specific and dynamic/static)[1][2][3][4].

In this context of multi-‐indicators measurement we firstly look for temporary and easy to use solution platform in order to make our own multi-‐indicator results using the Ophtimalia’s device. We find the embedded e-‐Health platform using an Arduino as support which is able to measure several indicators (blood pressure, heart rate, oxygen saturation, ECG, EMG, air flow, galvanic skin response, temperature, body position, glycemic index). After reviewing all the possibilities and the limits of the e-‐Health platform the next step is to redesign it in order to add new measurement system for indicators which are missing and remove what is not necessary. This step will be done with the aim to use the platform for multi-‐indicators measurement on a horse in parallel with the Ophtimalia’s device.

Reference: [1] Yazici1 B, Usta E, and et al. Comparison of ambulatory

blood pressure values in patients with glaucoma and ocular hypertension. Eye, 2003.

[2] Liu John H., Sit Arthu J., and et al. Variation of 24-‐hour intraocular pressure in healthy individuals. Ophthalmolo-‐gy, 2005.

[3] M Detr-‐Morel and et al. Utilité de la pachymétrie cor-‐néenne dans l’hypertension occulaire. Bull. Soc. Belge Ophtalmol., pages 1–9, 2004.

[4] Cooper R L, Beale D G, and et al. Continual monitoring of intraocular pressure : Effect of central venous pression, respiration, and eye mouvements on continual recordings of intraocular pressure in the rabbit, dog, and man. Br J Ophthalmol, 1979.

Figure 1 Arduino e-Health Platform

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A biomechanical emulator of eye A. DELUTHAULT, S. BERNARD, F. SOULIER, V. KERZERHO Contact : [email protected]

Project/Partners: SACSO/Ophtimalia, NXP, TIMA


A medical device is intended for treating the patient or for bringing a help to the diagnosis of pathology with a minimal risk. Today bridging the gap between the design of an e-‐Health medical device and the ex-‐vivo tests is becoming increasingly necessary for different reasons. The devel-‐opment of an electronic medical device, and in particu-‐lar of an e-‐Health device, can be impacted by the varia-‐bility of physiologic and anatomic parameters inside a population, the lack of stability and repeatability of the measurements on a single sample for the qualification of the device under development and the long time and the high cost of experimentation settings. Running simulations can help evaluate and understand some mechanisms and behaviors, but is not sufficient to validate solutions to be used on living subjects. In the developpement strategy of e-‐Health devices, the draw-‐backs of in-‐vivo, ex-‐vivo doesn’t ease the first design conception. For that, the conception phase includes a test bench with an artificial reproduction of the living organ or a subset of it, filling the gap between conven-‐tional validation tools (simulatior, classic test bench) and the ex-‐vivo experiments [1]. In the context of the developpement of device for IOP measurement a new tool called ”Biomechanical Eye Emulator” (BEE) has been designed, presented Figure 1. The BEE reproduce the common trend of the biome-‐chanic behavior of the cornea. This tool allows to make

repeatable comparison of Ophtimalia’s pressure sensor to find the best design solution.

The BEE is basically composed in two parts: an artificial ocular globe which performs the anatomical emulation and the physio-‐mechanical control which allows varia-‐tion of internal pressure and motion of the artificial ocular globe. This artificial ocular globe is made of an half sphere of steel, emulating the posterior globe of the eye, and an half sphere of silicone, which enable the strains due to the increase of pressure by the amount of water injected wthin. The physio-‐mechanical control of the artificial ocular globe relies on two parts: the pressure control by a syringe pump and the motion (rotation) control by two stepper mo-‐tors. The specifications of the BEE were chosen to be as close as possible to human anatomical characteristics and fit with the biomechanical common trend of the the cornea. In addition the ranges of those specifica-‐tions were chosen to be as close as possible to the variability of the human characteristics. This approach of designing an artificial test bench from a living target has some limits. Obviously, some addi-‐tional features has to be implemented in the next ver-‐sion of the BEE. A new membrane closer to the human cornea, eyelid and the eye blinking phenomenon may affect the IOP monitoring in case of using a contact lens. The more we seek to be closer to the real eye the more anatomical and physiological aspect or functions we must add. But the first aim of this system is not to make a copy of a real eye, the conception of this kind of system is to give a support during the design phase of a e-‐Health technology. We had to make compromis-‐es in the selection of critical parameters for the BEE’s first version in order to use it like a test bench and enhance the development of solutions.

Reference: [1] V. Laukhin, I. Sánchez, A. Moya, E. Laukhina, R.

Martin, F. Ussa, C. Rovira, C. Rovira, A. Guimera, R. Villa, et al., “Non-‐invasive intraocular pressure monitoring with a contact lens engineered with a nanostructured polymeric sensing film,” Sensors and Actuators, 2011.

Figure 1 BEE system view.

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Validation of New Multipolar Electrode Architecture for ENG Recording. O. ROSSEL, F. SOULIER, S. BERNARD, G. CATHEBRAS Contact: [email protected]

Project/Partners: AXA, INSERM Topic: Nerve Model & Analog Signal Processing

In the context of FES, neural recording is one of the main issues, as the control requires information, carried on afferent peripherals nerve. Because specific information is carried into different fascicles, we propose to realize a non-‐invasive and spatial-‐selective electrode. Last year, based on investigation on the topic of Extracellular Action Potentials (AP), we proposed a new tripoles design, were the tripolar output signal is the image of the activity on the close vicinity of this tripole, providing high spatial selectivity. We showed however, that this high spatial selectivity is achieved at the expense of signal amplitude. This first result jeopardizes the feasibility of this kind of electrode since the signal amplitude appears to be on the same range of the expected noise. First we propose to estimate the performance of the proposed electrode with a quantitative study of the electrode selectivity. Then, to conclude on the feasibility of this electrode, the SNR has to be determined. So with a more accurate model, we studied the sensitivity of the proposed tripole, allowing us to determine precisely the amplitude level of the expected signal. Thus, the SNR can be estimated knowing the expected noise. In short the work of this year aims at characterizing the performances and evaluating the feasibility this new multi-‐contact cuff electrode. We proposed an electrode configuration inspired from the FINE electrode designed for the same purpose. The electrode is composed of many tripoles, placed around the nerve. The main difference between existing multipolar cuff electrode and our proposal is the longitudinal inter-‐pole distance, which is 5mm for the classical electrode and 0.375mm for our electrode.

The recording is locally sensitive and increases the selectivity of electroneurogramm recording. This year we realized an experiment to validate this approach. The study of the small tripole sensibility was realized for single fiber action potential (SFAP). We proceed in the same way for the experiment by trying to measure SFAP. However, in-‐vitro experiment the SFAP would not be measurable by a small tripole. So, we decided to privilege an approach based on an

artificial axon. In this artificial model, every parameter is known. The position of the fiber and the NDR, the position of the electrode of measure, as well as the involved currents are knows. This allows to implement and to estimate with accuracy the filtering realized by the small tripole, with the same configurations as in simulations. By realizing different measure for several radial distances, we can verify the influence of this radial distance, to estimate the sensibility the small tripole.

Figure 1. Validation of of our electrode by simulation and with an artificial axon

To verify the sensibility of the monopolar and tripolar recording, we estimate the amplitude of a SFAP measured by a monopolar electrode and by the small tripolar electrode.

In the figure 1, the small tripole recording sensibility is estimated and compared with that one of the monopolar recording.

We can notify that the measurements correspond to the theoretical results. We can note that the attenuation according to the radial distance is more important for the small tripole than for the monopolar measurement.

This confirms that the measurement realized by one small tripole is sensitive exclusively to the closest fibers .

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Implant for Functional Electrical Stimulation J. SALLES, S.BERNARD, G. CATHEBRAS, F. SOULIER


Project/Partners: FP7 TIME / Neuromedics Topic: Analog Design, Functional Electrical Stimulation (FES)

Functional Electrical Stimulation (FES) has been used for about 30 years in order to restore deficient physiological functions. At the beginning, only surface stimulation was possible and thus only used in a clinical context due to the low reliability of electrode placements. In the early eighties, implanted FES appeared through well-‐known applications: pacemaker, Brindley bladder control, cochlear implant, and more recently deep brain stimulation (DBS).

Currently, FES is the only way to restore motor function even though biological solutions are studied, but not yet successfully tested on humans. Few teams carry out researches on implanted FES and the functional results remain poor.

The team developed a microstimulator in 2006 and a prototype (ASIC) was fabricated. The microstimulator can be divided in to two main parts: a controller (digital) and an active part (analog). In the active part, the output stage gets its input current from an external DAC converter which set the maximum stimulation amplitude. This current is then distributed to a twelve-‐pole stimulating electrode. A pole can be set in four different states: anode, cathode (both current controlled), open (high impedance) or shunt (voltage-‐controlled). A digital block controls the evolution of the pole states and the ratio of the stimulation current on each pole.

Some faults were observed while carrying out the circuit characterization. These faults were of four main kinds:

• asymmetry between poles (up to 108 μA),

• input/output non-‐linearities (over 4 LSB),

• over-‐consumption on idle state,

• erratic level-‐shifter behavior.

Since 2006, some researchs and experiments were carried out and few subcircuits were developed to fully access its faults and correct them. Finally, a corrected version was designed in 2010. The new IC offers three structural modifications and better layout techniques to improve the stimulator characteristics. Some simulation results are presented in the following pictures. The improvement in the matching of the 12 channels can be seen in figure 1. The results in terms of linearity are an integral non-‐linearity of +-‐2.5LSB and a differential non-‐linearity of +-‐0.3 LSB

.The command structure was also modified to get rid of the over-‐consumption. Finally, the level-‐shifter parts were designed anew.

The corrected ASIC was manufactured on November 2010 and is now under test and characterization.

Figure 1: Simulated voltage/current characteristics of CAFE12

)

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Implanted medical devices self-‐adaptive to fibrosis S. BERNARD, F. SOULIER, V. KERZERHO Contact : [email protected]

Project/Partners: FibroSES /IMS, INL, IBCP, Telecom Bretagne, ERRMECE, XP-‐MED, LE2I, LIP6, ETIS

Topic: fibrosis, medical devices

Innovations in integrated circuit technologies have spurred a revolution in in vivo healthcare monitoring, thereby catalyzing a significant growth in implantable medical devices. When implanting a foreign device into the body, a particular tissue is produced as a self-‐defence reaction. The fibrosis phenomenon is different from cicatrization since the presence of activated cells (expressing α-‐SMA) is maintained over a longer duration implying a continuous accumulation of extracellular matrix.

Figure 1: method for fibrosis Vs interface impedance analysis over-‐time

The development of fibrosis surrounding an implanted device or an implanted electrode is reflected by a characteristic change in the measured electrical impedance of the interface and/or the tissue itself. In order to develop a self-‐adaptive strategy for implanted devices, it is at first mandatory to precisely quantify the impact of fibrosis over time. In the FibroSES project an experimental approach, based on repeated in-‐vivo impedance

measurements over-‐time, along with periodic biological characterizations is carried out. The main goal is to identify physical and biological key influences in the formation and development of fibrosis, and to define a reliable and reproducible impedimetric-‐based fibrosis indicator (cf. figure 1). The methodology is based on the implantation of cuff-‐electrodes in mini-‐pigs, to make periodic impedance measurement between two contacts of the cuff and in parallel, to extract biological markers from the explantation of the cuff. A simple equivalent circuit model of tissue impedance is comprised of the series combination of the capacitance Cm, and the resistance Ri both of which are in parallel with the extra-‐cellular fluid of resistance Re (Fig. 2). A more complete model encompasses constant phase element (CPE). From the impedance measurement, ZCPE parameters are extracted and compared to the presence of biological markers A comparative study of electrical and biological parameters collected along the time exhibits a correlation between an electrical marker of fibrosis development and biological analyses.

(a) (b)

Figure 2: (a): Simple Equivalent circuit model of tissue impedance. (b): Schematic representation of current flow through a biological tissue

The preliminary results obtained are very encouraging and in a near future, new animal experimentations will be conducted to confirm them. The next step will focus on the design of an embedded system for the bio-‐impedance measurement and the marker extraction.

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Role and Involvement at the International and National LevelsSocieties •TestTechnologyTechnicalCouncil(TTTC)oftheIEEEComputerSociety •IFIPTechnicalCommitteeEditorialBoardofJournals •IEEETransactionsonVLSI •IEEEDesign&TestofComputers •JournalofElectronicTesting:TheoryandApplications(Springer) •ASPJournalofLowPowerElectronics •TheVLSIjournal(Elsevier) •InternationalJournalofReconfigurableComputing(Hindawi) •IOPJournalofNeuralEngineeringConferenceCommittees(GeneralChairs&ProgramChairs) •The5thInternationalSymposiumonElectronicDesign,TestandApplications(IEEEDELTA2011) •The3rdInternationalWorkshoponImpactofLow-PowerdesignonTestandReliability(LPonTR’11) •ThefirstEuropeanworkshoponCMOSVariability(VARI’11)ExecutiveCommitteesofConferences •IEEE/ACMDesign,Automation,andTestinEuropeconference(DATE) •IEEESymposiumonDesignandDiagnosticsofElectronicCircuitsandSystems(DDECS) •IEEEInternationalSymposiumonElectronicDesign,TestandApplications(DELTA) •Design&TechnologyofIntegratedSystemsinNano-scaleEra(DTIS) •IEEEEuropeanTestSymposium(ETS) •IEEEAsianTestSymposium(ATS) •IEEEAsianSymposiumonQualityElectronicDesign(ASQED) •InternationalConferenceonFieldProgrammableLogicandApplications(FPL) •IEEEComputerSocietyAnnualSymposiumonVLSI(ISVLSI) •IEEEWorkshoponSignalPropagationonInterconnects(SPI) •IFIP/IEEEInternationalConferenceonVeryLargeScaleIntegration(VLSI-SoC) •IEEEInternationalConferenceonReconfigurableComputing(ReConfig) •IEEEInternationalNEWCASConferenceCNRS:CentreNationaldelaRechercheScientifique •DéléguéScientifique •MembreduConseilScientifique(INS2I) •DirecteuretmembresdecomitédepilotageduGDRSoC-SiP,duGDRMNSANR:AgenceNationaledelaRecherche • Membres de comités de pilotage •MembresdecomitésSectorielsSTICetNANOAERES:Agenced’évaluationdelaRechercheetdel’enseignementsupérieur •Présidentsetmembresdecomitésd’évaluationdelaboratoirefrançais

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International Academic Cooperations

Brazil:UFRGS,PUCRS(PortoAlegre)–Capes/Cofecub

Canada:Univ.ofWaterloo,McMasterUniversity(Hamilton)

Germany:Univ.ofDarmstadt,Univ.ofStuttgart,KarlsruheInstituteofTechnology,Univ.ofFreiburg

Denmark:UniversityofAalborg

Italy:PolitecnicodiTorino,Univ.ofCatania,CampusBiomedicoofRoma,SSAPisa

Japan:KyushuInstituteofTechnology,Univ.ofTokyo

Spain:UPCBarcelona,UABBarcelona

Switzerland:UNILLausanne,EPFLNeuchâtel

Tunisia:UniversityofSFAX

UnitedKingdom:UniversityofLancaster

USA:UMASSAmherst,Univ.ofConnecticut,StanfordUniversity

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Ongoing European and National Projects

• 6 projects in the framework of CATRENE, ENIAC and FP7 Europeanprograms: - ENIAC European program: “ELESIS, European library-based flow of embedded silicon test instruments ” (2012-2015) - ENIAC European program: “MODERN, Modeling and Design of Reliable, process variation-aware - CATRENE European program: “TOETS, Towards One European Test Solution” (2009-2012) Nanoelectronic devices, circuits and systems” (2009-2012) - FP7 European program: “TIME, Transverse Intrafascicular Multichannel Electrode system for induction of sensation and treatment of phantom limb pain in amputees” (2008-2012) - FP7 European program: «MONT-BLANC : European scalable and power efficient HPC platform based on low-power embedded technology» (2011-2014)

•12ANRProjectsinthefieldsofMicrosystems,SecuredSystems,Multi-processorsArchitectures,Healthcare,EmergingTechnologies,Test&ReliabilityofMemories:

- MARS - LIESSE - SACSO - E-MATAHARI - EMAISeCi - SIMMIC - EMYR - DIPMEM - HAMLET - SECRESOC - LIESSE - DIPMEM

•1InternationalScientificCollaborativeProject(PICS)withPolitecnicodiTorino,Italy

•3FCEprojectsinthefieldsofDesignandTestofsecuredintegratedcircuits and systems: - CALISSON - PROSECURE - MAGE

•1otherFCEproject - NEUROCOM

•Severalfundedbi-nationalresearchprojectswithKarlsruheInstituteof Technology (PROCOPE-MOKA) and PUCRS (CAPES/COFECUB)

•Mainacademicpartners:TIMA, LIP6, CEA, LabSTICC, Paris’Tech, IEF,IMS, LAAS, IETR, CMP, SPINTEC, IM2NP, LaHc, ENSMSE

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Industrial Partners

Microelectronic Department - 2010 Activity Report

Industrial Partners

Medical Partners

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Industrial Partners ISyTest: A Joint Institute between LIRMM and NXP

Lafisi: A Joint lab between LIRMM and POLITO

http://www.lirmm.fr/isytest

ISyTest: Institute for System Testing

Partners:LIRMM, France – NXP (founded by Philips), FranceFirst joint Institute Industry/Academic of CNRS and UM2 with NXPObjective:Develop innovative test methods and techniques for integrated system solutions, SiP and SoC. By sharing their expertise from both academic and industrial sectors, partners will be able to develop truly inventive and cost-effective solutions with direct technological transfer to future electrical devices.

http://www.lirmm.fr/LEA_LAFISI

LAFISI:French-ItalianLAboratoryforscientificresearchonhardware-softwareIntegratedSystems

Partners:LIRMM, France - Politecnico di Torino, ItalyObjective:promote researches in the field of H/S integrated systems, with special emphasis on test pattern generation for power estimation and performance verification, software-based test of processor-based systems, fault diagnosis, circuit and system reliability evaluation, and fault tolerant techniques.

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SECNUM Platform

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SECNUM Platform Supported Platforms

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Sample Gallery

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Sample Gallery Sample Gallery

Laboratoired’Informatique,deRobotiqueetdeMicroélectroniquedeMontpellier161rueAda-34095Montpellier-Cedex05-FRANCETel:33(0)467418585-Fax:33(0)467418500

www.lirmm.fr

HeadoftheMicroelectronicsDepartment:[email protected]:33(0)467418666

department microelectronics - lirmm.fr d... · few words about lirmm and the microelectronics...

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