delivering vlsi chips to hep...

Delivering VLSI chips to HEP experiments

A. Marchioro / CERN-EP Amsterdam - September 29, 2003

LECC2003-Amsterdam A.Marchioro/CERN 2

Some undisputable statements1. LHC experiments would just not be possible without ASICs

2. … and this is true also for future HEP experiments

3. Total amount spent in DMILL is: 11 “LHC magnet-euros” (1)

Total amount spent in 0.25 µm is: 6 “LHC magnet-euros”

4. If any improvements will be introduced in LHC+ experiments, ASICs will again play a major role

Higher detector granularity and better resolutionspower reductionhigher speedhigher densitymore radiation resistance…

(1) Data from 1997 until May 2003 - LHC special monetary units is defined from corridor rumors


Outline

Introduction and ThemeBenefits of ASICsHistory and Lessons learned

Activity profileRelationships with suppliers

Moving forward Technical challengesWhat are the expected costs

Conclusions

Reticle from MPW8Reticle from MPW8


Theme of the talkThe first 15-20 years of VLSI design in the community was

organized mainly as a “fancy R&D” activity

Wish: Bring this activity to the level of a reliable, affordableand customer-oriented design serviceQuestion: How to organize the community of designers in the future within HEP as to provide:

The best chips for experimentsHigher performance

Both in terms of physics results and electrical parametersMore robust and reliable circuitsWithin the shortest design cycle

ButWithout killing creativity and frustrating innovationWithin budget


Historical Comparison

PervasiveLHC+

LHC

LEP

UA

Large utilization of “first generation”

Pervasive

FewLarge utilization of “first generation”

Not usedSome

Custom Integrated circuits

Standard, dedicated and custom microprocessors

Technology evolutionTechnology

penetration


Fascination of “The Small”0.8 µm

0.25 µm

0.13 µm

Power consumption:0.25 um: Inverter @ 100 MHz: 5.5 uW0.13 um: Inverter @ 100 MHz: 0.58 uW

Power consumption:0.25 um: Inverter @ 100 MHz: 5.5 uW0.13 um: Inverter @ 100 MHz: 0.58 uW

P1262 SRAM Cell20022002

11 mmmm

Contact in 1978


Summary of State-of-the-Art ADC(*)

290 mW75 MS/s120.35 CMOS

UCB

Radiation Tolerant

95 mW40 MS/s120.25 CMOS

ChipIdea

123 mW150 MS/s100.18 CMOS

Samsung

Commercial69 mW80 MS/s100.18 CMOS

National

310 mW2 GS/s60.18 CMOS

Broadcom

Radar70 mW1 GS/s40.25 CMOS

Stanford

Oscilloscope

10 W20 GS/s80.18 CMOS

Agilent

Applic.Power(**)Speed# BitsTech

(*) From ISSCC2003, (**)Analog core only


Potential benefits

The current limiting factor for many detectors is power dissipation

Power (both Watts and Amperes) must be reduced using:

New architectureNew circuit designNew technology

Material budget in CMS tracker

All electronics related


Future areas of workImportant Functional blocks

Basic analog libraryAll our designs are hand-made. Shorter design time requires parametrized models (Matlab etc.)

Low power AD convertersVery efficient and intelligent power regulatorsSimple chips: is a stock of 74XX compatible rad-tolerant chips desirable ?Complex digital blocks

Rad tolerant: DSP, FPGAsMemory/FIFO generatorHigh speed (bi-directional) serializersCompact and efficient data compression modules

Exotic chips/macros:RF transmission Optical modulation and switching

Is CMOS the only technology we will ever need ?Complex systems on chip

Large Pixelated and monolithic detectorFull calorimeter channel read-out with sophisticated signal processingUniversal rad-hard control and monitoring chip-set for all detectorsNew flexible timing and trigger distribution system


Outline



of HW … and SWMoving forward

Technical challengesWhat are the expected costs

Conclusions Reticle from MPW8Reticle from MPW8


Current service organization

CentralService

SupplierTech Adm

User 1 User 2 User …

CADService

Other External Services(dicing, testing, packaging, etc.)


MPW submissions (1)

MPWs statistics

0

5

10

15

20

25

MPW1MPW2MPW3MPW4MPW5MPW6MPW7MPW8MPW9MPW10MPW11

N of

chi

ps p

er M

PW

0

1

2

3

4

5

6

7

8

9

10

N of

Inst

itute

s pe

r M

PW

N chipsN Institutes

Total number of chips submitted: 184Institutes involved: 20

(1) as of July 2003

Reticle from MPW9Reticle from MPW9


MPW, Eng Run and Production Submissions

Total different projects: 20Institutes involved: 17

"Project specific" engineering runs(red point: forecast)

0

1

2

3

4

5

6

7

8

9

10

1998 1999 2000 2001 2002 2003 2004 2005 2006

Year

Num

ber o

f run

s


Production runsTotal number of projects in production: 18Institutes involved: 14

Production summary

0

100

200

300

400

500

600

700

800

900

1000

Y 2000 Y 2001 Y 2002 Y 2003 Y 2004

N o

f waf

ers

prod

uced

0

2

4

6

8

10

12

14

N o

f pro

ject

s in

pro

duct

ion

N of wafers produced

N of projects in production

Forecast


Prototyping vs. production needs

0

2

4

6

8

10

12

14

16

APV25

RAL_MGPA

adc4

1240

_full

Atlasp

ixHPTDC

CERN_gol

IN2P

3_HAL2

5

DTMROC-S

CERN_LVDSBUF

INFN-D

CU

PSI_CMSPIX

RAL_Fe

nixv3

CERN_Alice

_TOF

CERN_LD2

PLL25

NEVIS_gain

score

RAL-mux

pll

NEVIS_clkf

o

CERN_qxp

ll

CERN_Dela

ychip

CERN-CARIO

CABee

tle

Nikhef_

Alcapo

ne0

INFNCa_

DIALOG

INFNCa_

SYNCCCU

CERN_LVDSMUX

Delta

Pacea

m

CERN_Pixe

l

ATLASPIX

-MCC

INFNTo

_pas

cal_v

2

INFNTo

_ambra

_v2

Medipi

x

CERN_OpA

mp

CERN_Ana

log_M

ux

OSSU_VDC4I5

OSSU_DORIC

4I5

OSSI_OPTO

NEVIS_sca

c

CERN_RX40

otisD

LLLH

CBPIX

NIKHEF_ALA

BUFKch

ip

CERN_pilo

t

CERN_Ana

log_p

ilot

INFNBo_

carlo

s

CERN_na60

_32_

CH

Rutgers

_TBM

RAL_CPR

RAL-dfx

RAL-apv

b

RAL_HEPAPS1

RAL_DSMBGN2

RAL_APVMUX3

RAL_CMSMUX1

RAL_Mda

c40

Nikhef_

pixadc

2

CERN_rd49

_nan

opix

SCT-test

CERN_MONOPIX_1

CERN_apd

CERN_asr1

_b

CPPM_T1X

PAD

Beetle

1.2MAO

bigpm

os_c

hipTote

m

CERN_MIB

EDO

KIP_H

DR

CERN_CZTGE_1

7AC

CERN_CZTGE_1

7DC60

CERN_CZTGE_1

7DC90

I2Cex

pand

er

Num

ber o

f pro

toty

pe c

ycle

s

0

20000

40000

60000

80000

100000

120000

Num

ber o

f ASI

Cs

need

ed

prototype cyclesneeds (ASICs)

43 projects need more than 2000 pieces (20 more than 10000)6 projects need between 100 and 2000 pieces74 different chips integrated

Project


Lessons: Relationships with supplier

Who are we ?HEP is a technology driver in several areas:

Magnets and cooling technologyParticle detector technologyIT (in some respect)

… But definitively not in semiconductor components

Where are silicon foundries going ?Are silicon ASICs generic “commodity” items

In which areas do we need “special” relationships


Capacity of semicon industryCapacity and Utilization RatesCapacity and Utilization Rates

% Utilization 8” Wafer Starts

Worldwide IC Manufacturers – 1999-2003

% Utilization Capacity 8” Wafer Starts per week 1,000s

Source: Semiconductor Industry Association


Capacity of semicon industry (2)

MOS Capacity by Dimensions

0

200

400

600

800

1000

1200

1400

2Q00

3Q00

4Q00

1Q01

2Q01

3Q01

4Q01

1Q02

2Q02

3Q02

4Q02

1Q03

WSp

W x

1000

>=0.7µ<0.7µ >=0.4µ<0.4µ >=0.3µ<0.3µ<0.3µ >=0.2µ<0.2µ<0.2µ >=0.16µ<0.16µ

Source: Semiconductor Industry Association


Why is it vital to have an excellent relationship with foundry ?

A very intimate knowledge of silicon manufacturing process is required for essentially all analog designs

Example: monolithic pixel, ADC, APV25, bandgap, etc, etc…Designs coming from our community have often“special requirements”:

But often they are “weak”, or just about working with nominal process conditions

Going from prototypes to production is NOT a smooth ride !Understanding yield issues requires strict collaboration with foundry


Foundry interface (i.e. yield debugging)Example of “debugging”: yield issue

Problems on several projects (APV25, Atlaspix, HAL25, Medipix)Negotiation with foundry contacts at different levels to “acknowledge” the problemNegotiation on individual items (return of material/replacement)Regular phone conferencesDesign of special test structuresVisit to foundryFeed-back recommendation to users based on findings and learning

CERN investment: ~ 6 man*monthsFoundry investment: >> 6 man*months


Debugging chips

• Commercial Physical Analysis Lab Investment:

• Minimum equipment: > 2 M$• People: > 10

Hot-spot analysis

Electron microscopyand metrology

De-Layering

SEM


Relationship with tool supplierTwo levels of additional complexity

Analog: models (and transistors!) are increasingly more difficultDigital:

Large number of gatesPredominance of wires over transistor delays

Well characterized digital library is absolutely necessary Tools were “easy” until ¼ micron generation, less than obvious for future generationsEffort has been made on negotiating wafer costs, can we do the same for tools?


Summary of lessons:What can go wrong (and should be avoided in the future!)

Design stageEntire design done with out-of-date models Inappropriate selection of cells from libraryWrong DRC set Insufficient/excessive layer fillingInexistent or insufficient circuit protections

FoundryInconsistent GDSII file (inconsistent cell naming)Wrong or forgotten masksMarginal process

Wide Vt or other parameter spreadMarginal metal planarization, etching

PackagingInappropriate pad opening, passivation choiceWafer dicing cut through chipsWrong mounting (rotated chips or empty packages)Wrong chip selection on MPW wafer


Outline



Moving forward Technical challengesWhat are the expected costs

ConclusionsReticle from MPW8Reticle from MPW8


Moving forward

¼ micron technology is well established and well suited for first LHC generation0.18 µm technology skipped due to lack of resources and marginal cost advantages130 nm technology: significant benefits can be expected

Need to evaluation Radiation Hardness… design tools... understand costs


Moore’s Law was “almost” perfect

Moore’s Law in 1977 predicted a 57” waferby 2003


Where is industry going

Papers at ISSCC

0

10

20

30

40

50

<90 n

m13

0 nm

150n

m18

0 nm

.25 um

.35 um .5 um

.8 um

Technology generation

Num

ber o

f pap

ers

ISSCC 2002ISSCC 2003


Complexity: extraction of parasitic C


Increasing design complexityExample:

Delay model in 0.8 µm technology∆ = ∆gate + Σn δload

Delay model in 0.25 µm technology∆ = ∆gate + f(trise) + Σn δload + Σk δ ’cap-wire

Delay model in 0.13 µm technology and below∆ = ∆gate+f(trise) + Σn δload + Σk δ’cap-wire + Σj δ’’ Neighbors-activity

n: number of nets in circuitk: number of capacitive cross couplings of nets in circuitj: number of cross-coupled switching neighbor nets


Are HEP volume problems unique ?

Kind permission from: M. Rieger, Avant Corp.

0

100

200

300

400

500

600

700

0.40+ 0.25 0.2 0.18 0.15 0.13

250

500

1000

2500

5000

1000

0

Wafers per Mask

Mask CostWafer Cost

$K p

er m

ask

set

ASIC/SoC

MPU DRAM


Comparison MPW prices (25 mm2)

0%

50%

100%

150%

200%

250%

300%

350%

400%

450%

500%

Vendor A Vendor B Vendor C Vendor D MOSIS 0.25

Relative cost

Relative cost of 130 nm proto run vs. ¼µ

0.25 um


Are MOSIS/Europractice an option ?

Consider:What is the mandate of these services?

Does it match the requirements for HEP experiments ?

Peculiar spectrum of requirements from our communityExample: (1) CMS needs several circuits in quantities of 100,000+ at

reasonably low cost(2) Alice needs 112 dedicated chips without which the Pixel read-

out would not workWhen you will have to repair/refit LHC in 2012(?), will MOSIS/Europractice still offer the same technology?If you have a “yield” problem, who will assist you?What if you want to deposit amorphous Si on a wafer ?


Macro-economy vs. micro-economy of chip design

What are the economic deciding factors in the selection of a technology?

Cost of wafersCost of prototypingCost of designSystem integration (what is the cost impact of a particular ASIC in a given system)

How can one construct a formula that takes into account the real total costs of a design project for HEP?

Can there be such a formula as to cover high and low volume projects?


Where to focus our attention

Very highVery high(the product is a

“system”, not a “chip”)

LowIntegration of system

MediumMedium (good engineers are

expensive)

Low(in-house resources are “almost free”)

Cost of Design

HighLow(irrelevant w.r.t time-

to-market)

Very HighCost of prototypes

LowHigh(because of very high

volume)

Very HighCost of wafers

Future HEP perspective

Traditional industry view

Traditional HEP view

Importance of different cost contributions:


Next generation: What is neededTools

Design toolsP&R tools at early stage of designP&R cost/license is in the 1M$ range

Better verification tools:Electromigration, IR drop, substrate coupling, power analysis …

New well characterized LibrariesFree from some vendor, RH (especially SEU) to be verified

SubmissionAt least 2-3 MPW runs per year

PeopleExpertise and know-how is exclusively in the mind of people

Relationship with vendorThis is not a “commodity” technology, don’t select your supplier just on first order wafer cost !!!

CoordinationMuch more coordination is needed among HEP Institutes


ConclusionsThe future of instrumentation for HEP remains in microelectronicsThe last 5-6 years have shown that a good common service can be afforded if people in the community act coherently and with a long-range viewIn my mind, there is no way we can go beyond ¼ micron CMOS without a very special relationship with wafer and tool suppliersTo continue to succeed in the future, we must master higher costs and complexities:

Better system design prior to ASIC layoutShorter design timeMore reuse of common blocks

Less NIH attitudeBetter architectural planning

Sub-contracting to specialized design firms… in one word: more collaboration


“Custom integrated circuits have profoundly changed the way front-end electronics systems are designed. Indeed, there is no other way to build most present high energy physics experiments”

A. Lankford, LECC 1999

delivering vlsi chips to hep...

Documents