defect reduction for semiconductor memory applications
TRANSCRIPT
Mark Melliar-Smith Chief Executive Officer
Defect Reduction for Semiconductor Memory Applications Using Jet And
Flash Imprint Lithography
Zhengmao Ye, Kang Luo, Xiaoming Lu, Brian Fletcher, Weijun Liu, Frank Xu, Dwayne LaBrake, Douglas Resnick, Matt Shafran, Saul Lee, Whitney Longsine, Van Truskett,
S. V. Sreenivasan
February 26th, 2013
Overview
J-FIL memory strategy and roadmap
Mask status
Wafer defect data › Defect mechanisms › Short-run vs. long-run defect trends › Approach to achieve >20 lot runs at low defectivity
Conclusions › Excellent overall progress towards manufacturing › Mask plans and resist processes in place for 1x nm
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J-FIL Memory Manufacturing
Industry infrastructure:
› Equipment partner experienced in building and shipping J-FILTM steppers
› High quality DNP commercial imprints replica masks available today
J-FIL Stepper installations Customer’s Facility
3
Focusing on CMOS memory due to defect tolerance
Multiple tools installed for system refinement and process integration
Large semiconductor manufacturer has plans to ramp J-FILTM into advanced memory production by 2015.
2011 2012 2013 2014 2015 2016
Gen 2 Cluster (6 modules) Stepper Production CoO and <8nm O/L
Gen 2 (1 module) Stepper Production CoO and <8nm O/L
Equip. Partner ‘s Gen 1 Yield Targets and <10nm O/L
Imprio 450 300mm and 450mm Capable
Mask Commercial Supply DNP Mask Shop
Semiconductor Platform Roadmap
Perfecta MR5000 2X nm 1X nm
Wafer
Mask Replication
IM30
IM20
Development Line 2X nm 10 nm
IM30’C’
Pilot Production 1x nm 10 nm
Production Ramp 1x nm 10 nm
Molecular Imprints Platform
Equipment Partner Stepper
ship module
Molecular Imprints Module
Legend
Process Integration 24 nm 10 nm
4
Collaborative Relationships
Semiconductor J-FILTM Collaboration
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Imprint Masks Imprint Stepper
Apps and Materials
Memory IC Manufacturer
Equipment Partner Mask Shop Partner Resist Partner
Molecular Imprints
Mask Replicator Imprint Modules
Imprint Resist
Material Formulation
MII Confidential
J-FIL’s Manufacturing Readiness ATTRIBUTE Feb 2011 Sep 2012 Current Status Mfg Target TEMPLATE
Master CDU 1.2nm 1.2nm 1.2nm ~ 1nm
Image Placement 4nm 2.5nm 2.5nm < 3nm
Master Defectivity 10 def/cm2 0 to 1 def/cm2 0 def/cm2 < 0.1 def/cm2
Replica Defectivity to be determined 5 def/cm2 3 def/cm2 <1 def/cm2
IMPRINT LER 2nm 2nm 2nm <2nm
Overlay Accuracy 10nm 10nm 10nm < 8nm
CDU on Wafer to be determined 0.5nm 0.5nm < 1 nm
Throughput 5-7 wph 10 wph 10 wph 20wph
Defects (short run, ~2 wafers) 10 def/cm2 ~2 def/cm2 ~2 def/cm2 <0.1 def/cm2
Defects (long run, > 1 lot) to be determined <50 def/cm2 <10 def/cm2 <1 def/cm2
Data Source SPIE . SEMATECH Litho Forum
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Overview
J-FIL memory strategy and roadmap
Mask status
Wafer defect data › Defect mechanisms › Short-run vs. long-run defect trends › Approach to achieve >20 lot runs at low defectivity
Conclusions › Excellent overall progress towards manufacturing › Mask plans and resist processes in place for 1x nm
7
Mask Replication Master Masks
› Fabrication by e-beam › Inspected by e-beam and repaired
Replica Masks using J-FIL
› Enable low cost mask copies that can be used for all lines in memory fab › Leads to low overall cost of ownership
One replica is expected to be used to imprint ~500 wafers (20 lots)
…MasterMask …
Replicas createdby imprint
Wafers printed on J-FIL steppers
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Mask Infrastructure Readiness Status 2012
Master/Replica @ 2x nm Target 2012 Units
Master defectivity 0 0 with repair defects/cm2
Replica added image placement < 2 <2 nm, 3σ
Replica defect density <1 3 defects/cm2
Relica CDU 2 1.5 nm, 3σ
Defect repair of masters Yes In use
Resist etch resistance* 30% over 2011 Baseline
15% improvement
* Improved etch resistance is needed relative to Cr, and the etch process window is related to replica defects.
DNP is primarily shipping replica masks
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1xnm Mask Technology
E-Beam
Double Patterning
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15nm master/replica mask feasibility
Overview
J-FIL memory strategy and roadmap
Mask status
Wafer defect data › Defect mechanisms › Short-run vs. long-run defect trends › Approach to achieve >20 lot runs at low defectivity
Conclusions › Excellent overall progress towards manufacturing › Mask plans and resist processes in place for 1x nm
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J-FIL Electrical Yield: Excellent Progress
1 10 100 1000 10000
100%
80%
60%
40%
20%
0%
Line Length (mm)
Yiel
d
26nm HP
J-FIL
Electrical Defect Testing: Yield vs. Line Length
DNP presented yesterday that yields >90% have been achieved for 10 meter lines
More progress expected with improvements in contamination control as discussed next, and with reduced mask replica defects.
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Defect Mechanisms for 2xnm Features Separation step can cause pattern shear
failure. Particularly challenging for sub-25nm features at high throughput
Solved using improved precision machine design, real-time algorithms for controlled separation and enhanced resists
B. Sub-30nm particles lead to plug defects, causing line breaks in the resist
A. Surface contamination control is required to prevent fluid filling issues during the resist filling process
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A. and B. are key areas of ongoing development
A. Surface Contamination on Wafers Soft contaminants are airborne organic contaminants that adsorb
onto wafers causing local fluid flow disruption induced defects. › These contaminants can cause high defects › They do not cause repeaters, mask surface treatment promotes “self-cleaning”
0102030405060708090
100
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130
Impr
int S
peci
fic D
efec
ts #
/cm
2
Imprint Number
DD increate rate: 0.0028 pcs/cm2 per imprint
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Solution: Requires in-tool control of airborne contaminants
B. Sub-30 Particles Cause Line Breaks
Particles cause line break defects › Can cause high defects, and lead to repeaters › Mask cleaning (wet or dry) can recover most defects –
particles are predominantly soft organic particles
Establish Root-Cause by Introducing Sub-30nm Polystyrene Particles
Single Line Break Observed in 2xnm Half-Pitch Lines
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Solution: Requires in-line resist filtration; and in-situ mask cleaning
In-Line Sub-10nm Filtration
Sub-10nm inline multi-pass filtration installed in resist dispense system
› Has led to > two orders of magnitude reduction in defects at the 2x nm.
Two new generations of resist filtration improvements are planned, should lead to much lower defectivity
Recirculation system & Reservoir
Ink Jet
Resist Re- Fill bottle
Resist circulation Pump
10 nm filter
Hydra10 nm Filter
New recirculation filtration system
Vent
Waste bottle
Vent
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Mask Cleaning Addresses Line Plug Defects Defects Caused by Sub-30 Particles
90% 92% 94% 96% 98%
100% 102%
0 1 2
Def
ect D
ensi
ty
Reclaim #
2xnm features Preliminary results indicate >90% mask defect removal rate with cleaning
Implies mask plug defects are caused predominantly by soft polymeric contaminants
Now incorporating in-situ VUV cleaning systems on the stepper to extend mask life
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MII Confidential
Short Run Defectivity: Total Defect Density
Total defectivity at 2xnm CD is ~10 defect/cm2
Defect increase rate: 8x10-4/cm2 per imprint (2 adders/cm2 per lot)
Defect increase rate key to mask life of >500 wafers (20 lots) – To stay below 1 defect/cm2, requires 0.05 adders/cm2 per lot
Initial defectivity is from replica defects which will be <1/cm2 in 2013 Fluctuations in defect density are from surface contaminations Defect increase rate is from particles causing mask plugs
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MII Confidential
Long Run Defectivity: Over 12 Wafers
Device-like mask: 78% of each 26x33mm field consist of 2x nm fine features
Defect level is ~13 defect/cm2 with an increase rate of 5 adders/cm2 per lot
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Initial defectivity is from replica defects which will be <1/cm2 in 2013 Fluctuations in defect density are from surface contaminations Defect increase rate is from particles causing mask plugs
MII Confidential
3,281 1,680
3,380 437
276 132
37
4.7
426,563
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Impr
int A
dded
Def
ect D
ensit
y per
Lot
[#/cm
2]
Timeline (month)
Long Run Defectivity: Adders Over 1 Wafer Lot
Trend of imprint defect adder per lot (25 wafers)
Current (Q4 2012): › Defect increase rate: 4.7
adders/cm2 per lot (25 wafers)
2013 goal: › 1 adder/cm2 per 10 lots
(250 wafers)
2014 goal: › 1 adder/cm2 per 20 lots
(500 wafers)
Q4 2012
2011 2012
DRIVERS: Resist filtration Separation development
(HW/SW/Control/process) Resist improvement Imprint POR development
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Mask life limitations dominated by soft particles in resist.
Established final steps towards mask life target for production
2013 goal 0.1 >10x improvement each from resist filtration and inline mask cleaning 2014 goal <0.05
Status, end of 2012 <5
Defect adder/cm2 per lot Comments
Manufacturing target <0.05 20 lot mask replica life
Integrated in-stepper VUV mask cleaning is being implemented, based on >90% clean efficiency data expect to achieve an additional >10x improvement in mask life
Approach to Achieve >20 lot Mask Life
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Overview
J-FIL memory strategy and roadmap
Mask status
Wafer defect data › Defect mechanisms › Short-run vs. long-run defect trends › Approach to achieve >10 lot runs at low defectivity
Conclusions › Excellent overall progress towards manufacturing › Mask plans and resist processes in place for 1x nm
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Conclusions
Excellent progress in all aspects of patterning for manufacturing
Plans in place for memory production ramp in 2015
1x nm direct patterning being investigated for mask, nominal resist process exists
Focusing on CMOS memory due to defect tolerance
J-FIL has key advantages – Sub-10nm direct replication – Attractive cost structure due to low
cost tool and mask replication
Post etch BPM pattern on disk Baseline resist and etch process exists at 12nm half-pitch due to progress in HDD BPM
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Acknowledgements
TEXAS-ETF
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