decimal floating-point adder and multifunction unit with ... · decimal floating-point adder and...
TRANSCRIPT
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This research is supported by the UW-Madision Graduate School and IBM
1
Department of Electrical and Computer Engineering
MMadison adison EEmbedded mbedded SSystems & ystems & AArchitectures Laboratoryrchitectures Laboratory(MESA)
Decimal Floating-Point Adder and Multifunction Unit with Injection-Based
Rounding
Liang-Kai Wang and Michael J. SchulteUniversity of Wisconsin-Madison
ARITH-18, Montpellier, France
Department of Electrical and Computer Engineering
MMadison adison EEmbedded mbedded SSystems & ystems & AArchitectures Laboratoryrchitectures Laboratory(MESA)
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Outline
• Motivation• Related Research• Algorithm for Decimal Floating-Point (DFP)
Adder and Multifunction Unit• Hardware Design• Experimental Results and Analysis• Conclusions
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Motivation
• Important in business applications
=0.210= 0.00110011…2
• The IEEE P754 floating-point standard– Three DFP formats: 34-digit decimal128 format,
16-digit decimal64 format (this paper), and 7-digit decimal32 format
• Decimal floating-point software is slow• Decreasing transistor costs
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Previous Research and Proposed Design
• Previous designs– Focus on fixed-point addition and subtraction
• For example, [Adiletta89], [Schmookler71]– [Thompson04] presents the first IEEE P754
compliant DFP adder• We propose an DFP multifunction unit that
– Supports eight DFP operations• add, sub, quantize, sameQuantum, roundToIntegral,
minNum, maxNum, and compare– Optimizes significand alignment– Applies decimal injection-based rounding – Uses a decimal flag-tracing mechanism
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DFP Adder and Multifunction Unit
Forward format conversion
Operand alignment
Pre-correction
Carry propagation networkPost-correction
Overflow detection Shift and round
Backward format conversion
A B
S
SA = sign of ASB = sign of BEA = exponent of AEB = exponent of BCA = significand of ACB = significand of B
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X 10EBbk-1 … b00…0
A=CA X 10EA = 0…0 ai-1 … a0 X 10EA
P digits
LA
Result X 10EB+4
LB bk-1 b40………0 b3 b2 X 10EB+4G R S
ai-1 … a0 0 0 0 0 0 X 10EA-5
Operand Alignment
• Decimal operands are not normalized
• Operand alignment calculation• E.g. LA = 5 , EA – EB = 9
B=CB X 10EB =
LB
Exponents (EA and EB) and Lengths of Leading Zero (LA and
LB)
EA < EB
LAs < |EA-EB|Left Shift CAS by (LAS-|EA-EB|)
Left Shift CAS by LAS
Right Shift CBS by min(|EA-EB|-LAS, 19)
YES
NO
NO
YES
Swap CA and CB
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Pre-correction
• Effective operation = SA⊕SB⊕OP• Place operands based on effective
operations simplifies result shifting• Inject value into the digit positions, R and
S, based on rounding modes replaces rounding by truncation.
Effective addroundTiesToAway 0 0000 xxxx xxxx xx xx
0 xxxx xxxx xxxx xx xxG R SL
15
0result 10
A
B
5 0
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Pre-correction
• Injection value
• Operands are corrected to generate correct carry-out(9, 9)AwayZeroX
(0, 0)-∞+
(9, 9)+∞-
(9, 9)-∞+
(0, 0)+∞-
(5, 0)TieToEvenX
(4, 9)TieToZeroX
(5, 0)TieToAwayX
(0, 0)TowardZeroX
Injection Value(R, S)
Rounding ModeSigninj
( )( )( )⎪⎩
⎪⎨⎧ +
=i
ii CA
CACA
2
23 '
6' If EOP = addOtherwise
If EOP = add
Otherwise( )
( )( )⎪⎩
⎪⎨⎧
=i
ii CB
CBCB
2
23 '
'
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Carry Propagation Network
• Kogge-Stone parallel prefix network
• Two sets of flags – Flag F1 handles
the digit increment in the post-correction stage.
– Flag F2 handles the carry propagation from the injection correction value.
L G R S
F2
Post-correction
OriginalKS
Network
row 5
row 4
row 3
row 2
row 1
row 0
row 9
row 8
row 7
row 6
Shift andRound Unit
19 digits
row 10
Trailing Nine Detection Network
InjectionCorrection
Block
Post-correction
(LSD)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Digit
Position
carry-out (C1)flags (F1)
sum digits (UCR)
CR1
16 digits
16 digits
carry
CR2
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Post-correction
• Compensate the result from the K-S network• Rule 1: effective operation is ADD
– Subtract 6 from digit i for which (C1)i+1 is 0• Rule 2: effective operation is SUB
– If the result is positive• Increment the result using F1
• Subtract 6 from digit i for which (C1)i+1 ⊕ (F1)i ≡ 0– If the result is negative
• Invert all bits of the result• Subtract 6 from digit i for which (C1)i+1 ≡ 1
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0 4 5 05 0 0Significand
Shift and Round
• Most significant digit is zero– No action is needed
• Most significant digit is non-zero– Requires an injection correction step
Effective addTieToEven
XReal result
0
0 5 0G R SL
Predicted result
A
B
Right shift 1 digitExponent increment
+
P = 16 digits
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Shift and Round
• Injection correction value for different rounding modes
• Injection correction value may trigger carry propagation• Flag F2 eliminates carry propagation
(9, 0, 0)AwayZeroX(0, 0, 0)-∞+(9, 0, 0)+∞-(9, 0, 0)-∞+(0, 0, 0)+∞-(4, 5, 0)TieToEvenX(4, 5, 0)TieToZeroX(4, 5, 0)TieToAwayX(0, 0, 0)TowardZeroX
Injection Correction Value(G, R, S)
Rounding ModeSigninj
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Comparison
Injection-based rounding with correction.
Random logic and decimal incrementer.
Rounding
8: add, subtract, minNum, maxNum, compare, quantize, sameQuantum, roundToIntegral
2: add, subtractSupported DFP Operations
Before the result is roundedAfter result is roundedOverflow Detection
Two extra flags for roundingKogge-Stone with flag tracing for post-correction
Carry-propagate network
Exponent computation and LZD in parallel
Exponent computation and LZD in series
Operand Alignment
Excess-3 encoding
Thompson’s Design
BCD encodingInternal format
This Design
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Extension to Support More DFP Operations
• ToIntegralValue(A)– Round A to an integer value
• ToIntegralValue(13545 x 10-3) = 14 with round-ties-to-even– Design strategy
• Set CB1 and EB1 to zero• Enable right shift even if CB1=0• Set effective operation to ADD
• Quantize (A, B)– Change EA to EB
• Quantize(12345 x 10-4, 1 x 10-2) = 123 x 10-2 with round-down– Design strategy
• Set CB1 to zero• Enable right shift even if CB1=0• Set effective operation to ADD
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Extension to Support More DFP Operations
• SameQuantum(A, B)– Check if EA ≡ EB– Generate an extra flag in the operand alignment
stage• minNum, maxNum, and compare use the
original datapath• Many changes are made to exception flag logic• A post-processing unit is added to handle
special operands such as infinity and Not-a-Number
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Block Diagram of the DFP Adder and Multifunction Unit
Overflow
Op A
Op B
ForwardFormat
Conversion
OperandAlignmentCalculation
and Swapping
Pre-correction andOperand Placement
K-SNetwork
Post-correction
Shift andRound
BackwardFormat
ConversionPost-
processing
IEEE P754Result (Z)
CA1
EB1
CB1
EA1
CASCBS
CA3
CB3
UCRCR1 CR2
BarrelShifters
CA2
CB2
C1
F1
F2
R1
RoundingMode
Operation
SA1
SB1
Sign
ER1
SR1
overflow
ER2
RSALSA
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Hardware Implementation
• Modeled using RTL Verilog and simulatedusing Modelsim
• Synthesized using LSI Logic’s 0.11um Standard Cell Library and Synopsys Design Compiler
• Tested using a comprehensive testbench generator and the decNumber library 3.32
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Delay and Area Comparison
1.6%
21.0%
Improvement
22086 NAND eq. gates22443 NAND eq. gatesArea
2.76 ns, 50.2 FO43.50 ns, 63.6 FO4Delay (comb.)
Injection-based adderThompson’s adderMetric
9.7%2.8%
Overhead
24233 NAND eq. gates22086 NAND eq. gatesArea2.84ns, 51.6 FO42.76 ns, 50.2 FO4Delay
Multifunction UnitInjection-based adderMetric
Table 1. Improvement over Thompson’s Design
Table 2. Overhead of the Multifunction Unit Compared to the Injection-based Adder
• Combinational circuit designs
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0.00
10.00
20.00
30.00
40.00
50.00
60.00
1 2 3 4 5 6
# of Stages
FO4
Cycle Times vs. Pipeline Depth
• Synthesized using the pipeline_designcommand from the Synopsys Design Compiler
0
20000
40000
60000
80000
100000
120000
1 2 3 4 5 6
# of StagesA
rea
(NA
ND
2 G
ate
eq.)
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Conclusion
• A 16-digit DFP adder and multifunction unit compliant with the IEEE P754 standard
• Novel features:– Delay optimization in the operand alignment,
rounding, and overflow detection units– A modified injection-based rounding method– Extensions to support multiple DFP operations
• Design analysis– 21% delay improvement over Thompson’s
design– 2.8% delay overhead for DFP multifunction unit
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Questions?
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Backup Slide
• More on Forward Conversion• More on Operand Alignment• More on Post-correction• More on Carry Propagation Network
• More on Overflow Detection
• More on Sign and Backward Conversion• More on Extension to Support More DFP Operations
• More on Area Comparison
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Forward Format Conversion
• Extract sign bits, biased exponents, and significands from operands in the IEEE format– Combination field G contains the classification of a number,
the encoding information, the most significant digit of significand and a biased exponent.
– Trailing significand field T encodes a significand using Densely Packed Decimal (DPD) encoding. DPD encoding represents three digits using ten bits.
• Convert significands in DPD encoding to the BCD encoding
• Generate flag signals for special operands (signaling NaN, quiet NaN, zero, and infinity)
SignS
CombinationG
Trailing SignificandT
Width (w+5) bits = 13 bits
Field
1 bitdecimal64operand
t =10J bits = 50 =3J digits=15
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Operand Alignment and Pre-correction
• Operands are shifted using one 16-digit left-shift and one 18-digit right-shift decimal barrel shifters.
• Guard and round digits, and sticky bit are generated. CB becomes a 18-digit operand with a sticky bit.
• Operands are placed based on the effective operation flag to simplify the rounding.
CA'2
CB'2
0
0
Addition
R S
CB2[71:4], 18 digitsOR{CBS[3:0], sticky}
CA2[63:0] G
0CA'2
CB'2
Subtraction
R S
CB2[71:0], 18 digitssticky
CA2[63:0]
16 digits
G
3 digits
L
L
16 digits 3 digits
19 digits
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Operand Alignment and Pre-correction
LZDLZDSignificandSwapping
CA1CB1
SUB-ABS
EA1EB1
SUB
CASCBS
SUB
Right ShiftCorrector
LSA ER1RSA
EAS
|EA1 -EB
1 |
MUX
LAS
LA1
LB1
|EA1 -EB
1 |-LAS
MUX
MUX
swap
select
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Validity of Post-correction• Add:
– At Pre-correction: Ai + Bi + 6 – If digit carry is 0, Ai + Bi + Ci-1< 10, subtract 6 from
Sumi
• Sub:– Expect: A + (10…0 - B)– At Pre-correction: A + (9…9- B) + 6…6– If carry out of MSD is 1,
• Result is positive. Add the late carry-in from the LSD.• If the digit sum after incrementing the late carry-in is less
than 10 (A + (9-B) + 6 + C < 10), subtract 6 from Sum
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Validity of Post-correction– Else
• Result is negative. Invert Sum. Sumi = 15 – (Ai +15 – Bi + Ci-1)= Bi – Ai – Ci-1
• If Bi – (Ai +Ci-1) <0 – Need to borrow from the next digit– 25>=15-[Bi – (Ai + Ci-1)]>=16 9>=Sum>=0. This generates a
carry to the next digit.– After inverting, F>=Sumi’>=6. Need to subtract 6
• Else,– No borrow from the next digit– 15>=15-[Bi – (Ai + Ci-1)]>6, No carry is generated– After inverting, 9>=Sumi’>=0. No subtraction is needed.
– E.g 135 – 424 = 135 + bdb = d10 with 011 as borrow signals. After inversion, d10 2ef. Subtract by six on two LSDs, 2ef 289
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Carry Propagation Network
• Use Kogge-Stone parallel prefix network• Three sets of flags in addition to the carry bits are generated.• Flag F1 handles the digit increment in the post-correction stage to
increment results and is generated from the propagate bits.
• Flags F2 traces the trailing nine of the result before the post-correction stage.
( ) ( )( ) ( )( ) ( )( )
( ) ( )( ) ( ) ( )( ) ( )( )( )
( ) ( ) ( )( ) ( ) ( )
⎩⎨⎧
=
∧=
∧=⎩⎨⎧
=≡
≡∧≡∨≡∧≡=
∧≡∨≡==
−
−
−−−
−−−
+
4
42
211
211
34340
110
1
1
19...5i ,15114015
9154...19
flagSUBflagADD
F
flagSUBflagSUBflagSUB
flagADDflagADDflagADD
UCRPUCRPUCR
flagSUB
CUCRUCRflagADDi
x
x
ixixix
ixixix
ii
iiii
EOP = ADDEOP = SUB
, where X = 1~4
( ) ( ) ( )( )i
ixixix
PFxPPP x
41
211 0...4 where=
=∧= −−−
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Overflow Detection
• Injection-based rounding simplifies the overflow detection– The result is overflow before rounding (carry-
out is generated from the most significant digit of the result)
• Not influenced by the injection correction value– The result is overflow after rounding
• Handle by the injected value– Overflow detection can examine the result
before the rounding unit
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Sign and Backward Conversion
• Sign bit is determined by the signs of operands, the rounding mode, and if either of the operands is normal numbers.– Sign = (!EOP ∩ SignA) ∪ (EOP ∩ ((EA≥EB) ⊕
SignA ⊕ carryout)• Backward conversion combines the sign
bit, the exponent, and the significand to form the P754 compliant result.
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Extension to Support More DFP Operations
• Quantize (A, B)– Change the unit of A to EB– Set CB to zero– Enable right shift even if CB=0– Set effective operation to ADD to avoid wrong rounding operations
• SameQuantum(A, B)– Check if EA ≡ EB– Generate an extra flag in the operand alignment stage.
• MinNum, MaxNum, and Compare– Set the operator to SUB and observe the sign
• ToIntegralValue(A)– Round A to an integer value– Set CB and EB to zero– Enable right shift even if CB=0– Set effective operation to ADD to avoid wrong rounding operations
• Many changes to the conditions of exception flags are added. The post-processing unit is added to handle special operands such as infinity and Not-a-Number.
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Area Comparison
0.0
2000.0
4000.0
6000.0
8000.0
10000.0
12000.0
14000.0
16000.0
Barrel
Shif
ter (L
eft)
Barrel
Shif
ter (R
ight)
Forw
ard F
ormat
Conve
rsion
Effecti
ve O
perat
ion
Backw
ard F
ormat
Conve
rsion
Kogge
Ston
e Netw
ork
OACSU
Opera
nd Pr
e-corr
ectio
nPo
st-co
rrecti
onPo
st-Pr
oces
sing
Shift
and R
ound
Sign
Zero D
etecti
on
Spec
ial O
perat
ion H
andle
rOthe
r Log
ic
Are
a (N
AN
D E
quiv
alen
t Uni
ts) Thompson's Adder [14]
Adder w ith Inj-based Rounding
Multifunction w ith Inj-based Rounding
![Page 33: Decimal Floating-Point Adder and Multifunction Unit with ... · Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding Liang-Kai Wang and Michael J. Schulte](https://reader033.vdocuments.mx/reader033/viewer/2022051813/60339acd2a7af4074e4784f3/html5/thumbnails/33.jpg)
33
Comparison with Software (IBM’s decNumber library)
11
64
47.1
107.2
67.6
60.8
89.4
44.2
82.7
83.2
SlowFastSlowFast
64
Hardware
70.7282.8Compare
160.8643.1MinNum
101.4405.4MaxNum
91.2364.6ToIntegralValue
89.489.4SameQuantum
66.4265.4Quantize
124.1496.2SUB
124.9499.4ADD
ImprovementSoftware
DFP Operations
• decNumber library using the SimpleScalar simulator with PISA architecture
![Page 34: Decimal Floating-Point Adder and Multifunction Unit with ... · Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding Liang-Kai Wang and Michael J. Schulte](https://reader033.vdocuments.mx/reader033/viewer/2022051813/60339acd2a7af4074e4784f3/html5/thumbnails/34.jpg)
34
Comparison with Software (Intel’s BID library)
108
113
45
45
133
133
SlowFast
64
11.5
12.5
4.5
4.5
11.8
11.8
MinMaxSlowFast
64
Hardware
2769MinNum*
28.375MaxNum*
11.327ToIntegralValue
11.327Quantize
33.371SUB
33.371ADD
ImprovementSoftwareDFP Operations
• Intel’s BID library and EM64t Xeon 5100 3.0GHz• Results taken from their paper
![Page 35: Decimal Floating-Point Adder and Multifunction Unit with ... · Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding Liang-Kai Wang and Michael J. Schulte](https://reader033.vdocuments.mx/reader033/viewer/2022051813/60339acd2a7af4074e4784f3/html5/thumbnails/35.jpg)
35
Other DFP Operations
• Other DFP operations that can reuse our DFP adders include:– nextUp– nextDown
• Other DFP operations that can use our DFP with little extra gate– ABS– Negate– copySign
![Page 36: Decimal Floating-Point Adder and Multifunction Unit with ... · Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding Liang-Kai Wang and Michael J. Schulte](https://reader033.vdocuments.mx/reader033/viewer/2022051813/60339acd2a7af4074e4784f3/html5/thumbnails/36.jpg)
36
Delay Comparison
00.2
0.40.60.8
1
1.21.4
IEEE to BCD Fo
rmat
Conve
rsion
Unit
OACSU
Barrel
Shifter
Righ
t
Operan
d Pre-
corre
ction
Unit
Kogge
Stone N
etwork
Unit
Post-c
orrec
tion U
nit
Shift a
nd R
ound
Unit
BCD to IE
EE Form
at Con
versi
on U
nit
Post-P
roces
sing U
nit
Del
ay (n
s)
Thompson's Adder [14]
Adder with Inj-based Rounding