david malaspinafields i-pdr – dfb solar probe plus fields instrument pdr digital fields board...

David Malaspina 1FIELDS I-PDR – DFB

Solar Probe Plus FIELDSInstrument PDR

Digital Fields Board

David Malaspina

CU/LASP

[email protected]


DFB Agenda

• Science Objectives• Performance and Driving Requirements • DFB Block Diagram• Electrical Diagram / Layout• Interfaces • DFB Processing• Development Status• Resources• Backup Information

– L3 Requirements– Data Product Details– Heritage– QA, Parts, Materials, Safety– BOM– Schedule– Risks– Action Items


DFB High-Level Tasks

The Digital Fields Board on Solar Probe Plus:

1) Accepts signals from 5 electric field sensors, 4 search coil magnetic field sensors2) Performs analog processing, digitization, and digital processing of:

Voltage signals (antenna-to-spacecraft ground)DC-coupled, AC-coupled

Electric field signals (antenna-to-antenna)DC-coupled (High-gain, Low-gain), AC-coupled

Magnetic field signals (> 10 Hz)Low-frequency coil signals (High-gain and Low-gain)Medium-frequency coil signals

3) Generates time domain and spectral domain data products, transmit them to the digital control board (DCB)4) Provides calibration signals for search coil magnetometer


Electric Field Science Drivers

Electric Fieldsof Scientific Interest+DFB Frequency Coverage


Magnetic Field Science Drivers

Magnetic Fieldsof Scientific Interest+DFB Frequency Coverage


DFB Design Drivers

Solar Probe Plus• Science Challenges

– Unknown / highly variable plasma environment – signal strengths are not well established. Requires large dynamic range.

• DFB has programmable gain states• DFB uses low-noise operational amplifiers• DFB has flexible configurations

– Low telemetry volume. Requires on-board pre-selection of highest-rate data• DFB has burst memory• DFB has waveform compression• DFB has flexible data rates

• Engineering Challenges– Low power and mass allocation

• DFB uses a Teledyne SIDECAR for A/D conversion– High temperature environment

• Requires testing and characterization at expected temperatures


DFB Block Diagram


DFB ETU #1 PWB Layout

David Malaspina FIELDS I-PDR – DFB

DFB FPGA DIAGRAM


DFB Interface Documents

• Electrical – SPF_MEP_102_DFB_ICD_REV4– SPP_SCM-REC-10000-SP-0081-LPC2E v1-2– SPF_MEP_110_Connectors_REVA

• Command & Data– SPF_MEP_100_CDI_ICD_REV5

• Mechanical – MICD SPP-MEP-MEC- TBD

• SPF-MEP-MEC-004 Rev01 MEP Daughter Board• SPF-MEP-MEC-005 RevC MEP PCB Outline• SPF-MEP-MEC-006 Rev01 DB Standoff• SPF-MEP-MEC-010 Rev01 DB Insert• SPF-MEP-MEC-011 Rev01 DB Push Stop• MAV-IDP-MEC-009 RevC PCB Insert


Analog DFB Processing

High level block diagram goes hereShow schematic analog processing, digital processing


Digital DFB Processing


DFB Development Status

Prototype DFB

ETU #1

Xilinx FPGA DB

ETU #2Flatsat

SIDECAR Evaluation Board

Flight DFB

ETUs and Flight DFBs can accommodate all variations of FPGA DB: Xilinx, ProASIC, ProtoRTAX, Flt RTAX

FPGA DB


DFB Resources

• Mass– CBE 444 grams, NTE 524 grams

• Power– CBE 2.2 W, NTE 2.53 W

• Volume – 9.2” x 6.2” x 0.713” per SPF-MEP-MEC-005

• Telemetry to DCB– Survey Data Volume ≈ 15,750 bits/s– Spectral Data Volume ≈ 4,583 bits/s– Burst Data Volume ≈ 60,480 bits/s


DFB BU Data

Backup Information


Level-3 Requirements (Time Domain)

Time domain(L3 DFB req.)

E-DC E-AC SCM-LF SCM-MF

# Components 3 3 3 1

Frequency Range

DC – 7.5 kHz 100 Hz – 60 kHz

10 Hz – 50 kHz

1 kHz – 60 kHz

Amplitude Range

+/- 10 V/m @ DC

+/- 5 V/m@ 20 kHz

up to 3000 nT @ 3.5 kHz

up to 6 nT(@ 60 kHz)

Resolution 300 μV/m (+/- 10 V/m)30 μV/m (+/- 1 V/m)@ DC (TBR)

160 μV/m@ 20 kHz

1 pT/√(Hz)@ 100 Hz0.1 pT/√(Hz)@ 3.5 kHz

0.1 pT/√(Hz)@ 10 kHz


Level-3 Requirements (Frequency Domain)

Freq. domain(L3 DFB req.)

E-DC E-AC SCM-LF SCM-MF

Frequency Range

5 Hz – 7.5 kHz 100 Hz – 60 kHz

10 Hz – 50 kHz

1 kHz – 60 kHz

Cadence 1 spectrum / sec (max)

1 spectrum / sec (max)




Cycle Definition

All power supplies on SPP synchronized at 150 kHz + N x 50 kHz From EMC plan

150 kS/s DFB sampling is phase-locked with power switching for lowest noise

But, digital processing is most efficient on data in powers of 2150,000 is not a power of 2, closest is 2^17 = 131,072

Define a ‘cycle’ as 131,072 samplesTime of one ‘cycle’ is 131,072 / 150,000 = 0.8738133...

seconds

Defining samples per cycle (S/c) instead of samples per second (S/s)

DFB digital operations will be synchronized to a PPC (pulse per cycle)delivered by the DCB (digital control board)


DFB Data Products (Time Domain)

Time domainSurvey

Waveforms

V E SCM

SourceSignals

V1DC, V2DC, V3DC, V4DC, V5DC, <VDC>

E12DC (Lo, Hi)E34DC (Lo, Hi)EzDC (Lo, Hi)

SCMxLF (Lo,Hi)SCMyLF (Lo,Hi)SCMzLF (Lo,Hi)

Range +/- 115 V +/- 15 V/m (Lo)+/- 1.5 V/m (Hi)(w/ 2 m baseline)

+/- 8 V (Lo)+/- 0.53 V (Hi)

Resolution 3.5 mV 0.46 mV/m (Lo) 46 μV/m (Hi)(w/ 2 m baseline)

94 pT (Lo) 6 pT (Hi)

Sample rate 1 – 16,384 S/c 1 – 16,384 S/c 1 – 16,384 S/c

Coverage Continuous @ 256 S/c

Continuous @ 256 S/c

Continuous @ 256 S/c


DFB Data Products (Time Domain)

Time domainBurst Waveforms

V E SCM

SourceSignals

V1AC, V2AC, V3AC, V4AC, V5AC, <VAC>

E12AC E34AC EzAC

SCMxLF (Lo,Hi)SCMyLF (Lo,Hi)SCMzLF (Lo,Hi)SCMxMF

Range +/- 10 V +/- 2.5 V/m (w/ 2 m baseline)

+/- 8 V (Lo)+/- 0.53 V (Hi, MF)

Resolution 0.35 mV 76 μV/m(w/ 2 m baseline)

94 pT (Lo) 6 pT (Hi)12 fT (MF)

Sample rate 4096 – 131,072 S/c 4096 – 131,072 S/c 4096 – 131,072 S/c

Coverage ~4 second selected bursts @ 131,072 S/c

~4 second selected bursts @ 131,072 S/c

~4 second selected bursts @ 131,072 S/c


DFB Data Products (Frequency Domain)

Frequency domain

DC

Power Spectra1024-pt

Hanning Window

Cross Spectra1024-pt

Hanning Window

Triggers

SourceSignals

VDC, EDC, SCM-LF VDC, EDC, SCM-LF VDC, EDC, SCM-LF

Frequency Range

~(10 - 4687) Hz ~(10 - 4687) Hz ~(0.23 - 7500) Hz

Frequency Resolution

~8% df/f (56 bins)~4% df/f (96 bins)

~8% df/f (56 bins)~4% df/f (96 bins)

(3750-7500 Hz) / 2^N

Reporting rate (1/8 – 128) Results/c (1/8 – 128) Results/c (1/256 – 16) Results/c

Coverage Continuous Continuous Continuous


DFB Science Objectives and Heritage

Region of Study

# of Units

Waveform Functions Waves / Frequency Range

Comment

THEMIS Earth’s Magneto-sphere

5 E and B (SCM) surveyE and B burst (6 kHz)Field-aligned E (de-rotating)

Spectra – 2 BandsBroadband Filters

6 kHz

One channel measured power to 500 kHz.

Van AllenProbes (RBSP)

Earth’s Radiation Belt

2 E and B surveyE and B burst 1 (800 Hz)E and B burst 2 (6 kHz)Field-aligned E (de-rotating)

Spectra – 2 BandsCross spectraBroadband Filters6 kHz

DCB created data packets.

MAVEN Mars Iono-sphere

1 Langmuir probeE surveyE burst memory (2 MHz)Waveform compression

Spectra – 3 BandsActive sounding2 MHz

One E channel. Two antennas.

MMS Earth’s Magneto-sphere

4 + 4 E and B surveyE and B burst (100 kHz)E/B burst memory (100 kHz)Waveform compression

Spectra – 2 BandsBroadband Filters

100 kHz

Cold spare on each S/C.

• Seven units on orbit giving 39 unit–years of problem-free operation.• No upsets or anomalies have been seen on any of the in-flight units.


LASP Product Assurance

• Will follow LASP’s Quality Management System Plan and the SPP SMA Requirements and Compliance Matrix

• QA and project team have experience on multiple flight programs

• LASP’s standard build processes to be followed• Assembly and inspection personnel certified to NASA

workmanship standards• Hardware inspection processes in place

– MIPs to be performed by APL/SSL as required per SMA Matrix– LASP QA to inspect at vendor facilities if necessary

• Will follow LASP’s standard practices for contamination control

• LASP Alert and Advisory Procedure to be followed for GIDEP– GIDEP Representative in place

• Personnel trained and certified to LASP’s ESD Control Procedure– ESD Control program designed per ANSI/ESD S20.20– Access to labs denied without ESD certification


EEE Parts/PWB, Materials & Processes, and System Safety

• DFB will comply with parts control and materials & processes requirements per the SMA Requirements and Compliance Matrix– LASP EEE Parts Engineer will work with the UCB/SSL and JHU/APL Parts Control

Board to assure that all parts and PWBs have approved for use• Parts will be procured, and derated, to EEE-INST-002, Level 2 or better• Will facilitate delivery of: PEPL, ADPL, and ABPL • All PWB coupons shall be provided for test/approval at GSFC

– LASP Materials Engineer will work with the UCB/SSL and JHU/APL MPCB to assure that all materials and processes are approved for use

• Evaluated in accordance with program requirements• Will facilitate delivery of: MIL, ADMPL, and ABMPL

• DFB will support JHU/APL Mission System Safety Program Plan– Assist with Safety Requirements Compliance Checklist, OHA, Hazard Tracking Log– Initial Hazard Assessment revealed no applicable hazards

• No N2 purge or high-pressure devices

• No high voltage• No hazardous materials, flammable or explosives materials, or radiation sources • In the event, exceptions will be noted through safety waivers/deviations


DFB BOM

# Flight Part Number Manufacturer Generic PN Description Status Anticipated Upscreening LASP Comment

1 OP262GS Analog Devices OP262 IC OPAMP GP R-R 15MHZ DUAL 8SOIC Screen/Qual/Radiation

2 5962R1222201VXC Intersil ISL70218IC, LINEAR, DUAL, PRECISION, OPERATIONAL AMPLIFIER,

MONOLITHIC SILICONApproved -- Request early procurement (min buy)

3AD648SQ/883;

5962-9753501VPAAnalog Devices AD648 DUAL PRECISION, LOW POWER BIFET OP AMP --

4 JANTXV1N6642US Microsemi 1N6642 DIODE SWITCH 100V 0.15A SOD123 Approved --

5 5962F0821501VXC Honeywell HXS6408AVH SRAM, 512K X 8-BIT, 15 NS ACCESS TIME, LOW VOLTAGE -- Request Approval priority and early procurement (min buy)

6 5962R0323601VXC Aeroflex UT8R128K32-15WCA 128K x 32 SRAM -- Request Approval priority and early procurement (min buy)

7 5962R0820101VZA Analog Devices AD768S IC DAC 16BIT 30MSPS 28-SOIC -- Request Approval priority and early procurement (min buy)

8 5962F0253201VXA ST Micro RHFL7913KPA-01V NEG LDO REGULATOR From GSFC Request Approval priority and early procurement (long lead and min buy)

9 3DSD512M16VS1605IS 3D-Plus 3DSD512M16VS1605IS SDRAM 32Mx16-SOP Datapack, DPA Request Approval priority and early procurement (long lead)

10 SIDECAR ASIC Teledyne SIDECAR ASIC SIDECAR ASIC -- S/B approved already

11 RH1021CMW-5/CMH-5 Linear Tech RH1021 PRECISION 5V REFERENCE Datapack, DPA Request Approval priority and early procurement (long lead and min buy)

12 JANSR2N2222AUB Microsemi 2N2222 NPN SILICON SWITCHING TRANSISTOR Approved PIND

13 HDLP11090SMDOA0P0 Hypertronics HDLP11090SMDOA0P0 HIGH DENSITY LOW PROFILE CONNECTOR, MALE -- Request Approval priority and early procurement (long lead and min buy)

14 HDLP11090SFDLA0P0 Hypertronics HDLP11090SFDLA0P0 HIGH DENSITY LOW PROFILE CONNECTOR, FEMALE -- Request Approval priority and early procurement (long lead and min buy)

15 HDLP11090SFCLANP0 Hypertronics

HypertacHDLP11090SFCLANP0

CONN, RECTANGULAR, 90 CONTACT, HIGH DENSITY, FEMALE, LOW HEIGHT VERTICAL, WITH GUIDE PINS

-- Request Approval priority and early procurement (long lead and min buy)

16 HDLP11090SMCOANP0Hypertronics

HypertacHDLP11090SMCOANP0

CONN, RECTANGULAR, 90 CONTACT, HIGH DENSITY, MALE, LOW HEIGHT VERTICAL, WITH GUIDE PINS

-- Request Approval priority and early procurement (long lead and min buy)

17 311P407-2P-B-12 Positronic SDD26M0000G-1082.24 CONNECTOR, 26 PIN HIGH DENSITY, D-SUB, SOLDER CUP, MALE Approved --

18 MWDM2L-15P-6J5-18B Glenair MWDM2L-15P-6J5-18B CONNECTOR, D-SUB, MICRO-D --

19 311P407-1P-B-12 Positronic SDD15M0000G-1082.24 CONNECTOR, 15 PIN HIGH DENSITY, D-SUB, SOLDER CUP, MALE Approved --

20 311P409-2P-B-12 Positronic SNDM0000G-1082.24 CONNECTOR, 15 PIN MALE Approved --

21 MWDM2L-9S-6J5-18B Glenair MWDM2L-9S-6J5-18B CONNECTOR, D-SUB, MICRO-D --

22 G08P1 Positronic MC8022D-50-1202.4PLUGS, CRIMP, NON-MAGNETIC, SERIES 90, HIGH DENSITY

CONNECTORS Approved --

23 G10P1 Positronic MC6020D-50-1202.4PLUGS, CRIMP, NON-MAGNETIC, SERIES 90, HIGH DENSITY

CONNECTORS Approved --

24 311P829A Capacitors Presidio 311P829 Capacitors 311P829 CAPACITORS Approved --

25 SR1825NPO822F250VNT95 Presidio SR1825NPO822F250VNT95 8.2nF, 1%, 250V, 90/10 Sn/Pb OVER Ni, WAFFLE PACK --

26 MSK5978VRHG MS Kennedy MSK5978RHVOLTAGE REGULATOR, LDO, ADJUSTABLE, 700mA, RAD HARD, CFP-

10 Precap/PIND Request Approval priority and early procurement (long leand and min buy)

27 5962F8762401VXA ST Micro RHFAC14K02V IC HEX INVERTER SCHMITT TRIGGER CMOS, CFP-14 PIND

28 M834446/39-272J-30F API Delevan MIL1812 (M83446) RF INDUCTOR Thermal shock/burn-in Request Approval priority and early procurement (long leand and min buy)

29 M27/367-13L-21 API Delevan MIL4922 (MIL-PRF-27/367) POWER INDUCTOR Thermal shock/burn-in Request Approval priority and early procurement (long leand and min buy)

30 400102302xxxxL9 ESA Resistors Vishay PHR0805CxxxxLB/CRCW0805xxxxFKEA ESA RESISTORS -- Request Approval priority and early procurement (long leand and min buy)

39 400102303xxxxL9 ESA Resistors Vishay PHR1206CxxxxLB/CRCW120xxxxFKEA ESA RESISTORS -- Request Approval priority and early procurement (long leand and min buy)

40 M55681 Capacitors QPL Product level S M55681 CAPACITORS Approved --

41 M55365 Capacitors QPL Product level C M55365 CAPACITORS Approved --

42 M55342 Resistors QPL Product level R M55342 RESISTORS Approved --

43 JANSR2N2907AUB Microsemi 2N2907 TRANSISTOR, PNP PIND

44 CWR19CC227KCHB QPL CWR19CC227KCHB CAPACITOR, TANTALUM --

45 5962-08224 Actel RTAX4000SL-1CG1272B FPGA, 4000 gate array --

46 5962R9560403VXA National Semi LM6172AMGWRLQV OP AMP, DUAL, HIGH-SPEED, LOW-POWER --


DFB Schedule

• Critical path is thru ETU• Reserve held @

1mnth/year • Schedule threat is PWB

Deflection and component integrity

• Risk mitigation is Vibe TestETU1

ETU2


Like

lihoo

d of

Occ

urre

nce

(pro

babi

lity)

Consequence of Occurrence (Impact)

5

4

3

2

1

1 2 3 4 5

High Medium Low (Criticality)P = PerformanceC = CostS = ScheduleM = Mass

ID TITLE P I Crit Retire At

F-DFB01 SIDECAR workmanship 2 3L

Post PDR characterization testing

F-DFB01PM

If the SIDECAR experiences latent failure and/or has reliability issues, then the lack of a complete EIDP and respective workmanship could hinder the debug/troubleshooting, and have the potential to degrade performance and warrant possible redesign which could increase needed mass and power. Risk mitigation plan is to perform characterization and environmental testing on SIDECARs. These parts have prior electrical burn-in testing hence characterization and environmental tests will demonstrate good rigor to retire the risk.

Risk rating: Probability 2, Impact 3; not likely to occur based on successful burn-in testing completed by GSFC/Teledyne; consequences slightly higher based on possibility of reverting to backup plan of discrete ADCs. Proposed/heritage ADCs are not as rad-tolerant, require more board space (mass increases), more power, and/or could drive science return. Newer, more viable, ADCs identified but require radiation testing.

DFB SIDECAR Qualification Workmanship Risk


Like

lihoo

d of

Occ

urre

nce

(pro

babi

lity)

Consequence of Occurrence (Impact)

5

4

3

2

1

1 2 3 4 5

High Medium Low (Criticality)P = PerformanceC = CostS = ScheduleM = Mass

F-DFB02PMSC

If the DFB PWBA experiences too high of structural deflection, then the assembled components may experience package stresses, with respective workmanship and/or reliability issues. The primary concern is the SIDECAR CGAs. This potential could warrant possible redesign of the PWB layout, structural stiffness design, or reduction in DFB capability due to replacing the SIDECAR/other components to stay within mass and power constraints. Analysis and part modeling in process now. Risk mitigation plan is to perform vibration testing to SPF-MEP vibration levels on an ETU PWB with representative components and mass models. Analysis and modeling, along with vibration testing, must prove the PWBA design and demonstrate good rigor to retire the riskRisk rating: Probability 2, Impact 4; not likely to occur based on analysis and modeling and

good design practices of the PWBA. Consequences higher based on possibility of impact at a PDR level which may require redesign and/or reverting to backup plan of discrete ADCs. Analysis completing, vibe test post PDR.

DFB PWBA Structural Risk

ID TITLE P I Crit Retire AtF-

DFB02 PWB Structural Deflection 2 4M Post PDR vibration testing


DFB Related Action Items

No Title Detail Status

SCM-15 Calibration Frequencies Cal freq plan agreed to by Fields team SCM IC to be updated

SCM-17 Calibration Signal Cleanliness

Signal range requirements needed to be worked w/I Fields team

SCM team evaluating

DFB-01 Analog Amplitude Near Rails

Consider an indicator flag on SIDECAR if input is near a rail

New from DFB review

DFB-02 System Clk termination Add pull-down resistor on 19.2MHz – in ICD

New from DFB review

DFB-03 Filtering on LF Channels

Consider changing to 2-pole filters on LF channels

New from DFB review

DFB-04 Periodically re-sync SIDECAR

Consider Re-syncing SIDECAR ADC sampling to FPGA

New from DFB review

DFB-05 CCSDS Packet Checksum

Reconsider using checksums on CCSDS packets

New from DFB review

DFB-06 Signal Integrity on FPGA DB

Consider adding more grounding on FPGA DB

New from DFB review

DFB Peer Review held Nov 4-5th, materials available on SPF siteAction Items from this and other Peer reviews included here (SCM Peer Review Sept 4-5, 2013)

david malaspinafields i-pdr – dfb solar probe plus fields instrument pdr digital fields board...

Documents

pdr dfbdfb etu

pdr dfbdfb resourcesmasscbe

pdr dfbdfb block diagram

revc mep pcb outlinespfmep

pdr dfbmodule status

rev01 db standoffspfmep

rev01 db insertspfmep

mec tbdspf