d. m. monticelli, “a quad cmos single-supply op amp with rail-to

1026 IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-21, NO. 6, DECEMBER1986

A Quad CMOS Single-Supply Op Amp withRail-to-Rail Output Swing

DENNIS M. MONTICELLO

.&tract —The realization of a commercially viable, general-purposequad CMOS amplifier will be presented along with discussions of thetrade-offs involved in such a design. The amplifierfeatures an output swingthat extends to either supply rail. Together witfs an input common-moderange that includes ground, the device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over atemperature range of – 55 to + 12S”C. Unlike earlier designs thatsacrificed performance in the areas of input offset voltage, offset voltagedrift, input noise voltage, voltage gain, and load driving capability, thisimplementation offers performancethat equals or exceeds that of populargeneraf-purpose quads of bipolar or B1-FET’ construction. On a 5-Vsupply the typicaf VO,is 1 mV, VO,drift is 1.3 pV/OC, l-kHz noise is 36nV/~Hz, and gain is one million into a 600-Q load. This device achievesits performance through both circuit design and layout techniques a$opposed to special analog CMOS processing, thus lending itself to use onsystem chips built with the latest digital CMOS technology.

I. INTRODUCTION

A LTHOUGH special-purpose CMOS amplifiers arean accepted part of mixed analog/digital chips where

their ability to be integrated outweighs their existing weak-nesses, penetration into stand-alone applications has beenlimited to niches such as low voltage, low power, andchopper stabilization. Unfortunately, shortcomings in theinput stage relating to input offset voltage, drift and noise,shortcomings in the output stage in driving realistic loads,and latch-up sensitivity have prevented CMOS from mak-ing a strong contribution to the mainstream amplifierarena. This paper will describe a new CMOS amplifierdesign with overall performance on a + 5-V supply that isequal to or better than most commercially available bi-polar, BI-FET, or CMOS quad amplifiers. It is significantthat this has been achieved on a conventional 4-pm, dou-ble-polysilicon, P-well process optimized for digital chips.This ability to share a common process with advanceddigital CMOS circuits has important ramifications in real-izing the large mixed analog/digital chips of the futurethat are the dream of the system designer.

II. AMPLIFIERTOPOLOGY

The amplifier topology chosen (Fig. 1) departs some-what from the convention for general-purpose operationalamplifiers in that the traditional unity-gain buffer is absent

Manuscript received April 19, 1986; revised July 11, 1986.The author is with Nationaf Semiconductor Corporation, Santa Clara,

CA 95051.IEEE Log Number 8610607.1BI-FET is a trademark of Nationaf Semiconductor Corporation.

~ + 109m~ -

- CFF z CF

Fig. 1. Circuit topology of the amplifier.

and the output is taken instead directly from the output ofthe integrator. Designing the buffer would not have beenstraightforward due to requirements for a stable stage witha gain of between one and two and an output that swingsrail to rail. This remains a viable approach. However,eliminating the buffer has the advantage of simplicity andpotential power savings, but places greater demands uponthe integrator to deliver power, high gain, and rail-to-railswing, to withstand shorts to either rail, and to remainstable in the presence of a wide range of loads. As a resultof these demands, the integrator is a compound affair withan embedded gain stage that is doubly fed forward (via CFand C~F) by a dedicated unity-gain compensation driver.In addition, the output portion of the integrator is a robustpush–pull configuration. While sinking current the wholeamplifier path consists of three gain stages with one stagefed forward, whereas while sourcing the path contains fourgain stages with two fed forward.

III. THE INPUTSTAGE

The input stage (Fig. 2) is a conventional configurationthat has been very carefully optimized for best perfor-mance. The physical layout of this circuit block has asmuch to do with good performance as does the actualcircuit design. The most critical elements are the inputdevices Ml and M2, and considerable thought went intotheir choice, geometry, and placement on the die.

Noise measurements on test structures revealed that theNative p-channels (VT = – 1.5 V) were the quietest of thefour MOSFET types available on the process. The secondquietest device is the Native n-channel (VT= 0.7 V) fol-lowed in order by the implant adjusted p-channel (VT=

0018 -9200/86/1200-1026$01 .00 01986 IEEE

Authorized licensed use limited to: Iowa State University. Downloaded on November 24, 2008 at 00:26 from IEEE Xplore. Restrictions apply.

MONTICELLO: QUAD CMOS OP AMP WITH RAIL-TO-RAIL OUTPUT SWING 1027

V+

yf-J

v+ M21 20 BIAS

1

v+

+fm~+

20tiA~ 70Q13 13

(-)m M2

gm = lo5#u I

= =I

(+)

M3@+47jM5

———

=

l~ig. 2. Input stage with common-mode range that includes ground.

--0.7 ~ and the implant adjusted n-channel (VT= 1.0 V).ThN is in general agreement with the findings of otherdesigners and researchers. It appears that the hole-baseddevices are indeed quieter than the electron-based devices,but that the overriding factor is whether or not the devicereceives a threshold adjusting implant.

In order to insure that the input devices dominate theperformance of the input stage, they were designed to havea t mnsconductance (105 pmho) that was three times thatof the mirror transistors, Native n-channel devices M3 andM4. That ratio, coupled with the fact that the n-channelshave a higher transconductance for equivalent geometryrelative to the p-channels, results in the latter having amuch higher W/L (700/13) than the mirror devices ( JV/L= 120/40).

The input devices constitute an unusual structure (Fig.3) that is assembled from a regular array of 16 dcmghnut-shaped gate regions that are patterned out of a largesquare of p + source/drain implant. This background ofp+ represents the common-source connection of the pairancl the interior circles represent the interconnected drainregions. The doughnut structure has minimal associateddrain capacitance which helps minimize detrimental phaselag through the mirror. The relatively higher source capaci-tance manifests primarily as asymmetrical slew behavior.Calculation of the effective width of the doughnut channelregion is not straightforward. The width of a single tran-sistor cell as determined by the laterally diffused cir-cumference of the drain region is 80 pm, and as de-termined by the laterally diffused circumference of thesource circle it is 152 pm. Determination of the net effec-tive width of the structure via transconductance measure-ments put the value at 87 pm, indicating that the effectivewidlth of circumference is located much closer to the drainthan to the source. This appears logical from the stand-point that the channel near the drain has the highestcurrent density and thus can be expected to dominate thetransconductance. The drawn gate area is 1511 pm2 perdoughnut and eight times that or 12088 pm2 for Ml orM2.

The mirror devices M3 and M4 consist of a cross-cou-pled quad of conventional rectangular construction. Their

relatively long channels maximize first-stage gain, mini-mize output impedance related mismatch error, and set thedesired low transconductance of the mirror. The drawngate area is 4800 pm2 per transistor.

In order to achieve the best possible V(OJperformance,the use of common-centroid cross-coupling techniques ismandatory for effective rejection of processing gradients.The layout should strive to achieve the highest possiblenumber of cross-coupled elements per unit area consistentwith good definition of features and practical interconnect.Nowhere was this carried out to a higher degree than inMl and M2 where the 16 doughnuts are packed into acommon square of p + and interconnected in a checker-board pattern. The space between the individual dough-nuts was efficiently used to connect the poly gates to thesecond poly which in turn provided the cross-coupledinterconnect. Metal was used to cross couple the drains.The web of source material that threads through the struc-ture results in higher source resistance for the interiordevices than the outer devices. This means that the connec-tion to the common-source region cannot be freely chosenif systematic offsets are to be avoided. A complex matrixof some 50 resistive elements was created and computeranalyzed to study ,the p + pick-up problem. The two-sidedpick-up shown in Fig. 3 is one of several schemes that wasfound to be successful in the study.

Package-induced stress during die attach and molding isa known enemy of the precision match of surface deviceslike JFET’s, MOSFET’S, resistors, and to a lesser degree,BJT’s. For this reason, the entire input stage is arranged tolie symmetrically about the die centerlines of minimumstress (Fig. 4). The output stage power devices are locateddirectly above the input devices and are also on thecenterline for isothermal reasons. The rejection of thermalwaves from the other cells on the chip is left to the highdegree of cross coupling.

From a circuit point of view the input stage is also wellbalanced. The second-stage transistor M5 is biased suchthat its V& is equal to that of M3 which eliminates thepotential Vo. error term that would have occurred if Mland i142had been allowed to have unequal drain-to-sourcevoltages. When the needs of small-signal bandwidth, slew,common-mode range, voltage gain, and noise are com-bined, the input devices end up being biased into theirquasi-subthreshold region which lies somewhere betweensquare-law and exponential behavior. This is not at alla poor region in which to be operating. The V& matchis better than the square-law region and the current densityis not as low as in the subthreshold region where high-temperature operation is risked to leakage and ac perform-ance suffers from an abundance of capacitance and alack of current. At first it may appear that second-stagetransistor Q23 (see Fig. 7) will load the input stage withbase current, thus introducing a systematic offset and adrift component. This does not occur to any significantdegree, however, due to the high beta (typically 900) ofthe substrate n-p-n and the temperature coefficient ofits quiescent current. The excellent V& performance



DIECENTERLINE—

—— —

M1; M2

Fig. 3. Geometries of cross-coupled input transistors Ml and M2 and cross-coucenterline of minimum package-induced stress passes through tl

M3;M4

Ipledmirror transistors M3 and M4. Thele center of these criticaf devices.

BIAS

OUT

CF

CFF

- iN + iN cc Ma m; M2 k, M4 !i9

Fig. 4. Photomicrograph of 75X 75-roil (3.63-mm2) die. Each amplifierinput stage is located afong the die centerline of minimum stress andsymmetrically placed behind the thermaJ sources of the output stage.The capacitors are poly to poly with an overcoat of metaf.

(Fig. 5(a)) of the amplifier is better than existing CMOSofferings and compares favorably with the raw offsets ofbipolar and BI-FET quads. After die attach and encapsu-lation in plastic, the offset distribution undergoes minimaldegradation. The J’&drift performance (Fig. 5(b)) is like-wise excellent and again compares very favorably withother general-purpose untrimmed quads. Note the absenceof any telltale “hook” in the high-temperature end of thedrift curve that would be indicative of an input stageleakage problem.

The voltage gain of the input stage is quite high, typi-cally 54 dB, which easily swamps the noise of the secondstage and significantly contributes to the high gain of the

Vos (mV)

(a)

I 1 I I I I 1 I

+ 200

+100

s3: 0~

-100

-200t

iI I 1 1 1 1 1 I (

-50 -25 0 25 50 75 100 125TEMPERATURE (°C)

(b)

Fig. 5. (a) The distribution of VO, on a typicaf wafer as measured atwafer-sort for all functional op-arnp cells on the wafer taken as a group.The mean VO$is – 0.04 mV and the sigma is 1.37 mV. (b) The Vo, driftversus temperature for three representative op-arnp cells.


MONTICELL1: QUAD CMOSOP AMP WITH RAIL-TO-RAIL OUTPUT SWING 1029

I I I I

IOHZ 100Hz 1kHz 10kHz

FREQUENCY

(a)

0,0, ~o 25 50 75 100 125 150

TEMPERATURE (°C)

(b)

Fig. 6. (a) Input-referred voltage noise density versus frequency. (b)Input bias current versus temperature for each input.

overall amplifier. This high gain is achieved because thesecond-stag eloadin gisverylight, themirror hasveryhiglhoutput impedance, and the input devices are operatingquasi-subthreshold.

For true single-supply operation the input-stage com-mon-mode range must include ground. Two effects com-bine to achieve this. One is the higher V~(l.5 V) of theNative input devices and the other is the unavoidable bodyeffect of those same devices which are built in the sub-strate. Although the body effect is desirable in that itincreases the V&, the mismatch of the body effects of Mland M2 will determine to a large extent the maximumachievable CMRR and positive PSRR. For a CMRR of 85dB, the mismatch must be less than 0.03 percent. The highdegree of cross coupling makes this possible.

CMOS amplifiers are notorious for exhibiting large volt-age noise. While this design reveals no cures for theproblem, the superiority of the silicon gate processing overmel al gate and the choice of Native p-channel devices thatare allowed to dominate the noise picture leads to voltagenoise performance (Fig. 6(a)) that is quite acceptable forgeneral-purpose applications. With a voltage noise densityof typically 36 nV/~Hz at 1 kHz and 30 nV/JHz at 10

kHz, it compares reasonably well with general-purposebipolar and BI-FET quads. There is clearly room forimprovement at the low-frequency end, however, with 80and 220 nV/~Hz found at 100 and 10 Hz, respectively.One bright spot is that the wafer-to-wafer and run-to-runvariations are minimal. There have been no observed casesof popcorn noise.

In order to protect the inputs from ESD damage, a200-fl polysilicon resistor is placed in series with eachinput and protection diodes are connected from each inputgate to either rail. These diodes are actually parasitictransistors and can protect with a low impedance on therails (i.e., in the circuit board) or with rails floating asoccurs during handling. In the former situation the protec-tion is by diode action. In most cases, continuous currentsof up to 50 mA can be put through these diodes while theIC is powered up without triggering a destructive latch. Inthe latter situation the floating supply rails allow theparasitic transistors that the diodes represent to combineand form a desirable, protective, bidirectional SCR dif-ferentially across the otherwise vulnerable input pins. Theinput bias and input offset currents that result from theseprotection diodes are dominated by the upper diodes whichconsistently outleak the bottom diodes causing the biascurrent to always exit the pins. This current is exception-ally low and typically only 50 fA at room temperature(even less in plastic). It is proportional to the voltageacross the upper diode and thus varies with common-modevoltage at the rate of about 10 fA/V, which is equivalentto an input resistance of 100 t il. The leakage currents fromthe respective inputs track well with temperature (Fig.6(b)) and rise to only 5 pA typically at + 125°C.

IV. THE INTEGRATOR

As mentioned earlier, the integrator is a compound stagethat is actually two stages in one: a preceding feed-forwardnoninverting block, and a push–pull inverting output blockthat drives the load rail to rail. The feed-forward stage(Fig. 7) is a relatively simple circuit that consists of M5,M19, M20, and M6. This small, lightly loaded, single-ended stage is able to deliver about 40 dB of gain which islargely responsible for the high overall gain of the ampli-fier. The output of this interior stage can swing rail to railwhich is essential in delivering the large gate overdrive tothe big output n-channel M8 (Fig. 8). The maximumoverdrive is clamped at 6 V by Z1 so as to act as a currentlimit. The stage is fed forward at high frequencies bycapacitor CF~ at the frequency given by

$= g~#(2~”CF~) = 550 kHz. (1)

This frequency is about one-third of the’ unity crossfrequency of the amplifier. Although CF~ could have beendriven from the first stage directly, it is more effectivebeing driven by a high-transconductance driver such asQ23. Q23 also proves useful in providing feed-forwardcompensation all the way to the large output p-channel



INPUTFROM

STAGE

FROMFEED-FORWARD

STAGE

-g

f) ‘b:““””-60

M19n

M20

ccRZ

:;12PF

1Ooorl =.

Q23I

10PAIOPF

I’oJA ‘“’Al :FCFF

TO OUTPUTSTAGE

&~5 M2;IM6 ,

, 0 BIAS@

* 916

3.=

Fig. 7. The feed-forward stage portion of the integrator.

12PF

9

Fig. 8. The output stage with rail-to-rad swing capability.

i149. Near the unity cross of the amplifier, the input stage(via Q23, CFF and C~) effectively has control of the gatesof the two large output devices lending ac stability to theamplifier.

The output stage (Fig. 8) must solve a level shiftingproblem that has plagued rail-to-rail designs for sometime. Elaborate solutions have been proposed that com-bine multiple embedded feedback loops that are in effectop amps within op amps. To succeed as a general-purposequad, a simpler solution had to be found. The signal pathof the output stage that resulted consists of just fivedevices, Q7 and M8- M1l. The complementary outputdevices M8 and M9 change their conduction in responseto the complementary common-gate level shifters M1O andM1l. These common-gate devices alter their relative con-duction levels in turn via the voltage drive of the high-transconductance driver Q7.

Quiescently, the stage biases as follows. Complementarycurrents from the bias generator flow into complementarystacks of diode-connected transistors whose 2V& “poten-

tials are used to bias the gates of M1O and M1l. Separatebut equal area ratioing of the’ top and bottom clusters ofcomplementary transistors causes M8 and M9 to carry200 PA when the level shifters each carry half (20 pA) ofthe current from current source Ml 8. This condition oc-curs when Q 7 conducts half (40 PA) of the current fromcurrent sink M14. The class AB current is stable withsupply and processing variations being only dependentupon the bias current generator and device area ratioing.

Under small-signal conditions, M8 is directly driven byQ7 and M9 is driven in like phase via M1O feeding thesource of Ml 1. M1O thus acts like a broad-band nonin-verting stage with a gain of slightly more than one. Thetotal transconductance of the output stage is found bysimply adding the transconductances of M8 and M9 whichare roughly equal. This combined transconductance isabout 2.5 mmho which is high enough to provide somegain into low-impedance loads even under small-signalconditions, which is worst case. Under large-signal condi-tions the gain will climb as either the top or bottom device


MC!NTICELL1: QUAD CMOS OP AMP WITH RAIL-TO-lL41L OUTPUT SWING 1031

begins to conduct load current. This behavior is unique todrain-output or collector-output type designs. The highsmall-signal transconductance is also a help in drivingcapacitive loads because the pole frequency caused by loadcapacitance is proportional to this transconductance. Un-delr small-signal conditions, the amplifier will typicallyhandle 100 pF over the military temperature range. Underlarge-signal conditions the capacitive load handling capa-bility increases.

‘When the output stage is driven to sink a lot of current,Q7 absorbs all the current from M14 and pulls the gate ofM8 up to a V~~ less than the supply rail or a V~~ less than6 V, whichever is less. Under these conditions M1O iscompletely shut off and Mll must carry the full current of40 pA from M18. The source of Mll rises to. its maximumpoint thus cutting back on the conduction of M9 but notturning it off. Leaving M9 in an idlig state is importantto keeping large signal distortion at a minimum, becauseotherwise there would be a crossover gap that would needto be closed by rapid slewing. Under conditions of strongsourcing, Q7 shuts off and M14 pulls all of its currentthrough M1O. Inasmuch & this current is twice as much asM-18 can provide, Mll is shut off as the gate of M9 ispulled low. This condition results in a high impedance onthe drain of M1O allowing the device to exhibit substantialVOItage gain. While the additional gain from this fourthstage is welcome, the phase shift it adds to the signal pathis certainly not. This is why the second feed-forwardcapacitor CF is needed to feed around M1O. In the strongsourcing situation, the opposing output device again doesnot shut off but instead merely idles back and this is justas important to distortion as the top-side idle. Ultimatelythe swing on the gate of M9 will come to a stop about2P’~~ from the negative rail or 6 V from the positive rail.The large swing drive to both output devices is veryimportant in driving loads close to the rails.

V. mE BXASCIRCUIT

The lack of a good, simple bias circuit has been adamper on analog CMOS performance. Aside from zeners,which do not work on + 5-V supplies, it is difficult toobtain an accurate potential in CMOS let alone a repeat-able potential with a positive temperature coefficient (TC).The positive TC is useful in moderating the growth intransistor trartsconductance at cold temperatures and hold-ing, it up at high temperatures. The accuracy is needed tohit certain performance targets and the repeatability isneeded to guarantee that performance on the data sheet. Itis iik desirable to be able to guarantee the performanceover the entire supply range and this requires that the biascircuit possess high PSRR. Finally, this particular applica-tion needs a bias circuit with complementary outputs andthe ability to work down to less than 3 V, which is thelower limit of operation for the amplifier. These needs areall met by equipping the substrate n-p-n’s with lateralcollector elements (Q26 and Q27) and operating them at

lJ+

r T -f T T 1wF~

MM ~J!.!29,5~ ~ ~

m 20 20

I

M30 M213PA

T2T

/7WA SUB

20#A II 1owl

LAT

Q26lx

10PA

t+LAT

A Cl.. I fcl “+ tb?

1% l!?

Fig. 9. The bias circuit which features area-ratioed lateral/vertical n-p-ntransistors to define a AVb, -related current.

different current densities to create a AV~~-based biascircuit (Fig. 9).

In laying out such a transistor, the lateral collector ismade to surround the emitter and is placed as close asfeature size permits to that emitter so as to maximize thecollection of electrons laterally as opposed to vertically.This lateral base width of 4 pm is defined by polysiliconand the resultant structure looks much like a concentricMOSFET which in fact it actually is. Conduction fromemitter to lateral collector due to parasitic MOS action isdiscouraged by biasing the parasitic gate such that surfaceinversion is weak or nonexistent. For the case where thegate is tied to the eniitter, which is very convenient fromboth a circuit and layout standpoint, a small amount ofsubthreshold current will flow that is insignificant fornoncritical applications such as bias circuits. Usingthe transistors in a bandgap voltage reference on theother hand would require that this effect be taken intoaccount. Bandgap designers need also consider the effectdue to the onset of large-signal injection. For minimum-sizeemitters built in a light well background such as these itoccurs at 10 p A or more. For maximum accuracy, themultiple-emitter transistor Q27 should be built with indi-vidual wells for each emitter, though the wells were madecommon in this application in order to reduce die areaconsumption.

The split of emitter current between the vertical andlateral paths is not stable with normal variations in ,processing as it depends upon controlling the ratio be-tween the vertical and lateral base widths, among otherthings. The performance of a good cir&it design using thistype of transistor should not be dependent upon theabsolute value of the split. For a drawn lateral width of 4pm and a well depth of about 5 ~m, the current flowsabout one third in the lateral collector and two thirds inthe vertical collector. Increases in collector voltage willmodulate the split as the Early voltages of the two collec-



(

v+

IY

M21M19

-)

==

RZ1000

(

CFF10

M38

4

M3

=

Fig. 10. Circuit for the entire op-arnp cell. One such cell consumes approximately 0.71 mm2 of die area

tors are not equal. The vertical collector has an Earlyvoltage of 90 V, whereas for the lateral collector it is only15 V with breakdown occurring at around 8 V.

In the circuit, Q26 and Q27 are connected in bootstrapfashion such that the collector-base voltage of each collec-tor type on each device is approximately O V. The duty ofabsorbing supply-voltage changes falls upon long-channeldevices M30 and M32 which results in high PSRR. Nega-tive feedback introduced into the” tail” of the bipolar coreof the circuit serves to stabilize the operating point of thecircuit where AVBE is irnpres=d across RB =COrd@ @

the familiar relation

1~16 = I~z4= (k. T/q” RB). h(J26/Jz7). (2)

Whereas the calculated AVBE is 36 mV for 300 K, theobserved value is closer to 38 or 40 mV due to theseconda~ effects previously mentioned. R B is constructedout of the material with the best control in the process, thep+ source/drain implant. In addition to being under goodcontrol, it also possesses a relatively mild TC of approxi-mately +500 ppm which when combined with AVBE givesthe complementary bias current outputs a net TC of+2800 ppm/°C. The start-up needs of the circuit are metby i1433–M35 and by a long 5-pm-wide well resistor thatpinches off at about 5 V and draws about 1 PA. Over the5–15-V supply range of the op amp the bias circuit helpshold the supply current changes down to just 6 percentand the majority of this change is due to output imped-ances of the transistors in the op-amp cells themselves.

VI. PERFORMANCE

The complete op-amp cell schematic shown in Fig. 10has two circuit portions not previously described which areneeded to address the situation where the feedback loop is

5V

Ov

MI, M2

M3, M4M5MSMaM9

M1o, M11

M*2, M13M14

M15

M16

Ml?M16

Ml 8, M20M21M22M24

M25M36

M37M38

700{13

120/4040)1680/91500/92200/7

100/1175/1 1

600/975/960/30100/7400/760/14320/20155/9150/209/8914200/4200/9

Fig. 11. Output swing at 1 kHz on a + 5-V suppiy into a 2-k!J capaci-tor coupled load. The swing extends to 100 mV of the negative rail and130 mV of the positive rail.

broken and the inputs are overdriven as will occur whenthe outputs clip against the rails. One is the addition of asecond emitter to Q23 to limit the overdrive to M5 and theother is the inclusion of M25 and M36– A438 to eliminatepotential instability as the amplifier output recovers frombeing collapsed against the upper rail. Small sense tran-sistor M25 straddles M9 and delivers a current wheneverM9 collapses into its triode region. This current passesthrough a gained-up mirror to blend in negative feedbacktransistor M38, which serves to reduce the forward gainand in doing so assists the four-stage amplifier in reestab-lishing equilibrium cleanly. The rail-to-rail swing and cleanclipping behavior of the amplifier is shown in Fig. 11 witha 2-kfl capacitor coupled load and l-kHz excitation. Theoutput swings to within 130 mV of the + 5-V rail and towithin 100 mV of ground. For a 600-fl load the swings areto within 390 and 300 mV, respectively.

Small-signal gain and phase is best shown on the net-work analyzer plot in Fig. 12(a) where the unity cross forthe particular device measured was 1.4 MHz with a phasemargin of 54° and a gain margin of 17 dB. The mild bumpin the gain curve (lower trace) is due to the integrator andnever presents a threat to the amplifier. Under worst-case


MONTICELLO: QUAD CMOS OP AMP WITH RAIL-TO-RAIL OUTPUT SWING 1033

(a)

(b)

Fig. 12. (a) The small-signal gain and phase response versus frequencyfrom 100 kHz to 30 MHz. The unity-gain frequency is 1.4 MHz? thephase margin is 54°, and the gain margin is 17 dB. (b) The large-signalstep response in the voltage-follower mode in which the amplifierdlisplays the classic slew steps and asymmetry caused by “tail” capaci-t ante. Positive-going slew rate is 1.45 V/ps while negative-going slew is2.1 v/ps.

conditions of heavy sinking and cold temperatures it onlypeaks a few decibels. The phase curve (upper trace) showsevidence of phase holdup due to the beneficial effects ofthe zero setting resistor R z in series with the main com-pensation capacitor Cc.

The large-signal step response is shown in Fig. 12(b) forthe voltage-follower configuration. Note the presence ofthe slew steps and slew asymmetry that one would expectfrom an input stage that features inverting p-type devices.The slew rate is degraded rising, assisted falling, andtypically averages 1.7 V/ps. Despite the use of feed-for-ward compensation, the settling time is not impaired.While driving 2 kfl from – 5 to +5 V with an invertinggalin of one, the output settles to within 0.01 percent in 7ps on the positive-going edge and 6.5 ps on the negative-going edge.

The remainder of the amplifier performance is sum-marized in Table I. For operation on a 15-V supply, thespecifications are nearly identical except for short-circuitcurrent, which doubles, and for output swing, which doesnot come as close to the rails because of the larger load

TABLE ITYPICAL PERFORMANCE(PER OP AMP) AT V+= + 5 V AND

TA = 25°C

Vos 1mVVOS Drift 1 .3@v/”c

E.@lkHz 36rWl~Hz

lb 50fA

CMRR S5dB

+ PSRR 85dB

- PSRR 95dB

Common Mode Range -0.3V to 3.1 V

Differential Range t 5V

@ity Gain Bandwidth 1.5MHz

Slaw Rate 1 .7vl#a

THD (@lOkHz with Av= - 10) 0.01%

Voltage Gain into 2kQ; Source/Sink 2000 / 500 V/mV

Voltage Gaininto 600% Source/Sink 10001250 V/mV

Output Swing into 2kfl; Low/High 0.10V/4.87V

Output Swing into 600% Low/High 0.30V/4.61V

Output Currant (Short Circuit] ~ 22mA

Supply Current 3501JA

Supply Voltage Rang: (Guaranteed) 4.75V to 15.5V

currents that must be delivered into the rated 2-kfl and600-lil loads. For example, in driving 2 kfl, the outputswings to within 370 mV of the upper rail and 260 mV ofthe lower rail. The input common-mode range will stillextend from ground to within 2 V of the upper rail.Operation over the full military temperature range of – 55to + 125°C is guaranteed for both 5- and 15-V supplies.

No special processing was used to control latch-tipsensitivity, yet the quad is not susceptible to latch-up overthe entire military temperature range. For example, inputexcitation from low-impedance sources can be applied toeither or both inputs and then the device powered up inany supply sequence without fear of latch. At least t 30mA can be accommodated under the worst-case conditionsof high supply voltage (15 V) ‘and high ambient tempera-ture (125°C). This was achieved via careful layoutthroughout the chip and output transistor geometries thatembed the drain completely within the surrounding source.

VII. CONCLUSION

A CMOS amplifier design has been presented that iswell suited to operation on a single+ 5-V supply andfeatures rail-to-rail output swing. Performance limitationsthat have limited CMOS amplifiers in the past are not aproblem with this approach. Specifications regardingV&,VO~drift, IB, lo~, broad-band noise, voltage gain, andload driving capability are all equal to or better than mostcommercially available quad op amps whether constructedwith CMOS, BI-FET, or bipolar technology. Because thisperformance has been a~hieved via circuit design andlayout techniques as opposed to special analog CMOSprocessing, the design has significance beyond its use in astand-alone product. Advanced digitally based system chipsbuilt on CMOS processes can now realize the benefits of agood on-chip op amp provided that the proper layoutconsiderations are met.


1034

ACKNOWLEDGMENT

The author wishes to acknowledge the capable assis-tance of Design Manager T. Isbell, Product Line ManagerM. Morrione, Product Engineer W. Ma, Test Engineer M.Vu, and Marketing Engineer H. Wright, whose teamworkand positive attitude were essential to the project’s success.

REFERENCES

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

[16]

[17]

[18]

[19]

[20]

P. R. Gray and R. G. Meyer, Analysis and Design of AnalogIntegrated Circuits. New York: Wiley, 1977.

Iler and T. I. Kamins, Device Electronics for IntegratedR. S. MulCircuits. New York: Wiley, 1977.P. R. Gray, D. A. Hodges, and R. W. Broderson, Eds., AnalogMOS Integrated Circuits. New York: IEEE Press, 1980.R. D. Jofiy and R. H. McCharles, “A low noise amplifier forswitched ca~acitor filters.” IEEE J. Solid-State Circuits. vol. SC-17.pp. 1192-1~94, Dec. 1982.H. C. Lin, “Comparison of input offset voltage of differentialamplifiers using bipolar transistors and field-effect transistors,”IEEE J. Solid-State Circuits, vol. SC-5, pp. 126-129, June 1970.M. A. Polinskv. O. H. Schade. Jr.. and J. P. Keller. “ CMOS-binolw. . ,, .monolithic integrated-circuit technology,” in Proc. Int. ElectronDevice Meeting, 19733 pp. 229-23LO. H. Schade, “A new generation of MOS/bipolar operationalanmlifiers.” RCA Rev.. vol. 37. DD. 404–424. SeDt. 1976.E. ?ittoz bd J. Fellrath, “ CM~S analog integrated circuits basedon weak inversion operation,” IEEE J. Solid-State Circuits, vol.SC-12, pp. 224-231,June 1977.G. Smarandoiu, D. A. Hodges, P. R. Gray, and G. F. Landsburg,“ CMOS mrlse-code-rnodtdation voice codec,” IEEE J. Solid-StateCircuits, ~ol. SC-13, pp. 504-507, Aug. 1978.0. H. Schade. Jr.. “BiMOS microuower IC’S.” IEEE J. Solid-StateCircuit;? vol. SC-13, pp. 791-79 fi,’Dec. 1978W. Steurhagen and W. L. Engl, “Design of integrated analogCMOS circuits-A multichannel telemetrv transmitter,” IEEE J.Solid-State Circuits, vol. SC-13? pp. 799-805, Dec. 1978.J. Bertails, “Low frequency noise considerations for MOS amplifierdesign,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 773-776,Aug. 1979.W. C. Black, Jr., D. J. Allstot, and R. A. Reed, “A high-perfor-mance low-power CMOS channel filter,” IEEE J. Solid-State Cir-cuits, vol. SC-15, pp. 929–938, Dec. 1980.0. H. Schade, Jr. and E. J. Kramer, “A low-voltage BiMOS opamp;’ IEEE J, Solid-State Circuitsj vol. SC-16, pp. 661-668, Dec.1981.M. G. Degrauwe, J. Rijmenants, E. A. Vittoz, and H. J. De Man,“Adaptive biasing CMOS amplifiers,” IEEE J. Solid-State Circuits,vol. SC-17, pp. 522–528, June 1982.B. Sorw and P. R. Grav. “A mecision curvature-compensatedCMOS &ndgap reference,;’’IEEE>. Solid-State Circuits, vdl. SC-18,pp. 634-643, Dec. 1983.P. R. Gray Wd R. G. Meyer, “ MOS operational amplifierdesign—A tutorial overview,” IEEE J. Solid-State Circuits, vol.SC-17, pp. 969-982, Dec. 1982.D. Maeding, “A CMOS operational amplifier with low impedancedrive capability,” ZE8E J. Solid-State Circuits, vol. SC-18, pp.227-229, Apr. 1983.V. R. Saari, “Low power high-drive CMOS operational amplifiers:’IEEE J. Solid-State Circuits? vol. SC-18, pp. 121–127, Feb. 1983.E. Toy, “AU NMOS operational amplifier:’ in ZSSCC Dig. Tech.Papers, Feb. 1979, pp. 134-135.

IEEEJOURNAL OF SOLID-STATECIRCUITS, VOL. SC-21, NO. 6, DECEMBER1986

[21]

[22]

[23]

[24]

[25]

[26]

[27]

[28]

[29]

[30]

[31]

[32]

[33]

[34]

[35]

Y. P. Tsividis, D. L. Fraser, Jr., and J. E. Dziak, “A processinsensitive high-performance NMOS operational amplifier,” IEEEJ. Solid-State Circuits, vol. SC-15, pp. 921-928, Dec. 1980.B. J. Hosticka, “Improvement of the gain of MOS amplifiers,”IEEE J. Solid-State Circuits, vol. SC-14, p . 1111–1114, Dec. 1979.

r$I. A. Young, “A high performance all-e ancement NMOS oper-ational amplifier;’ IEEE J. Solid-State Circuits, vol. SC-14, pp.1070-1077, Dec. 1979.D. Senderowicz and J. H. Huggins, “A low-noise NMOS oper-ational amplifierfl IEEE J. Solid-State Circuits, vol. SC-17, pp.

999-100$ Dec. 1982.Y. P. Tsnidis and R. W. Ulmer, “A CMOS voltage reference,”IEEE J. Solid-State Circuits, vol. SC-13, pp. 774-778, Dec. 1978.E. Vittoz and O. Neyroud, “A low-voltage CMOS bandgap refer-ence,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 573–577, June1Q7Q-, . .P. Antognetti, D. D. Caviglia, and E. Profumo, “CAD model forthreshold and subthreshold conduction in MOSFET’s~’ ZEEE J.Solid-State Circuits, vol. SC-17, pp. 454-458, June 1982.E. Vittoz, “ MOS transistors operated in the lateral bipolar modeand their application in CMOS technology,” IEEE J. Solid-StateCircuits, vol. SC-18, pp. 273-279, June 1983.E. Vittoz, “The design of high-performance anafog circuits ondigital CMOS chips:’ IEEE J. Solid-State Circuits, vol. SC-20, pp.657-665, June 1985.M. Degrauwe, E. Vittoz, and H. Oguey, “A family of CMOScompatible bandgap voltage regulators,” in lSSCC Dig. Tech.Papers, Feb. 1985, pp. 142-143.M. Degrauwe, 0. Leuthold, E, Vittoz, H. Ogueyand, and A.Descombes, “CMOS voltage references using lateral bipolar tran-sistors,” IEEE J. Solid-State Circuits, vol. SC-20, pp.1151-1157,Dec. 1985.

. .

B. Ricco, “Effects of channel geometries on FET output conduc-tance in saturation: IEEE Electron Device Lett., vol. EDL-5, pp.353-356, Sept. 1984.K. E. Brehmer and J. B. Wieser, “Large swing CMOS poweramplifier: IEEE J. Solid-State Circuits, vol. SC-18, pp. 624-629,Dec. 1983.D. Stone, J. Schroeder, R. Kaplan, and A. Smith, “Analog CMOSbuilding blocks for custom and semicustom applications;’ IEEE J.Solid-State Circuits, vol. SC-19, pp. 55-61, Sept. 1984.J. Pimbley and G. Gildenblat, “Effect of hot-electron stress onlow-frequency MOSFET noise; IEEE Electron Device Lett., vol.EDL-5, pp. 345-347,Sept.1984.

Dennis M. Monticellowas born in San Francisco,CA, on December 16, 1951. He received the B.S.degree in electrical engineering from the Univer-sity of California, Santa Barbara, in 1974.

Upon graduation, he joined National Semi-conductor Corporation, Santa Clara, CA, as aDesigner in the Consumer Linear IC Group.Since then he has worked on camera electronics,linear optoelectronics, RF remote control, groundfault interrupters, automotive electronics, oper-ational amplifiers, comparators, ac power-line

communications, voltage regulators and converters, voltage references,buffers, and other analog-related building blocks. Presently, he is aGroup Leader in the Industrial Linear IC Group. He has authoredseveral papers and has over 20 patents issued or pending in circuit design.

Mr. Monticello received the Outstanding Paper Award at the IEEEIntemationrd Solid State Circuits Conference in 1977.


d. m. monticelli, “a quad cmos single-supply op amp with rail-to

Documents