cv of md nasir uddin bhuyian
TRANSCRIPT
1
Md Nasir Uddin Bhuyian
CONTACT
INFORMATION
Department of Electrical and Computer
Engineering,
New Jersey Institute of Technology,
Newark, NJ 07102
(862) 213-6550
https://web.njit.edu/~mnb3/
RESEARCH
INTERESTS
Simulation, modeling, processing, and characterization of semiconductor devices
with novel design and architecture.
III-nitride semiconductor devices for photonic applications.
Device Reliability issues like noise spectrum analysis, BTI, electrode surface
modulation, self-heating behavior, electromigration etc.
Beyond-CMOS devices, sub-60 mV/dec transistors.
Complex oxides, ferroelectrics, correlated and multifunctional materials.
RESEARCH
EXPERIENCE
Post Doctoral Research Associate, New Jersey Institute of Technology (01/2015-
present)
PIs: Dr. Durga Misra and Dr. Hieu P T Nguyen
Studied high efficiency III-nitride nanowires on both Si and sapphire substrates for
optoelectronic devices including LEDs, lasers, solar cells and photodetectors.
Worked in clean room for molecular beam epitaxial (MBE) growth, fabrication of
nanowire devices.
Studied physical characterization, and electrical characterization of white LED
Conducted research for new applications of III-nitride nanowires for high-
brightness emissive displays with long life, full color capability, and low power
consumption.
Graduate Student Researcher, New Jersey Institute of Technology (09/2011-
12/2014)
PI: Dr. Durga Misra
Studied MOSFET and MOS Capacitors on Si and Ge substrates, III-V
semiconductors, nanowires, LED, Solar cells.
Studied the impact of cyclic SPA plasma treatment during ALD Hf1-xZrxO2
deposition.
Developed an advanced ALD process to incorporate extremely low percentage of Al
in HfO2.
Conducted research on dry and wet processed interface layers for three different p
type Ge/High-K samples on 300 mm wafers.
Conducted electrical characterization of MOS Capacitors by capacitance voltage(C-
V), current voltage(I-V), and conductance voltage(G-V) measurement over
temperatures and frequencies.
Analyzed equivalent oxide thickness (EOT), flat-band voltage (VFB), bulk doping ,
surface potential, and interface state density (Dit).
Studied the reliability of high-k/metal gate stacks by stress induced flat-band
voltage shift, stress induced leakage current (SILC), interface degradation, time
dependent dielectric breakdown (TDDB), and Weibull statistical data analysis
2
RESEARCH
EXPERIENCE
(CONTINUED)
Detail analysis of the oxygen vacancy related defects (V+/V2+ centers) has been done
and the impact of stress on the oxygen vacancy defects has been evaluated.
Developed automatic Labview programs to operate HP 4284A LCR meter and HP
4156B semiconductor parameter analyzer for efficient operation with minimum
error.
Graduate Student Researcher, Bangladesh University of Engineering and Technology
(11/2007-08/2011)
PI: Dr. Quazi Deen Mohd. Khosru
Studied the impact of uniaxial strain on band gap, electron and hole effective
mass.
Research on compact modeling of multi gate MOSFETs.
Studied different scattering mechanisms and their impact on carrier mobility.
Developed a mobility model incorporating the impact of uniaxial strain.
Developed a compact analytical model for the drain current behavior of double
gate MOSFET.
Performed simulation using MATLAB, and Synopsis Sentaurus. (Short descriptions of the research projects are available in the appendix.)
EDUCATION New Jersey Institute of Technology (NJIT), Newark, NJ, USA
Ph. D. in Electrical Engineering (January, 2015)
Dissertation: Reliability Study of Zr and Al Incorporated Hf-based High-k Dielectric
Deposited by Advanced Processing.
Advisor: Dr. Durga Misra
Bangladesh University of Engineering and Technology (BUET), Dhaka,
Bangladesh
M. Sc. in Electrical and Electronic Engineering (August, 2011)
Thesis: Drain Current Modeling of Double Gate Uniaxially Strained Si MOSFET.
Advisor: Dr. Q. D. M. Khosru
B.Sc. in Electrical and Electronic Engineering (June, 2007)
TECHNICAL SKILLS
Research Expertise: Advanced transistor device structures and architectures
(MOSFET and MOS Capacitors on Si and Ge substrates, III-V semiconductors,
nanowires, LED, Solar cells). Extensive knowledge on future transistor device physics
and process integration.
Performance Analysis: On wafer electrical characterization and reliability study of
leading edge transistor devices including current-voltage, capacitance-voltage, and
conductance-voltage across temperatures and frequencies, stress induced flat-band
voltage shift, leakage current (SILC), interface state density (Dit), TDDB failure data,
Weibull statistics analysis, and gate delay estimation.
Clean Room: Photolithography: Karl Suss MA-6 exposure tool with backside
alignment, Wet bench, Molecular beam epitaxy -Varian Gen II MBE system.
Equipment: Cascade Prober-Summit 12000 series, HP4156B/4145B semiconductor
parameter analyzer, HP 4284 precision LCR meter, Micromanipulator with HSM,
Scanning electron microscopy- LEO 1530VP Cryo SEM system , Spectrum analyzer,
Software defined radio.
Software and Programming: Synopsis Sentaurus, LabVIEW, Mentor Graphics,
Microwind, DsCh, HSPICE, VHDL, Verilog, PSPice, Multisim, Circuit maker, Assembly
language, C/C++, MATLAB, Python, MS Office, OriginLab, JMP, Creo PTC.
3
SELECTED COURSE
PROJECTS Simulation of FinFET using Synopsis Sentaurus.
Design of a 16-bit word-serial multiplier using Mentor Graphics CAD tools.
Design of a Parallel VLSI Architecture for a class of LDPC Codes using VHDL.
Design of a fully-differential, high-speed, high-precision operational amplifier with
15 mW power budget using SPICE simulation tools.
BOOK CHAPTER 1. M. N. Bhyian and D. Misra, “High-k Dielectrics and Device Reliability,” in Nano-
CMOS and Post-CMOS Electronics: Devices and Modelling, 2016, Saraju P. Mohanty
and Ashok Srivastava, ed., The Institution of Engineering and Technology.
PEER-REVIEWED
PUBLICATIONS
1. M. N. Bhuyian, R. Sengupta, P. Vurikiti, and D. Misra, “Oxygen Vacancy Defect
Engineering Using Atomic Layer Deposited HfAlOx in Multi-Layered Gate Stack,”
Appl. Phys. Lett., 108,183501( 2016).
2. M. N. Bhuyian and D. Misra, “Multilayered ALD HfAlOx and HfO2 for High Quality
Gate Stack,” IEEE TDMR, 15(2), 229 (2015).
3. M. N. Bhuyian, S. Poddar, and D. Misra, “Impact of Cyclic Plasma Treatment on
Oxygen Vacancy Defects in TiN/HfZrO/SiON/Si Gate Stacks,” Appl. Phys. Lett. 106,
193508 (2015).
4. M. N. Bhuyian, D. Misra, K. Tapily, R. Clark, S. Consiglio, C. Wajda, G. Nakamura,
and G. Leusink, “Interface State Density Engineering in Hf1-xZrxO2/SiON/Si gate
stack,” J. of Vac. Sci. and Technol. B, 34(1), 011207 (2015).
5. M. N. Bhuyian and D. Misra “ALD Hf0.2Zr0.8O2 and HfO2 with Cyclic
Annealing/SPA Plasma Treatment: Reliability,” Emerging Materials Research, 4,
229(2015).
6. M. N. Bhuyian, D. Misra, K. Tapily et al., “Cyclic Plasma Treatment during ALD
Hf1-xZrxO2 Deposition,” ECS J. Solid State Sci. and Technol., 3(5) N83 (2014).
7. Y. Ding, D. Misra, M. N. Bhuyian, K. Tapily, R. D. Clark, S. Consiglio, C. S. Wajda,
and G. J. Leusink, “Electrical Characterization of Dry and Wet Processed Interface
Layer in Ge/High-K Devices,” J. of Vac. Sci. and Technol. B, 34(2), 021203(2016).
8. M. N. Bhuyian and D. Misra, “Reliability of HfAlOx in Multi Layered Gate Stack,”
In Proc. IEEE IRPS, 2015, PI.3.1-3.7.
9. Y. Ding, D. Misra, M. N. Bhuyian, K. Tapily, R. D. Clark, S. Consiglio, C. S. Wajda,
and G. J. Leusink, “Electrical Characterization of Dry and Wet Processed Interface
Layer in Ge/High-K Devices,” ECS Transactions, 69(5), 313 (2015).
10. D. Misra, M.N. Bhuyian, and Y. Ding, “Dielectric-Semiconductor Interface for
High-k Gate Dielectrics for sub-16nm CMOS Technology,” in Proc. IEEE Conference
on Electron Devices and Solid State Circuits, 2015.
11. M. N. Bhuyian, D. Misra, K. Tapily, R. Clark, S. Consiglio, C. Wajda, G. Nakamura,
and G. Leusink, “Effect of Al Doping on the Reliability of ALD HfO2,” ECS
Transactions, 64(8), 29(2014).
12. M. N. Bhuyian, D. Misra, K. Tapily, R. Clark, S. Consiglio, C. Wajda, G. Nakamura,
and G. Leusink, “Cyclic Plasma Treatment during ALD Hf1-xZrxO2 Deposition,” ECS
Transactions, 61(2), 41(2014).
13. M. Bhuyian, and D. Misra, “Reliability Considerations of High-k Dielectrics
Deposited by Various Intermediate Treatment,” ECS Transactions, 60(1), 103(2014).
14. M. N. Bhuyian, D. Misra, K. Tapily, R. Clark, S. Consiglio, C. Wajda, G. Nakamura,
and G. Leusink, “Reliability of ALD Hf1-xZrxO2 Deposited by Intermediate Annealing
or Intermediate Plasma Treatment,” ECS Transactions, 58(7), 17(2013).
4
PEER-REVIEWED
PUBLICATIONS
(CONTINUED)
15. H. P. T. Nguyen, M.N. Bhuyian, A. Diop, M. R. Phillip, Y. Evo, and J, Piao, “Self-
Organized InGaN/AlGaN Superlattice Core-Shell Heterostructures for High Power
Phosphor-Free Nanowire White Light-Emitting Diodes,” (Submitted to The Journal
of Luminescence).
PRESENTATIONS 1. “Effect of Al Doping On The Reliability of ALD HfO2,” Semiconductors, Dielectrics, and
Metals for Nanoelectronics 12, 226th ECS Meeting, Cancun, Mexico, Oct 5-9, 2014.
2. “Cyclic Plasma Treatment during ALD Hf1-xZrxO2 Deposition,” Dielectrics for
Nanosystems 6: Materials Science, Processing, Reliability, and Manufacturing, 225th
ECS Meeting, Orlando, FL, May 11-15, 2014.
3. , “Reliability of ALD Hf1-xZrxO2 Deposited by Intermediate Annealing or Intermediate
Plasma Treatment,” Semiconductors, Dielectrics and Metals for Nanoelectronics 11,
224th ECS Meeting, San Francisco, CA, October 27 – November 1, 2013.
4. “Reliability of HfAlOx in Multi Layered Gate Stack,” Poster presentation in IEEE
International Reliability Physics Symposium, Monterey, CA, April 19-23, 2015.
5. “Reliability of Al Doped HfO2 with Multi Layered ALD HfAlOx,” 2014 GSA Research
Day Poster Presentation at New Jersey Institute of Technology, Newark, NJ.
6. “ALD High-K Gate Stacks for Next Generation CMOS Technology,” 2015 Summer
Research Program Poster Presentation at New Jersey Institute of Technology, Newark,
NJ.
7. “Understanding Defects in TiN/HfZrO/SiON/Si Gate Stacks,” 2014 Summer Research
Program Poster Presentation at New Jersey Institute of Technology, Newark, NJ.
8. “Reliability Of ALD Hf1-xZrxO2 Deposited by Intermediate Plasma Treatment (DSDS)
with Nitrided Chemically Grown Interface and Plasma Oxynitride Interface,” 2013
Summer Research Program Poster Presentation at New Jersey Institute of Technology,
Newark, NJ.
9. “Characterization Of High-K Gate Dielectrics Using a MOS Capacitor,” 2012 Summer
Research Program Poster Presentation at New Jersey Institute of Technology, Newark,
NJ.
10. “Electrical Characterization of Dry and Wet Processed Interface Layer in Ge/High-K
Devices,” Semiconductors, Dielectrics, and Metals for Nanoelectronics-13, 228th ECS
Meeting, Phoneix, Az, October 11 – 16, 2015.
PROFESSIONAL
ACTIVITIES AND
SERVICES
MEBERSHIP:
The Electrochemical Society.
American Vacuum Society.
Graduate Student Association of NJIT.
Bangladesh Student Association of NJIT.
BUET Debating Club.
PEER REVIEWING:
Journal of Nanomaterials (2015-present).
Emerging Material Research (2015-present).
FELLOWSHIPS AND
AWARDS
Hashimoto Fellowship and Ross Fellowship awarded by NJIT.
Special Achievement Award by GSA of NJIT.
Best Poster Presentation Award on GSA Research Day, October, 30, 2014.
Student Travel Grant awarded by The Electrochemical Society.
BUET Dean’s List Award and BUET Merit Scholarship.
5
LEADERSHIP
EXPERIENCE
Research Mentorship, 07/2007-present
I mentored 14 undergraduate students (EE major) and five graduate student (EE major)
at New Jersey Institute of Technology (NJIT). Their projects focused on electrical
characterization and reliability study of high-k/metal gate stacks and III-nitride nanowire
LED devices, simulation of solar cell by synopsis sentaurus.
Graduate: Y. Ding (NJIT, 01/2014-present), A. M. Diop (NJIT, 05/2015-10/2015), S.
Mukhopadhyay (NJIT, 09/2015-present), S. Mitra (NJIT, 09/2015-present), M.R. Philip
(NJIT, 09/2015-10/2015).
Undergraduate: A. Sengupta (06/2016-08/2016), A. John (NJIT, 05/2015-10/2015), Y.
Evo (NJIT, 05/2015-10/2015), R. Rocha (NJIT, 05/2015-10/2015), M. K. Yamaoka (NJIT,
05/2015-10/2015), R. Sengupta (NJIT, 06/2015-08/2015), P. Vurikiti (NJIT, 06/2015-
08/2015), S. Poddar (06/2014-08/2014), S. Bhattacharya (NJIT, 06/2013-08/2013), I.
Priyadharshini (NJIT, 06/2013-08/2013), A. Mohan (NJIT, 06/2013-08/2013), D.
Chattopadhyay (NJIT, 06/2012-08/2012), H. Chakraborty (NJIT, 06/2012-08/2012), J.
Krishnasamy (NJIT, 06/2012-08/2012)
TEACHING
EXPERIENCE
Adjunct Faculty at New Jersey Institute of Technology, Newark, New Jersey
(02/2015-present)
Taught Computer Programming and Problem Solving (CS 101) in the Computer
Science Department, in four sections, enrolment ~30 students in each section.
Conducted one and half hour theory class, three hours lab class in each week, and
held an hour long office hour per week.
Taught Introduction to Communication (ECET 214) in the Engineering
Technology Department, enrolment ~25 students. Conducted two hours theory
class, two hours lab class in each week, and held an hour long office hour per
week.
Instructor of Center for Pre-College Program at New Jersey Institute of
Technology, Newark, New Jersey (07/2015-08/2015)
Taught science courses (Physics, Chemistry, Biology, and Environmental Science)
to high school students in the upward bound summer program.
Teaching Assistant at New Jersey Institute of Technology, Newark, New Jersey
(09/2011-12/2014)
Instructed Digital Design lab course (ECE 394) to undergraduate students.
Designed lab manual, Conducted three hours long lab class, and held an hour long
office hour per week.
Instructed CAD softwares (Mentorgraphics, HSPICE) to graduate students in the
VLSI Design (ECE 658) course.
Conducted recitation class (one hour problem solving class in each week)in
Electrical Circuits I (ECE 221) course for undergraduate students.
Served as a grader for Electrical Circuits II (ECE 231), Random Signal Processing
(ECE 673) courses.
6
TEACHING
EXPERIENCE
(CONTINUED)
Senior Lecturer (01/2011-08/2011), Lecturer (07/2007-12/2010) at Stamford
University Bangladesh, Dhaka, Bangladesh
Taught multiple theory courses (Electronics I, Energy Conversion I &II, Power
Systems I, Optoelectronics) and two lab courses (Energy Conversion laboratory
and Power Systems Laboratory) to undergraduate students in the Electrical and
Electronic Engineering department.
Mentored three undergraduate students in final year project. The project topic
was “Design and simulation of a long power transmission line”.
Maintained five hours counseling session in a week to help students outside the
classroom hours.
Advised students in choosing major/minor courses and career planning.
Assisted administration in driving curriculum design & development.
Worked with University leadership on strategic planning initiatives advancing
science and technology education.
Actively participated on university committees.
Active engagement in professional development activities.
REFERENCES Academia:
Dr. Durga Misra
Professor of ECE Department
New Jersey Institute of Technology
Newark, NJ-07102
Telephone: 973 596 5739
Email: [email protected]
Dr. Hieu P T Nguyen
Assistant Professor of ECE Department
New Jersey Institute of Technology
Newark, NJ-07102
Telephone: 973 596 3523
Email: [email protected]
Dr. Leonid Tsybeskov
Professor of ECE Department
New Jersey Institute of Technology
Newark, NJ-07102
Telephone: 973 596 6594
Email: [email protected]
Industry:
Dr. Kanda Tapily
Thin Film Process Technology
TEL Technology Center, America, LLC
Albany, NY 12203
Email: [email protected]
Robert D. Clark
Thin Film Process Technology
TEL Technology Center, America, LLC
Albany, NY 12203
Email: [email protected]
7
APPENDIX SHORT DESCRIPTION OF PROJECTS
A. ALD HfAlOx WITH ADVANCED PROCESSING: RELIABILITY
A1. Multilayered ALD HfAlOx and HfO2 for High Quality Gate Stacks. This work has demonstrated a
high quality HfO2 based gate
stack by depositing atomic layer
deposited (ALD) HfAlOx along
with HfO2 in a layered structure.
In order to get a multifold
enhancement of the gate stack
quality, both Al percentage and
distribution were observed by
varying the HfAlOx layer
thickness and its location in the
gate stack (Fig. 1(a)). It was
found that < 2% Al/(Al+Hf)%
incorporation can result in up to
18% reduction in the average
EOT(Fig. 1(b)) along with up to
41% reduction in the gate
leakage current (Fig. 1(c)) as
compared to the dielectric with
no Al content. The modification in the crystalline structure by Al incorporation in HfO2
was found to contribute to the enhancement in electrical characteristics.
[Publication: M. N. Bhuyian et al, IEEE TDMR, 15(2), 229 (2015).]
A2. Reliability of HfAlOx in Multi Layered Gate Stack. We evaluated the reliability characteristic of ALD HfAlOx with extremely low Al incorporation (<7%) in HfO2 by subjecting them to a constant voltage stress in the gate injection mode. Stress
induced flat-band voltage shift (VFB) (Fig. 2(a)), stress induced leakage current (SILC) (Fig. 2(b)),
stress induced interface state density (Dit) were monitored. In addition, all devices were subjected to time dependent dielectric breakdown (TDDB) stress in gate injection mode. Comparison for dielectrics (A2) annealed at different temperatures are shown in insets in Fig. 2(a-b). It is observed that Al presence in HfO2 reduces stress induced trap generation for both Lot A and Lot B compared to the control sample C (Fig. 2). [Publication: M. N. Bhuyian et al, IEEE IRPS, 2015, PI.3.1-3.7.]
Fig. 1 (a) ALD multilayered structures, (b)
experimental flat-band voltage and (c) gate leakage
current as a function of EOT.
Fig. 2 (a) Stress induced flat-band
voltage shift and (b) SILC for ALD
HfAlOx with <2 to 7% Al.
8
A. ALD HfAlOx WITH ADVANCED PROCESSING: RELIABILITY (CONTINUED)
A3. Interface State Density and TDDB Reliability Study for ALD HfAlOx with Multilayered Gate Stacks.
We have estimated the interface state density (Dit) in the Si band gap for ALD HfAlOx with extremely low Al incorporation (<2 to 7%) using conductance method (Fig. 3(a)). The addition of Al in HfO2 showed a slight increase in the mid gap Dit (Fig. 3(a)). On the other hand, dielectrics with <4% Al showed higher charged to breakdown (QBD) and steeper Weibull slope as shown in the TDDB plot in Fig. 3(b). [Publication: M.N. Bhuyian et al., ECS Transactions, 64(8), 29(2014).]
A4. Oxygen Vacancy Defect Engineering Using ALD HfAlOx in Multi-Layered Gate Stack. This work evaluates the defects in high quality ALD
HfAlOx with extremely low Al (<3% Al/(Al+Hf))
incorporation in the Hf based high-k dielectrics. The
defect activation energy estimated by high
temperature current voltage measurement shows
that the charged oxygen vacancies, V+/V2+ are the
primary source of defects in these dielectrics. When
Al is added in HfO2, the V+ type defects with a defect
activation energy of Ea ~0.2 eV modifies to V2+ type
to Ea ~0.1 eV with referenced to the Si conduction
band. When devices were stressed in the gate
injection mode for 1000s, more V+ type defects are
generated and Ea reverts back to ~0.2 eV. Since Al
has less number of valance electrons than Hf, the
change in the co-ordination number due to Al
incorporation seems to contribute to the defect level
modifications. Additionally, the stress induced
leakage current (SILC) behavior observed at 200C
and at 1250C demonstrates that the addition of Al in
HfO2 contributed to suppressed trap generation
process. The Arrhenius plots for Sample A (2.4%
Al) and Sample B (0.6% Al) were compared with the
control Sample C (0% Al) in Figs. 4 (a-b).
[Publication: M.N. Bhuyian et al., Appl. Phys. Lett., 108,183501( 2016).]
Fig. 3(a) Interface state density (Dit) in the Si band gap and
(b) TDDB characteristics for ALD multilayered gate stack
with <2 to 7% Al in HfO2.
Fig.4 ln(Jg/Eox) vs 1000/T
(Arrhenius plot) for different
dielectrics: (a) for unstressed
devices and (b) for devices stressed
at VG = -1V at 1250C in the gate
injection mode for 1000s.
9
B. ALD Hf1-xZrxO2 WITH ADVANCED PROCESSING: RELIABILITY
B1. Cyclic Plasma Treatment (DSDS Process) During ALD Hf1-xZrxO2
Deposition.
In this research, the effect of slot plane antenna
(SPA) Ar plasma on the performance of
intermediate plasma (DSDS) treated ALD Hf1-
xZrxO2 samples with x=0, 0.31, 0.8 were
investigated. The DSDS process is shown in
Fig. 5(a). For both DSDS and As-Dep Hf1-xZrxO2
a total of 44 ALD cycles were used to deposit the
dielectrics and none of them were subjected to any
post deposition anneal (PDA). Figure 5(b) shows
the comparison of dielectric thickness and IL
thickness for DSDS and As-Dep processed high-k
dielectrics with different Zr percentages. It was
observed that, samples with higher Zr percentages
have lower interfacial layer thickness. Exposure to
intermediate plasma increases the film density by
reducing the impurity concentration. Also, plasma
suppresses thermal induced oxygen diffusion to
the interfacial layer for oxide regrowth. As a result,
both the dielectric thickness and the IL thickness
reduction are observed for the films subjected to
intermediate plasma (Fig. 5(b)).
[Publication: M.N. Bhuyian et al., ECS J. Solid
State Sci. and Technol., 3(5) N83 (2014).]
B2. Enhanced Electrical Characteristics of ALD Hf1-xZrxO2 by DSDS Processing. In this research we demonstrated enhanced electrical characteristics of DSDS processed ALD Hf1-xZrxO2 by direct measurement of capacitance voltage characteristics (Fig. 6(a)). It was found that with increasing percentage of Zr in the gate oxide EOT downscaling is possible as shown in Fig. 6(b). The addition of Zr reduces available oxygen in the film which is responsible for
interfacial layer regrowth. The SPA
plasma exposure further enhances
the EOT by reducing impurity content in the dielectrics and thus a better film
formation. [Publication: M.N. Bhuyian et al., ECS Transactions, 61(2), 41(2014).]
Fig.5(a) Schematic representation of
DSDS process using a SPA plasma
system, (b) dielectric thickness and
interfacial layer (IL) thickness for
MOSCAPs with DSDS and As-Dep
Hf1-xZrxO2 (x = 0,0.31, and 0.8).
Fig. 6 (a) Capacitance voltage (C-V)
characteristics for DSDS and As-Dep MOSCAPs
(b) EOT variation for the devices with
intermediate SPA plasma and without plasma as
a function of zirconium percentage.
10
B. ALD Hf1-xZrxO2 WITH ADVANCED PROCESSING: RELIABILITY (CONTINUED)
B3. Reliability Characterization of ALD Hf1-xZrxO2 with Cyclic Plasma Treatment/Cyclic Annealing. In this research, the reliability of atomic layer deposited (ALD) Hf0.2Zr0.8O2 and HfO2 on a SiON interfacial layer (IL) with DADA (cyclic deposition and annealing) and DSDS (cyclic deposition and slot-plane-antenna (SPA) Ar plasma exposure) are studied. The results are compared with control As-Deposited samples (As-Dep), without any treatment during or after the dielectric deposition. When devices are subjected to a constant voltage stress in the gate injection mode, DSDS Hf0.2Zr0.8O2 showed a 4 times reduction in the flat-
band voltage shift (VFB) (Fig. 7(a)) and a 3 order of magnitude reduction in the stress induced leakage current (SILC) (Fig. 7(b)) within 100 s stress as compared to the control sample. The addition of Zr and the cyclic plasma exposure (DSDS process) seems to supress the oxide trap formation in Hf0.2Zr0.8O2 films. On the other hand, cyclic annealing does not provide benefit to ALD Hf1-
xZrxO2 and resulted a degraded interface when Zr is added to HfO2. [Publication: M.N. Bhuyian et al., ECS Transactions, 58(7), 17(2013).]
B4. Reliability Characterization for Different Interfacial Layers on Si Substrate. This research evaluates the electrical characteristics and reliability for ALD Hf1-xZrxO2
deposited on SiON interface formed by two different processing conditions: (i) UV
nitridation of chemically grown oxide (Chemox +RFN) and (ii)growth of plasma
oxinitride after removing the chemically grown oxide by COR process (COR+SPAON).
While the plasma
oxynitride showed to scale
the EOT by around 2 Å, it
also showed more than
200 mV higher flat-band
voltage shift (Fig. 8(a)).
When the devices were
subjected to a constant
voltage stress in the gate
injection mode, the
Chemox + RFN interfacial
layer showed an improved
resistance to the stress
(Fig. 8(b)).
[Publication: M.N. Bhuyian et al., Emerging Materials Research, 4, 229(2015).]
Fig. 7 Impact of stress on (a) flat-
band voltage shift, (b) gate leakage
current for DSDS and DADA Hf1-
xZrxO2. The inset in Fig. 7(b) shows
the gate leakage current behavior for
DSDS HfO2.
Fig. 8 (a) Capacitance voltage characteristics and (b) flat-band voltage shift as a function of stress time for ALD Hf1-xZrxO2 deposited on two different interfacial layers: Chemox+RFN and COR+SPAON.
11
C. CURRENT VOLTAGE (I-V) CHARACTERIZATION OF ALD Hf1-
xZrxO2 ACROSS TEMPERATURES
C1. Experimental Observation of Trap Assisted Tunneling Using High Temperature (I-V) Measurements. In this research temperature
dependent current voltage
characteristics of ALD Hf1-
xZrxO2 have been analyzed to
understand the current
conduction mechanism in the
dielectrics. Fig. 9 (a) shows the
current voltage characteristics
for DSDS Hf0.2Zr0.8O2 with the
variation in measurement
temperature. Fig. 9 (b) shows ln
(Jg) as a function of ln (Eox) in the
negative bias region. The electric field across the high-k dielectrics, Eox was calculated by
using stacked dual oxide MOS energy band diagram visual representation program. The
linear relationship between ln (Jg) and ln (Eox) (Fig. 9(b)) suggests that the trap
assisted tunneling is the dominant mechanism for the gate leakage current.
[Publication: M.N. Bhuyian et al., Appl. Phys. Lett. 106, 193508 (2015).]
C2. Defect Level Estimation from the Arrhenius Plots.
In this research the defect activation energy (Ea) for
various ALD grown Hf1-xZrxO2 dielectrics has been
evaluated by analyzing the ln(Jg/Eox) vs 1000/T
(Arrhenius plot) (Fig. 10 (a)). The observed defect
levels that contribute to trap assisted tunneling, are
found within 0.5 eV from the Si conduction band for
all samples (Fig. 10(b)). Considering the conduction
band offset for HfO2 ~1.5 eV, and for Hf0.2Zr0.8O2 ~1.4
eV, these traps have the defect energy level in the
range 1.8 eV to 1.9 eV from the conduction band edge
of the high-k layer. The observed trap energy levels in
Fig. 10 (b) suggest that charged oxygen vacancies
(V+/V2+) are the likely defects in HfO2 and
Hf0.2Zr0.8O2.
[Publication: M.N. Bhuyian et al., Appl. Phys. Lett.
106, 193508 (2015).]
Fig. 9 (a) Current voltage (I-V) characteristics at
elevated temperatures, (b) ln(Jg) as a function of
ln(Eox) in the negative bias region.
Fig. 10 (a) ln(Jg/Eox) vs 1000/T (Arrhenius plot) for different dielectrics, (b) Charged oxygen vacancies (V2+ and V+ ) in Hf1-xZrxO2 in the context of MOS energy band diagram.
12
D. INTERFACE
STATE DENSITY
ENGINEERING IN
Hf1-xZrxO2/SiON/Si
GATE STACKS
D1. Interface State Density Characterization Using Conductance Method. In the conductance method, the capacitance
voltage (C-V) and conductance voltage (G-V)
characteristics were obtained at multiple
frequencies in the range of 1 MHz to 100 Hz.
The original measured capacitance (Cm) and
conductance (Gm) values were subsequently
corrected to exclude the effect of Rs which
results the corrected capacitance Cc (Fig.
11(a)). During the gate voltage sweep from
inversion to accumulation the capture and
emission process of the interface traps at
different energy levels in the Si band gap
gives rise to the conductance variation when
plotted as function of frequency. The trap
energy level, Et in the Si band gap was
determined from the surface potential Φs,
and the interface state density, Dit was
estimated from the magnitude of the
conductance peak observed in the Gp/vs
frequency plots (Fig. 11(b-c)).
[Publication: M.N. Bhuyian et al., Journal of Vacuum Science and Technology B, 34(1), 011207 (2015).]
D2. Impact of Cyclic Plasma Treatment, Cyclic Annealing, and Interfacial Layer on Interface State Density.
This work investigates the interface state density, Dit by
conductance method for: i) cyclic deposition and slot-plane-
antenna (SPA) Ar plasma exposure, DSDS, and ii) cyclic
deposition and annealing, DADA, during the deposition of
ALD Hf1-xZrxO2 to fabricate the TiN/Hf1-xZrxO2/SiON/Si
gate stack. The addition of ZrO2 and SPA plasma exposure
is found to suppress interface state generation (Fig. 12(a)). On the other hand, DADA process increases the mid gap Dit
when Zr is added to HfO2 (Fig. 12(b)). The interface
characteristics observed for SiON formed by UV nitridation
seems to be better as compared to that formed plasma
oxynitride (Fig. 12(c)), which is attributed to the more
uniform nitrogen incorporation by UV nitridation.
[Publication: M.N. Bhuyian et al., J. Vac. Sci. Technol. B, 34(1), 011207 (2015).]
Fig. 11 (a) Corrected capacitance (Cc) as a
function of gate voltage (b) the normalized
conductance (Gp/) as a function of the
measurement frequency, (c) the
normalized conductance (Gp/) as a
function of surface potential (Φs) at 500
KHz (solid lines and filled symbols) and at
50 KHz (dotted lines and open symbols)
for different sample types, (d) Interface
state density, Dit in the Si band gap.
Fig. 12 Mid gap Dit as a function of stress in the gate injection mode for (a) DSDS vs
As-Dep Hf1-xZrxO2 (b) DADA vs As-Dep Hf1-xZrxO2, and (c) Chemox+RFN vs
COR+SPAON interfacial layers.
13
E. DRY AND WET
PROCESSED
INTERFACE LAYER IN
GE/HIGH-K
DEVICES
E1. Electrical Characterization of Dry and Wet Processed Interface Layer in Ge/High-K Devices. In this work, the dry and
wet processed interface
layers for three different p
type Ge/interfacial
layer/Al2O3/ZrO2/TiN
gate stacks on 300mm
wafers were studied at low
temperatures by
capacitance–voltage (CV),
conductance–voltage
measurement, and
deep level transient
spectroscopy. The interface
treatments were (1) simple
chemical oxidation
(Chemox); (2) chemical
oxide removal (COR)
followed by 1nm oxide by
slot-plane-antenna (SPA)
plasma (COR and SPAOx);
and (3) COR followed by
vapor O3 treatment (COR
and O3). Since low
temperature measurements
are more reliable, several
parameters like equivalent
oxide thickness, flatband voltage, bulk doping, and surface potential as a function of gate
voltage are reported. Different temperature CV measurement suggests that all the
samples are pinned at flat band voltage(Cit give a pseudo-accumulation region) due to
large Dit (larger than 1013cm_2/eV). Room temperature measurement indicates that
superior results were observed for slot-plane-plasma-oxidation processed samples.
[Publication: Y. Ding, D. Misra, M.N. Bhuyian et al., J. Vac. Sci. and Technol.
B, 34(2), 021203(2016).]
Fig. 13 (a) Corrected 1MHz capacitances (Cc) as a function of gate voltage at room temperature, (b) Interface defects density (Dit) is plotted as function of bandgap for three samples at two temperatures (100 and 300 K), (c) Deep level transient spectrum for the sample with COR followed by vapor O3 treatment (COR and O3)., Ct1 and Ct2 are two capacitance values sampled at two different time (t1<t2), s is the time
constant calculated as (t2 t1)/Ln(t2/t1). (d) Jg as a function of EOT for different splits.
14
F. PHOSPHOR-FREE
InGaN/AlGaN
CORE-SHELL
NANOWIRE WHITE
LIGHT-EMITTING
DIODES
E1. Phosphor-Free InGaN/AlGaN Core-Shell Nanowire White Light-Emitting
Diodes Grown by Molecular Beam Epitaxy.
In this research we report on
the achievement of phosphor-
free nanowire white light-
emitting diodes (LEDs), with
the incorporation of
InGaN/AlGaN nanowire
heterostructures grown
directly on Si(111) substrates
by molecular beam epitaxy.
Multiple color emission
across nearly the entire visible
wavelength range can be
realized by varying the In
composition in the quantum
dot active region. Moreover,
multiple AlGaN shell layers
are spontaneously formed
during the growth of the
InGaN/AlGaN quantum dots,
leading to the drastically
reduced nonradiative surface
recombination, and enhanced
carrier injection efficiency.
Such core-shell nanowire
structures exhibit significantly
increased carrier lifetime and
massively enhanced photoluminescence intensity compared to conventional InGaN/GaN
nanowire LEDs. Strong white-light emission was recorded for the unpackaged core-shell
nanowire LEDs with an output power of >5.2 mW, measured under an injection current
density of ~ 60A/cm2, with an unprecedentedly high color rendering index of > 95.
[Publication: M.N. Bhuyian et al., Journal of Luminescence (Just submitted).]
Fig. 14 (a) Schematic illustration of an InGaN/AlGaN
dot-in-a-wire core-shell LED heterostructure on Si
substrate. (b) A 45° tilted SEM image of a typical
InGaN/AlGaN core-shell nanowire LED sample, (c)
photoluminescence spectra showing significant
stronger intensity for the InGaN/AlGaN core-shell LED
structure, compared to the InGaN/GaN sample without
using core-shell structure, (d) Current-voltage
characteristics of the core-shell nanowire LED with the
optical image of the white LED.