custom integrated circuits conference ; 6 (rochester, ny ... · contents l j,/ ^ c c mondaymorning...
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Proceedings of the
1984
CUSTOM INTEGRATED CIRCUITS
CONFERENCE
Genesee Plaza/Holiday Inn
Rochester, NY May 21-23,1984
'uNiVERSITATSBiBUOTHEK"HANNOVER
TECHNISCHE
INFORMATIONSBIBLIOTHEK
The 1084 CICC is sponsored by the Electron Devices Society of the IEEE and the
Rochester Section of the IEEE, The CICC alms to bring together designers, producers and
users of custom IC's to discuss recent developments and future directions In custom
integrated circuits.
84CH1987-7
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CONTENTS l j,/ ^ c c
MONDAY MORNING Room A/B PAGE
8:30 WELCOME-OPENING REMARKS 1
A. K. Silzars, Conference Chairman
8:50 "CICC '84-TECHNICAL PROGRAM" 3
W. N. Grant, Technical Program Committee Chairman
9:00 KEYNOTE ADDRESS 5
"Bridging the Gap"James E. Dykes, Vice President & General Manager, Semiconductor Business Division, G.E., Research Triangle
Park, NC
MACRO-CELL BASED DESIGN 9
Chairperson: V. Leo Rideout
Co-Chairperson: Joel M. Schoen
9:45 A 32 bit CMOS Microprocessor Using a Semi-custom Cell Library 10
K. LeClair, R. Bell, D. Breid, P. Torgerson, D. Fier, B. Jensen, Sperry Corp., St. Paul, MN
10:10 Customization of a Microcomputer Chip 13
H. T. French, AT&T Bell Laboratories, Murray Hill, NJ
10:35 A CMOS High Speed CODEC Processor for a Facsimile Apparatus 14
T. Harakawa, N. Suemori, T. Matsunaga, K. Nakamura, Y. Kojima, J. Koike, M. Mizukami, K. Ikuzaki, Hitachi,Ltd., Tokyo, Japan
11:00 An Eight Bit CMOS DAC Cell for Semi-custom Designs 19
P. H. Saul, D. W. Howard, C. J. Greenwood, Plessey Research (Caswell) Ltd., Towcester, Northants, England
11:25 64K Bit Modular CMOS ROM Array 24
M. Mazin, J.-l. Sano, M. Borghese, N. Cserhalmi, Raytheon Company, Bedford, MA
11:50 Cell Memory Array 25
J. T. Harrington, H. N. Scholz, AT&T Bell Laboratories, Allentown, PA
H. Fischer, T. Bednar, rWIXnQllffWNwanz, IBM, Essex Junction, VT
12:40 A High Performance 1.5 Micron CMOS 24 x 24 Bit Multiplier 30
C. Y. Ho, R. T. Jerdonek, S. E. Noujaim, D. Schumacher, General Electric Corporate R&D, Schenectady, NY
CONTENTS
MONDAY MORNING Room C/D PAGE
FABRICATION TECHNOLOGY 35
Chairperson: Heinz H. Busta
Co-Chairperson: Marc D. Hartranft
9:45 TUTORIAL
Recent Advances in Silicon-on-lnsulator Technologies 36
H. W. Lam, Texas Instruments, Inc., Dallas, TX
10:35 Scaled CMOS Technology with PTSI/TI:W/AL ( + Cu)/Oxide/AL Double Level Interconnect for Gate ArrayProducts 40
M. Gill, V. Tsai, L. Harper, T. Tran, A. Haranhalli, P. Shah, G. Brown, P. Ghate, Texas Instruments Inc., Dallas,TX
11:00 An Isolated Vertical npn Bipolar Transistor in an N-well CMOS Process 46
C. N. Anagnostopoulos, P. M. Zeitzoff, K. Y. Wong, B, Brandt, Eastman Kodak Co., Rochester, NY
11:25 Complementary Hybrid MOS Technology 47
J. R. Pfiester, J. D. Shott, J. D. Meindl, Stanford University, Stanford, CA
11:50 Power BiMOS—A Versatile IC Technology for Switching and Regulation Applications 51
S. Lytle, R. Roop, D. Cave, D. Hughes, W. Gegg, A. R. Alvarez, Motorola, Inc., Mesa, AZ
12:15 Characterization and Use of the Mosaic Oxide Isolation Process for Linear Applications 57
J. Foerstner, D. Cave, R. Roop, Motorola, Inc., Mesa, AZ
MONDAY MORNING Room E/F/G
IMAGE PROCESSING AND DETECTORS 61
Chairperson: Rajinder P. Khosla
Co-Chairperson: Tom H. Lee
9:45 Fading Memory Focal Plane Processor 62
C. E. Tew, Texas Instruments Inc., Dallas, TX
10:10 CCD-Based Parallel Analog Processor 66
J. D, Joseph, P. C. T. Roberts, C. L. Carrison, P. M. Narendra, J. A. Hoschette, N. Zafar, Honeywell Inc.,Minneapolis, MN
10:35 Custom Circuits Minimize CCD Camera Power and Space Requirements 70
P. J. Andrews, D. E. Russell, J. M. Younse, Texas Instruments Inc., Dallas, TX
11:00 A 27-Channel Photodiode/Preamp Array 76
N. W. Van Vonno*, B. P. Howell*, B. Simon**, Harris CICD, Melbourne, FL*, Applied Technology, Sunnyvale,CA**
11:25 Silicon Imaging Arrays with New Photoelements, Wide Dynamic Range and Free From BloomingS. G. Chamberlain*, J. P. Y. Lee**, University of Waterloo, Waterloo, Ont., Canada*, Dept. of National Defence,
Ottawa, Shirleys Bay; Ont, Canada**
CONTENTS
MONDAY MORNING Room E/F/G PAGE
11:50 A Self-Calibrating Infrared Reflectance Densitometer ChipM. Zomorrodi, L F. Cheung, A. Ibrahim, Xerox Corporation, El Segundo, CA
12:15 MOS Integrated Silicon Pressure SensorH. Tanigawa, T. Ishihara, M. Hirata, K. Suzuki, NEC Corporation, Kawasaki, Japan
86
91
MONDAY AFTERNOON Room A/B
INTEGRATED DESIGN SYSTEMS
Chairperson: Richard BryantCo-Chairperson: Ronald J. Jerdonek
2:00 INVITED
CAE Needs and Solutions for the Mid 80's
D. A. Stamm, Daisy Systems Corp., Sunnyvale, CA
2:25 A CALMA/General Electric VLSI Design CAD SystemK. Vorm, General Electric Co., Binghamton, NY
2:50 A Hierarchical Workstation Design Approach to Custom VLSI
W. R. Blemberg, E. W. Cordan, R. D. Pepple, NCR Microelectronics, Colorado Springs, CO
3:15 An Advanced HCMOS Gate Array Design ApproachD. Soderman, S. Chan, LSI Logic Corp., Milpitas, CA
3:40 IDS—A System for Fast, Hierarchical Design of Handcrafted VLSI Circuits
S. N. Stevens, S. P. McCabe, TRW LSI Products, La Jolla, CA
4:05 Full-Custom Design with ZODIAC System 2
S. Garue, L Silvestri, S. Storti, SGS-ATES Componenti Elettronici SpA, Milano, Italy
4:30 CIPAR—A Complete Correct by Construction Placement and Routing SystemS. Mehta**, M. Ng*, R. Babbar*, R. Kirk**, American Microsystems, Inc., Santa Clara, CA*, American
Microsystems, Inc., Twain Harte, CA**
97
98
99
101
106
107
112
117
MONDAY AFTERNOON Room C/D
APPLICATIONS-NEW TECHNIQUES
Chairperson: Gene E, BlankenshipCo-Chairperson: Sidney Shapiro
2:00 A Very-High Throughput Rate Clocked CMOS Parallel MultiplierB. Hoefflinger*, M. Poliac**, Purdue Univ., West Lafayette, IN*, Univ. of Minnesota, Minneapolis, MN*'
123
124
CONTENTS
MONDAY AFTERNOON Room C/D PAGE
2:25 VLSI Design for a Reed-Solomon Encoder 129
J. T. Johl, California State University, Northridge, CA
2:50 The Vote Tallying Chip—A Custom Integrated Circuit 130
D. Sher, A. Tevanian, University of Rochester, Rochester, NY
3:15 Novel Dynamic Merged Load Technology 135
E. Harari, Wafer Scale Integration, Inc., Santa Clara, CA
3:40 Formal Design Procedures for Pass Transistor Switching Circuits 139
D. Rakhakrishnan*, S. R. Whitaker**, G. K. Maki***, Old Dominion Univ., Norfolk, VA\ AMT, Santa Clara,CA**, Univ. of Idaho, Moscow, ID***
4:05 Random Logic Design Utilizing Single Ended Cascode Voltage Switch Circuit in NMOS 145
C. K. Erdelyi, IBM, Essex Junction, VT
4:30 Optimization of Domino CMOS Logic and Its Applications to Standard Cells 150
J. Pretorius, A. Shubat, C. A. T. Salama, D. A. Smith, University of Toronto, Toronto, Ontario, Canada
MONDAY AFTERNOON Room E/F/G
TESTING IN IC DEVELOPMENT 155
Chairperson: Peter Lloyd
Co-Chairperson: Steve R. Quigley
1:45 TUTORIAL
A Testing Environment for Custom IC Development 156
D. L. Denburg, AT&T Bell Laboratories, Allentown, PA
2:25 INVITED
Automation in Design for Testability 159
V. D. Agrawal, S. K. Jain, D. M. Singer, AT&T Bell Laboratories, Muray Hill, NJ
2:50 A Bus Organized Self-Test Processor Architecture 164
F. C. Wang*, D. D. Bhavsar**, Tektronix, Inc., Beaverton, OR*, Digital Equipment Corp., Hudson, MA**
3:15 Hierarchical Design Verification and Incremental Test of a 100,000 Transistor Integrated Circuit 168
R. J. Clarke, P. Arya, R. J. Potter, G. J. Smith, I. D. Smith, CSIRO VLSI Program, Adelaide, South Australia
3:40 An Integrated IC Test Development System 169
M. Brashler, D. Coleman, R. Dubois, Tektronix, Inc., Beaverton, OR
4:05 Computer Aided Test for VLSI 172
B. Koenemann, J. Ducklow, N. Lanners, T. Vriezen, Honeywell Inc., Plymouth, MN
4:30 Latch-up Analysis in CMOS Static 4K RAMs Using Laser Scanning 176C. Huang, H. Choe, R. Rabe, K. Golke, Honeywell Inc., Plymouth, MN
CONTENTS
MONDAY AFTERNOON Room E/F/G PAGE
4:55 Functional Testing and Failure Analysis of VLSI Using a Laser Probe
F. J. Henley, Spectrum Sciences, Santa Clara, CA181
TUESDAY MORNING Room A/B
ADVANCES IN GATE ARRAYS 187
Chairperson: Jonathan Allen
Co-Chairperson: Daniel F. Daly
9:10 Design Features of a 10K CMOS Gate Array 188
F. Perner, L Roylance, K. Van Bree, Hewlett Packard Labs, Palo Alto, CA
9:35 A CMOS Masterslice Chip with Versatile Design Features 192
F. R. Sporck, V. L. Rideout, R. A. Piro, S. Tom, IBM, Essex Junction, VT
10:00 The Honeywell HT5000 a VLSI Subnanosecond TTL Gate Array 196
D. Bondurant, D. Wick, Honeywell Digital Products Center, Colorado Springs, CO
10:25 A 3500 Gate Bipolar ECL/ITL Array Approaching Standard Cell Density 202
R. C. Yuen, M. P. Huang, Applied Micro Circuits Corp., San Diego, CA
10:50 A 13.5K CMOS Gate Array with 2300 Dedicated Analog Transistors and 200 Multifunctional I/O Cells 206
M. P. Gagliardi, General Electric Co., Research Triangle Park, NC
11:15 An Advanced 11K Gate CMOS Gate Array with Fully Automated Design System 210
T. Nishimura, K. Matsumoto, O. Kudo, M. Murayama, H. Ooka, K. Koyata, F. Tsubokura, NEC Corp., Kawasaki,
Japan
TUESDAY MORNING Room C/D
SIMULATION
Chairperson: Bernd HoeffllngerCo-Chairperson: Gilbert J. DeClerck
8:50 TUTORIAL
Return on Investment in CAD Tools
A. E. Gorlick, W. J. Portelli, ZyCAD Corporation, Morristown, NJ
9:35 Interactive Circuit Simulation and Model Parameter Extraction for the CAD Work Station
A. L Silburt, R. St. Laurent, MOSAID Inc., Kanata, Ont., Canada
10:00 SAMSON: An Event Driven VLSI Circuit Simulator
K. A, Sakallah*, S. W. Director**, Digital Equipment Corp.*, Carnegie-Mellon University, Pittsburgh, PA*
215
216
221
226
CONTENTS
TUESDAY MORNING Room C/D PAGE
10:25 Relax 2.1: A Waveform Relaxation Based Circuit Simulation Program 232
J. White, A. L. Sangiovanni-Vincentelli, University of California, Berkeley, CA
10:50 Continuous Expansion Methods in Computer Aided Circuit Analysis 237
0. A. Palusinski, University of Arizona, Tucson, AZ
11:15 Low Cost Hardware Logic Simulator/Fault Grade Machine 242
J. T. Marino, Jr., Motorola, Inc., Scottsdale, AZ
TUESDAY MORNING Room E/F/G
APPLICATIONS—COMMUNICATIONS 245
Chairperson: Ken Parulski
Co-Chairperson: Harold L. Scalf
9:10 Full Custom LSI/VLSI Design Manpower Model 246
C. F. Fey, Xerox Corporation, Rochester, NY
9:35 Data Modem for Mobile VHF/UHF Radio Applications 251
T. Foxall*, P. Driessen**, Pacific Microcircults Ltd., White Rock, B.C., Canada*, MDI Mobile Data International
Inc., Richmond, B.C., Canada**
10:00 A Single Chip 1200 BPS MSK Modem for Multi Channel Access 255
K. Gotoh, T. Yamamura, T. Saito, A. Itoh, T. Shirato, Fujitsu Limited, Kawasaki, Japan
10:25 An Integrated Single-Sideband Modulator/Demodulator tor an FDM System 260
R. Gregorian*, B. Fotouhi*, L. Engh**, AMI, Santa Clara, CA*, Harris Corp., San Carlos, CA**
10:50 A Switched Capacitor Adaptive Line Equalizer for a High-Speed Digital Subscriber Loop 264
Y. Kuraishi, Y, Takahashi, K. Nakayama, T. Senba, NEC Corporation, Kawasaki, Japan
11:15
^r?zmtfowmsxxzl. «. to„v
11:40 nMOS Multiplexer for Fiber OpticsY. C. Jeung, J. C. Daly, University of Rhode Island, Kingston, Rl
269
CONTENTS
TUESDAY MORNING Theater PAGE
IC TESTING, QUALIFICATION, AND RELIABILITY 275
Chairperson: David E. Brown
Co-Chairperson: James J. Whalen
8:50 TUTORIAL
Survey of VLSI Test Strategies 276
A. K. Susskind, Lehigh University, Bethlehem, PA
9:35 INVITED
Semiconductor Component Quality 281
H. S. Lehman, H. J. Jones, IBM, White Plains, NY
10:00 On-Chip Testing of Embedded RAMs 286
P. Varma, A. P. Ambler, K. Baker, University of Manchester Institute of Science & Technology, Manchester,
United Kingdom
10:25 Testing of Analog Mask Programmable IC's 291
D. B. Cox, Lode Systems, Inc., Santa Clara, CA
10:50 Military Specification, Qualification, and Testing of VLSI 295
J. R. Haberer, M. S. Karlovic, United States Air Force, Griffiss AFB, NY
11:15 The Role of Design Automation Systems in IBM GTD Bipolar Product Qualifications 300
K. Y. Enright, B. J. Van Auken, IBM, Poughkeepsie, NY
11:40 Reliability in a Custom Integrated Circuit Environment 305
R. Goetz, Tektronix, Inc., Beaverton, OR
TUESDAY AFTERNOON Room A/B
MODELLING 309
Chairperson: Hoda S. Abdel-Aty-ZohdyCo-Chairperson: Jagdish C. Tandon
2:00 Table Models for Timing Simulation 310
P. Subramaniam, AT&T Bell Laboratories, Murray Hill, NJ
2:25 Scaling of the DC Drain Current and Intrinsic Charges with Channel Length for MOS Transistors 315
D. Divekar, ZyMOS Corp., Sunnyvale, CA
2:50 Technology Independent and Automatic Device Model Generation for Custom IC's 319
G. Bischoff, J. P. Krusius, Cornell University, Ithaca, NY
3:15 Computer Aided Design in VLSI Device Development 324
K. M. Cham, S. Y. Oh, Hewlett Packard Laboratories, Palo Alto, CA
3:40 Automated MOSFET Impurity Profile Design 329
R. C. Jaeger, Auburn University, Auburn, AL
CONTENTS
TUESDAY AFTERNOON Room A/B PAGE
4:05 Modelling Effective Source Resistance of a Short-Channel MOSFET 335
J. S. Kim*, H. C. Lin**, Westinghouse Electric Corp., Baltimore, MD*
Univ. of Maryland, College Park, MD**
4:30 A Quasiequilibrium Approach to MOSFET Modeling 339
D.-H. Ju, R. M. Warner, Jr., University of Minnesota, Minneapolis, MN
TUESDAY AFTERNOON Room C/D
DESIGN SYNTHESIS 345
Chairperson: Alberto Sangiovanni-VincentelllCo-Chairperson: James L. Dunkley
2:00 Automated Implementation of Switching Functions as Dynamic CMOS Circuits 346
R. K. Brayton, C. L. Chen, C. T. McMullen, R. H. J. M. Otten, J. Y. Yamour, IBM, Yorktown Heights, NY
2:25 Performance Prediction with the MacPitts Silicon Compiler 351
J. R. Fox, GTE Laboratories, Inc., Waltham, MA
2:50 An Automatic Logic Synthesizer for Integrated VLSI Design System 356
T. Hoshino, M. Endo, O. Karatsu, Atsugl Electrical Communication Lab, Kanagawa, Japan
3:15 Direct Implementation of State Diagram Specifications 361
L Spaanenburg, G. Kleissen, H. van der Veen, Twente University of Technology, Enschede, The Netherlands
3:40 Automated Design Approach to an NMOS LSI Circuit 366
J. T. O'Connor, G. R. Brown, C. Hoac, Texas Instruments, Inc., Houston, TX
4:05 EXPRESSO-II: A New Logic Minimizer for Programmable Logic Arrays 370
R. K. Brayton*, G. D. Hachtel**, K. McMullen***, A. Sangiovanni-Vincentelli****, IBM, Yorktown Heights, NY*,
Univ. of Colorado, Boulder, CO**, Harvard Univ., Cambridge, MA***, University of California, Berkeley,CA****
4:30 A P.L.A. Synthesis System 377
G. Puggelli, Honeywell Information Systems Italia, Milano, Italy
CONTENTS
TUESDAY AFTERNOON Room E/F/G PAGE
SIGNAL PROCESSING AND FILTERS 383
Chairperson: David M. Lewis
Co-Chairperson: Tom Foxall
1:45 TUTORIAL
The Future Role of Analog Processing in Custom Circuits 384
R. W. Brodersen, University of California, Berkeley, CA
2:25 2 Micron CMOS Digital Signal Processors 385
M. Sugai, M. Miyata, M. Shirakawa, M. Suzuki, E. Nishihara, K. Aoki, S. Kawasaki, Toshiba Corp., Kawaski,Japan
2:50 Custom CMOS Digital Correlators by Mask Programming 390
S. Renjen, R. Zinser, TRW LSI Products, La Jolla, CA
3:15 Design and Implementation of FIR Filter Structures Using Standard Cell Techniques 394
R. J. Inkol*, K. D. Symons**, P. D. Clarke**, Defence Research Est., Ottawa, Ont, Canada*, Calmos Systems, /
Inc., Kanata, Ont., Canada**
3:40 A Narrowband Charge Domain Bandpass Filter 399
T. L. Vogelsong*, A. J. Steckl**, J. J. Tiemann*, General Electric Co., Schenectady, NY*, Rensselaer
Polytechnic Institute, Troy, NY**
4:05 A "Z" Plane Lerner Switched Capacitor Filter 404
A. Lish, Standard Microsystems Corp., Hauppauge, NY
TUESDAY EVENING Room A/B
8:00 TUESDAY EVENING PANEL 409
"System Design vs. IC Design"Why Can't Just Anyone Design a Custom Integrated Circuit?
Moderator: Dave Brown, IC Design Manager, MITEL Corporation
Panelists: Paul Russo, General Manager, GE Microelectronics Center
Merrill Brooksby, Manager, VLSI CAD & Applications Operation, GE Corporate Research &
Development Center
Bill Hoffman, Senior Engineer, Micro-Processor Design, IBM
Binoy Rosario, Design Manager, Tektronix, Inc.
Chuck Gwinn, Acting General Manager, United Technologies Microelectronics Center
Brenda Bittner, Manager, VLSI Design Engineering, Xerox, Corporation
CONTENTS
TUESDAY EVENING Room C/D PAGE
8:00 TUESDAY EVENING PANEL 411
"Workstations vs. Mainframe Software Systems"
Moderator: Greg Ledenbach, Product Line Manager, Semicustom Options, National Semiconductor
Panelists: Avyeh Finegold, President, Daisy SystemsGraham Shenton, Vice President of Marketing & Engineering Design Systems, I.M.P.
Sheldon Larson, Engineering Manager, Universal Semiconductor
Jim Lipman, Manager of Training and Foundry Development, V.T.I.
TUESDAY EVENING Room E/F/G
8:00 TUESDAY EVENING PANEL 413
"The Ultimate Cost of Integrated Circuit Quality"
Moderators: William H. Becker, AT&T Bell Laboratories
Stephen R. Quigley, IBM
Panelists: Irv Roth, Director of Quality Assurance, Burroughs CorporationC. Mark Melliar-Smlth, Director of Engineering, Kansas City Works, AT&T TechnologiesRob Walker, Vice President of Engineering, LSI Logic CorporationHerb Lehman, Director of Product Assurance and Quality, IBM—General Technology Division
Jack Cotton, Director of Advanced System Architecture, ITT
Dave Shaver, Microelectronics Staff, MIT Lincoln Laboratory
WEDNESDAY MORNING Room AB
LAYOUT SO FTWARE 415
Chairperson: James L. DunkleyCo-Chairman: Sidney Shapiro
9:10 A Custom Circuit Netlist Extractor with Detailed Parasitic Measurement and Node Identification 416
D. E. Krekelberg, Sperry Corporation, St. Paul, MN
9:35 Computer Evaluated Layout Design Rules for Integrated Circuits 420
C. Beck, Synertek, Inc., Santa Clara, CA
10:00 An Automated System for CMOS Layout Rule Generation and Analysis 425C. Groves, M.-A. Caux, M. Pigeon, Mitel Semiconductor, Bromont, Quebec, Canada
10:25 Extraction of Interconnect Delays from Computer Generated LayoutsJ. D. Mastroianni, RCA, Somerville, NJ
430
CONTENTS
WEDNESDAY MORNING Room A/B PAGE
DESIGN SYSTEM INTEGRATION 435
Chairperson: Allan L. Goodman
Co-Chairperson: Alberto Sangiovanni-Vincentelli
10:50 A Practical Application of Data Modelling to Design System Integration 436
K. R. Bennett, Standard Telecommunication Labs, Ltd., Harlow, Essex, United Kingdom
11:15 Conceptual Data Model for a Custom IC Design System 441
R. Raghavan, Mentor Graphics Corp., Beaverton, OR
11:40 EDIF: A Mechanism for the Exchange of Design Information 446
J. D. Crawford, Tektronix, Inc., Beaverton, OR
WEDNESDAY MORNING Room C/D
ADVANCED FABRICATION 451
Chairperson: Kris B. Verma
Co-Chairperson: James F. Maynard
8:50 TUTORIAL
Electron-Beam techniques for Integrated Circuit Testing and Customization 452
D. C. Shaver, MIT, Lincoln Labs, Lexington, MA
9:35 Reconfiguring Semi-custom IC's Using Laser Microchemical Techniques 453
W. S. Graber*, D. J. Ehrlich**, J. Y. Tsao**, D. J. Silversmith**, J. H. C. Sedlacek**, R. W. Mountain**, Gould,Rolling Meadows, IL\ MIT, Lincoln Labs, Lexington, MA**
10:00 Bipolar Logic Gates for ULSI Applications 457
E. H. Stevens, Honeywell Inc., Plymouth, MN
GATE ARRAY CIRCUIT TECHNIQUES 463
Chairperson: Charles K. ErdelyiCo-Chairperson: Marc D. Hartranft
10:25 A Highly Efficient Gate Array Architecture 464
L Finegold, V. Schnathorst, T. Adams, C. Freymuth, UTMC, Colorado Springs, CO
10:50 The Development of Interface LSI 468
A. Mizuno, S. Hososaka, M. Enomoto, T. Ohba, T. Nakao, Hitachi, Ltd., Tokyo, Japan
11:15 A Plastic Packaged 1600 GateTTL Type Gate Array 472
Y. Suzuki*, S. Kadono*, M. Yoshimura*, I. Masuda**, M. Iwamura**, Hitachi Takasaki Works, Gunma, Japan*,Hitachi Research Laboratory, Ibaragl, Japan**
CONTENTS
WEDNESDAY MORNING Room E/F/G PAGE
APPLICATIONS—COMPUTATION AND DISK DRIVERS 477
Chairperson: Wesley A. Vincent
Co-Chairperson: Ken Parulski
9:10 A Floating Point Unit for a 32b Microprocessor System 478
B. Simcoe, B. Bidermann, G. Wolrich, A. Fisher, E. McLellan, M. Leary, D. Forsythe, J. Montanaro, B. Wheeler,
B. Yodlowski, L. Harada, Digital Equipment Corp., Hudson, MA
9:35 Custom-VLSI on DPS4 Architecture 482
A. Ramolini, Honeywell Information Systems Italia, Milano, Italy
10:00 A Custom Data Conversion IC for Personal Computers 487
I. Miller*, J. Prickett**, Motorola, Tempe, AZ*, Radio Shack, Fort Worth, TX**
10:25 A Servo Control IC for Small Disk Drives 492
R. Hester, J. Shier, Control Data Corp., Bloomlngton, MN
10:50 A Single Chip Floppy Disk Drive Subsystem IC 496
T. Gotoh, J. Itoh, Y. Funada, T. Okabe, Mitsubishi Electric Corp., Hyogo, Japan
11:15 A Frequency Lock Loop for DC Brushless Motor Speed Control 501
T. Glad, Silicon Systems, Nevada City, CA
11:40 A PLL IC for Magnetic Disk Drives 506
N. Takagi, N. Nakamura, T. Yuyama, M. Fujiki, Toshiba Corporation, Kawasaki, Japan
WEDNESDAY AFTERNOON Room A/B
AUTOMATED IC LAYOUT 511
Chairperson: Gregory W. Ledenbach
Co-Chairperson: Allan L. Goodman
2:00 CMOS Cell-Layout Compilers for Custom IC Design 512
D. Edginton, B. Walker, S. Nance, C. Starr, S. Dholakia, M. Kliment, VLSI Technology, Inc. (VTI), San Jose, CA
2:25 Automatic Layout of Gate Arrays 518
J. T. Li, C. K. Cheng, M. Turner, E. S. Kuh, M. Marek-Sadowska, Univ. of California, Berkeley, CA
2:50 The TimberWolf Placement and Routing Package 522
C. Sechen, A. Sangiovanni-Vincentelli, University of California, Berkeley, CA
3:15 Hierarchical Layout Using a Standard Cell Router 528
R. W. Muir, L. J. Specter, Raytheon Co., Sudbury, MA
3:40 A CAD System for Current Distribution Analysis on Gate Arrays 533
H. Kato, H. Yoshizawa, S. Ito, K. Yamada, H. Kawanishi, NEC Corp., Kawasaki, Japan
CONTENTS
WEDNESDAY AFTERNOON Room C/D PAGE
ANALOG TECHNIQUES 539
Chairperson: Douglas Barber
Co-Chairperson: Jagdish C. Tandon
1:45 TUTORIAL
The Operational Amplifier in Custom LSI Design—A Tutorial Study 540
A. B. Grebene, Micro-Linear Corp., Sunnyvale, CA
2:25 The "Quick-Chip": A Comprehensive System for Fast Prototyping of High-Speed Custom Analog IC's 546
W. Gross, Tektronix, Inc., Beaverton, OR
2:50 Analog Master Chip—A Versatile Analog Array 551
P. K. Sun, C. F. Chiou, Magnetic Peripherals, Inc., Minneapolis, MN
3:15 Design of a Custom IC for a Disc Camera 554
R. Alessi, L. Hudson, Eastman Kodak Co., Rochester, NY
3:40 A Frequency-Ratio Based 12-bit MOS Precision Binary Current Source 555
E. D. Kwong, G. L Baldwin, T. Hornak, Hewlett-Packard Labs, Palo Alto, CA
4:05 A CMOS Pipeline Algorithmic A/D Converter 559
S. Masuda, Y. Kitamura, S. Ohya, M. Kikuchi, NEC Corporation, Kawasaki, Japan
WEDNESDAY AFTERNOON Room E/F/G
INTERFACE TECHNOLOGY 563
Chairperson: Peter M. Zeitzoff
Co-Chairperson: Jack S. T. Huang
2:00 A Monolithic Capacitor-Coupled Gate Input High Voltage SOS/CMOS Driver Array 564
H. Sakuma, K. Hirata, NEC Corporation, Kawasaki, Japan
2:25 Optimized ESD Protection Circuits for High-Speed MOS/VLSI 569
E. Fujishin*, K. Garrett*, M. Levis*, R. Motta*, M. Hartranft**, Zilog, Inc., Campbell, CA*, CypressSemiconductor Corp., Santa Clara, CA**
2:50 FET Off-Chip-Drivers and Package Disturbs 574N. Raver, IBM Corporation, Yorktown Heights, NY
3:15 Layer to Layer Interconnections: Impact on VLSI Circuits 580
H. B. Harrison*, G. Sai-Halasz**, G. K. Reeves***, Royal Melbourne Inst of Tech., Melbourne, Australia*, IBM,Yorktown Heights, NY**, Telecom Australia***
3:40 A New Latch-up Resistant CMOS Buffer with a Novel TTL Input Stage 584
R. Woodruff, D. Hawley, V. Schnathorst, J. Arreola, UTMC, Colorado Springs, CO