csee 3827: fundamentals of computer systems, spring 2011 6...
TRANSCRIPT
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CSEE 3827: Fundamentals of Computer Systems, Spring 2011
6. Memory Arrays
Prof. Martha Kim ([email protected])Web: http://www.cs.columbia.edu/~martha/courses/3827/sp11/
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Outline (H&H 5.5-5.6)
2
• Memory Arrays
• RAM, ROM, SRAM, DRAM
• Logic Arrays
• Programmable Logic Arrays (PLAs)
• Field-Programmable Gate Arrays (FPGAs)
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Address
Read
Enable
DataIn
DataOut
k
n
n
2 wordsn bits per word
k
MEMORY
Memory interface
• Stores data in word units
• A word is several bytes (16-, 32-, or 64-bit words are typical)
• write operations store data to memory
• read operations retrieve data from memory
3
An n-bit value can be read from or written to each k-bit address
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Memory Array: Example
• 22 × 3-bit array
• Number of words: 4
• Word size: 3-bits
• For example, the 3-bit word stored at address 10 is 100
4
Copyright © 2007 Elsevier
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Memory array architecture (1)
5
wordline311
10
2:4Decoder
Address
01
00
storedbit = 0wordline2
wordline1
wordline0
storedbit = 1
storedbit = 0
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
bitline2 bitline1 bitline0
Data2 Data1 Data0
2
Memory is a 2D array of bits. Each bit stored in a cell.
cell
Copyright © 2007 Elsevier
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Memory array architecture (2)
6
wordline311
10
2:4Decoder
Address
01
00
storedbit = 0wordline2
wordline1
wordline0
storedbit = 1
storedbit = 0
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
bitline2 bitline1 bitline0
Data2 Data1 Data0
2
Address is decoded into set of wordlines. Wordlines select row to be read/written. Only one wordline=1 at a time.
Copyright © 2007 Elsevier
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Memory array architecture (3)
7
wordline311
10
2:4Decoder
Address
01
00
storedbit = 0wordline2
wordline1
wordline0
storedbit = 1
storedbit = 0
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
bitline2 bitline1 bitline0
Data2 Data1 Data0
2
When reading, contents of word written to bitlines.
Copyright © 2007 Elsevier
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Memory cell abstraction
8
stored bit
wordlinebitline
Copyright © 2007 Elsevier
wordline stored bit bitline
0 x Z
1 0 0
1 1 1
Cell is base element of memory that stores a single bit
Implementation of cell varies with type of memory.
Implemented with a tristate buffer. Value “Z” does not drive output wire to either a 0 or 1.
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Types of memory
Volatile (data lost on power off)
Fast reads and writes
Historically called RAM because equal time to read/write all addresses (in contrast to serial-access devices such as a hard disk or tape). Somewhat misleading as ROM also can have uniform access time.
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Non-volatile (retains data when powered off)
Fast reads, writing is impossible or slow (again, misleading name)
Historically called ROMs because written by permanently blowing fuses (so rewriting was impossible). Modern ROMs, such as flash memory in iPod are rewritable, just slowly.
Random access memory (RAM) Read-only memory (ROM)
Dynamic RAM (DRAM) Static RAM (SRAM)Cell stores data w. capacitors
Cell stores data w. cross-coupled inverters
wordline
bitline
storedbit
wordlinebitline bitline
ROMMask-programmed (at chip fab)
PROMFuse- or antifuse-programmed
FLASH
Electrically erasable floating gate with multiple erasure and programming modes
Copyright © 2007 Elsevier
Hard Disk
Flip-flop Register
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Volatile storage (RAM) comparisons
10
Flip-flop SRAM DRAM
Transistors / bit ~20 6 1
Density Low Medium High
Access time Fast Medium Slow
Destructive read? No No Yes (refresh required)
Power consumption High Medium Low
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Storage hierarchy
11
Main memory
(DRAM)
Non-volatile storage
(Hard disk or
solid-state drive)
CPU Cache
(SRAM)Registers
Fast access to small amount of data
Slow access to large amount of data
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Bottom-up examination of SRAM circuits
12
wordline311
10
2:4Decoder
Address
01
00
storedbit = 0wordline2
wordline1
wordline0
storedbit = 1
storedbit = 0
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
bitline2 bitline1 bitline0
Data2 Data1 Data0
2
Copyright © 2007 Elsevier
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Bottom-up examination of SRAM circuits (2)
13
wordline311
10
2:4Decoder
Address
01
00
storedbit = 0wordline2
wordline1
wordline0
storedbit = 1
storedbit = 0
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
bitline2 bitline1 bitline0
Data2 Data1 Data0
2
Copyright © 2007 Elsevier
Bits stored in cells (modeled by an SR latch)
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Bottom-up examination of SRAM circuits (3)
14
wordline311
10
2:4Decoder
Address
01
00
storedbit = 0wordline2
wordline1
wordline0
storedbit = 1
storedbit = 0
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
bitline2 bitline1 bitline0
Data2 Data1 Data0
2
Cells wired into bitslices.
Copyright © 2007 Elsevier
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Bottom-up examination of SRAM circuits (4)
15
wordline311
10
2:4Decoder
Address
01
00
storedbit = 0wordline2
wordline1
wordline0
storedbit = 1
storedbit = 0
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
bitline2 bitline1 bitline0
Data2 Data1 Data0
2
Block diagram of a bitslice
Copyright © 2007 Elsevier
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Bottom-up examination of SRAM circuits (5)
16
wordline311
10
2:4Decoder
Address
01
00
storedbit = 0wordline2
wordline1
wordline0
storedbit = 1
storedbit = 0
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
bitline2 bitline1 bitline0
Data2 Data1 Data0
2
Address decoded to select one row of bitslice
for read/write
Copyright © 2007 Elsevier
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Bottom-up examination of SRAM circuits (6)
17
wordline311
10
2:4Decoder
Address
01
00
storedbit = 0wordline2
wordline1
wordline0
storedbit = 1
storedbit = 0
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
bitline2 bitline1 bitline0
Data2 Data1 Data0
2
To increase word size, add bitslices.
Copyright © 2007 Elsevier
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Coincident cell selection
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• Decode address into both row and column select signals
• How many words in this RAM?
• How many bits per word?
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Coincident cell selection w. larger words
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• How many words in this RAM?
• How many bits per word?
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Coincident cell selection saves decode logic
20
32K
wor
ds
1 byte
STORAGECOLUMN
15-b
it ad
dres
s
(32,800 gates)
DECODER
512
wor
ds
1 byte9-
bits
of a
ddre
ss
DECODER#1
STORAGE COLUMNS
...
...64 column selects...
… 3
2,76
8 ro
w s
elec
ts ..
.
… 5
12 ro
w s
elec
ts ..
.
DECODER #2
6-bits of address(608 gates)
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Multi-chip memories
• If you need a larger memory than any available chip
• Wire multiple RAM chips together to work in concert as one large memory
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ROMs: Dot Notation
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Data2 = A1 ! A0
Data1 = A1 + A0
Data0 = A1A0
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Example: Logic with ROMs
• Implement the following logic functions using a 2^2 × 3-bit ROM:
• X = AB
• Y = A + B
• Z = AB
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Logic with Any Memory Array
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• X = AB
• Y = A + B
• Z = AB
Called lookup tables (LUTs): look up output at each input combination (address)
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Multi-ported Memories
• Port: address/data pair
• 3-ported memory
• 2 read ports (A1/RD1, A2/RD2)
• 1 write port (A3/WD3, WE3 enables writing)
• Small multi-ported memories are called register files
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Logic Arrays: PLAs
• Programmable logic arrays (PLAs)
• AND array followed by OR array
• Perform combinational logic only
• Fixed internal connections
• Example
• X = `A`BC + AB`C
• Y = A`B
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Logic Arrays: FPGAs
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• FPGAs are composed of:
• CLBs (Configurable logic blocks): perform logic, are composed of:
• LUTs (lookup tables): perform combinational logic
• Flip-flops: perform sequential functions
• Multiplexers: connect LUTs and flip-flops
• IOBs (Input/output buffers): interface with outside world
• Programmable interconnection: connect CLBs and IOBs
• Some FPGAs include other building blocks such as multipliers and RAMs