cse140l: components and design techniques for digital...
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CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab
Timing, Mux, Demux, Adders
Tajana Simunic Rosing
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Outline• Non-ideal gate behavior (3.5)
– Rise/fall time– Delay– Pulse width
• Pass gates (Appendix B)g ( pp )• Muxes & Demuxes (chap 4.2 pp. 171-183)• Adders (chap 5.6)
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Charge/discharge in CMOSg g• Calculate on resistance• Calculate capacitance of the gates circuit is drivingCalculate capacitance of the gates circuit is driving• Get RC delay & use it as an estimate of circuit delay
– Vout = Vdd ( 1- e-t/RpC)
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Source: Prof. Subhashish Mitra
Time behavior of combinational networks• Waveforms
– visualization of values carried on signal wires over timeg– useful in explaining sequences of events (changes in value)
• Simulation tools are used to create these waveforms– input to the simulator includes gates and their connectionsinput to the simulator includes gates and their connections– input stimulus, that is, input signal waveforms
• Some terms– gate delay — time for change at input to cause change at output– gate delay — time for change at input to cause change at output
• min delay – typical/nominal delay – max delay• careful designers design for the worst case
– rise time — time for output to transition from low to high voltagep g g– fall time — time for output to transition from high to low voltage– pulse width — time that an output stays high or stays low between changes
Non-Ideal Gate Behavior – Delay
a Fa F
a
F
a
Time
• Real gates don’t respond immediately to input changes– Rise/fall time
Delay
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– Delay– Pulse width
Waveform view of logic functionsg• Just a sideways truth table
– but note how edges don’t line up exactly
time
g p y– it takes time for a gate to switch its output!
time
6change in Y takes time to "propagate" through gates
Momentary changes in outputsy g p• Can be useful — pulse shaping circuits• Can be a problem — incorrect circuit operation
FA B C D
Can be a problem incorrect circuit operation (glitches/hazards)
• Example: pulse shaping circuitF– A’ • A = 0
– delays matter
F i l 0D remains high for
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F is not always 0pulse 3 gate-delays wide
D remains high forthree gate delays after
A changes from low to high
Oscillatory behavior
+
y• Another pulse shaping circuit
open switch
resistorA B
C
initially
close switch
switch D
initially undefined
open switch
CSE140: Components and Design Techniques CSE140: Components and Design Techniques for Digital Systems
Muxes and demuxes
Tajana Simunic Rosing
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Pass transistor – Mux building block
• Connects X & Y when A=1, else X & Y disconnected– A_b = not(A)
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Fig source: Prof. Subhashish Mitra
Multiplexor (Mux)p ( )• Mux routes one of its N data inputs to its one output,
based on binary value of select inputsy p• 4 input mux needs 2 select inputs to indicate which input to route
through• 8 input mux 3 select inputs • N inputs log2(N) selects
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Mux Internal Design
2×1
i0
2×1
i02×1
i0A YA Ai1i0
s01
di1i0
s00
di1i0
s0
dAB Y YA
BAB
2x1 mux
• Selects input to connect to Y– selA == 1: connects A to Y– selB == 1: connects B to Y
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Fig source: Prof. Subhashish Mitra
Multiplexers/selectorsp• 2:1 mux: Z = A'I0 + AI1• 4:1 mux: Z = A'B'I0 + A'BI1 + AB'I2 + ABI34:1 mux: Z A B I0 + A BI1 + AB I2 + ABI3• 8:1 mux: Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +
AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
2 -1I0I1k=0
n• In general: Z = Σ (mkIk)I1I2I3I4I5
8:1mux
Z
I0
0
– in minterm shorthand form for a 2n:1 Mux
I5I6I7
A B C
I0I1I2I3
4:1mux
ZI0I1
2:1mux Z
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A B CA BA
N-bit Mux Examplep
• Four possible display itemsT t (T) A il ll (A) I t t (I)– Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles remaining (M) -- each is 8-bits wide
– Choose which to display using two inputs x and y– Use 8-bit 4x1 mux
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Use 8 bit 4x1 mux
Multiplexers as general-purpose logicp g p p g• A 2n-1:1 multiplexer can implement any function of n variables
– with n-1 variables used as control inputs and– the data inputs tied to the last variable or its complement
• Example: F(A,B,C) = m0 + m2 + m6 + m7
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Demultiplexers/decodersp• Decoders/demultiplexers: general concept
– single data input, n control inputs, 2n outputsg p , p , p– control inputs (called “selects” (S)) represent binary index of
output to which the input is connected– data input usually called “enable” (G)
1:2 Decoder:O0 = G • S’O1 = G • S 3:8 Decoder:
data input usually called enable (G)
O1 = G • S
2:4 Decoder: O0 = G • S1’ • S0’
3:8 Decoder: O0 = G • S2’ • S1’ • S0’O1 = G • S2’ • S1’ • S0O2 = G • S2’ • S1 • S0’O3 = G • S2’ • S1 • S0O0 = G • S1 • S0
O1 = G • S1’ • S0O2 = G • S1 • S0’O3 = G • S1 • S0
O3 = G • S2 • S1 • S0O4 = G • S2 • S1’ • S0’O5 = G • S2 • S1’ • S0O6 = G • S2 • S1 • S0’O7 = G • S2 • S1 • S0
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O7 = G • S2 • S1 • S0
Gate level implementation of demultiplexersp p• 1:2 decoders
• 2:4 decoders
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Demultiplexers as general-purpose logic (cont’d)
• F1 = A'BC'D + A'B'CD + ABCD• F2 = ABC'D' + ABC• F3 = (A' + B' + C' + D')
0 A'B'C'D'1 A'B'C'D2 A'B'CD'3 A'B'CD4 A'BC'D'5 A'BC'D6 A'BCD'7 A'BCD7 A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11 AB'CD
4:16DECEnable
11 AB CD12 ABC'D'13 ABC'D14 ABCD'15 ABCD
18A B C D
Mux and demux combination• Uses in multi-point connections
B0 B1A0 A1
multiple input sourcesMUX
A B
Sa SbMUX
A B
Sum
multiple output destinationsSs DEMUX
19S0 S1
Mux example: Logical function unitp g• Multi-purpose function block
– 3 control inputs to specify operation to perform on operandsp p y p p p– 2 data inputs for operands– 1 output of the same bit-width as operands
C0 C1 C2 Function Comments0 0 0 1 always 1 00 0 0 1 always 10 0 1 A + B logical OR0 1 0 (A • B)' logical NAND0 1 1 A xor B logical xor
1234
8:1 MUXF
1 0 0 A xnor B logical xnor1 0 1 A • B logical AND1 1 0 (A + B)' logical NOR1 1 1 0 always 0
4567S2 S1 S0
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1 1 1 0 always 0
C2C0 C1
CSE140: Components and Design Techniques CSE140: Components and Design Techniques for Digital Systems
Arithmetic circuits
Tajana Simunic Rosing
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Example: 4-bit binary adderp y• Inputs: A, B, Carry-in• Outputs: Sum Carry-out A A A A A
CinCout
Outputs: Sum, Carry out
AB
Cout
S
A A A A AB B B B B
S S S S S
CinCout
a3
FA
b3 a2b2
cibaFA
ciba
a1b1
FAciba
a0 b0 ci
FAciba
co s
co s3 s2 s1
co s co s
s0
co s
(a)
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Ripple-carry adder critical delay pathAB
Cin Cout
@0@0
@N
@1 @N+1 4 stageadder
A0
0
S0 @2
pp y y p
AB
Cout@0@0
@
@1
@N+2 B0
A1B1
C1 @2
S1 @3C2 @4late
arrivingsignal
two gate delaysto compute Cout
B1
A2B2
C2 @4
S2 @5C3 @6B2
A3B3
C3 @6
S3 @7Cout @8
S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid
Cout @8
23T0 T2 T4 T6 T8
Carry-lookaheady• Evaluate Sum and Ci+1
– Sum = Ai xor Bi xor Ci – Ci+1 = Ai Bi + Ai Ci + Bi Ci
= Ai Bi + Ci (Ai xor Bi)
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Carry-lookahead implementationy p• Adder with propagate and generate outputs
Pi @ 1 gate delay
Ci Si @ 2 gate delays
BiAi
increasingly complexlogic for carries
C0
C0C0
P0P1P2P3
Gi @ 1 gate delay
C0
C0
C0P0
P0
P0G0
G0G0
C1 @ 3P1
P1
P1
G1P2
P2
P2
P2
P3
P3
G3
P0
G0P1
P1
G1
G1
C2 @ 3
P2
P2 G2
G2
C3 @ 3
P3
P3C4 @ 3
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Carry-lookahead implementation (cont’d)y p ( )• Carry-lookahead logic generates individual carries
– sums computed much more quickly in parallelh t f l i i ith t
0 A0B0
0
S0 @2
– however, cost of carry logic increases with more stages
A0B0
S0 @2C1 @2 A1
B1
C1 @3
S1 @4
A1B1
S1 @3C2 @4 A2
B2
C2 @3
S2 @4
A2B2
S2 @5
3
C3 @6
S3 @
A3B3
C3 @3
S3 @4
C4 @3 C4 @3
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A3B3
S3 @7Cout @8
C4 @3 C4 @3
Carry-lookahead adderwith cascaded carry lookahead logicwith cascaded carry-lookahead logic
• Carry-lookahead adder4 four bit adders with internal carry lookahead
G = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0
4 44 44 44 4
– 4 four-bit adders with internal carry lookahead– second level carry lookahead unit extends lookahead to 16 bits
P = P3 P2 P1 P0
A[15-12] B[15-12]C12
A[11-8] B[11-8]C8
A[7-4] B[7-4]C4
A[3-0] B[3-0]C0@0
4 4
P G
4-bit Adder
4 4
P G
4-bit Adder
4 4
P G
4-bit Adder
4 4
P G
4-bit Adder
@3@2@4
@3@2@5
@3@2@5
@3@2S[15-12] S[11-8] S[7-4]
@7@8@8S[3-0]
@4
4444
Lookahead Carry UnitC0
P0 G0P1 G1P2 G2P3 G3 C3 C2 C1
C0
P3-0 G3-0
C4
@@
@4 @0C16
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P3-0 G3-0@5@3
C1 = G0 + P0 C0C2 = G1 + P1 G0 + P1 P0 C0
Carry-select addery• Redundant hardware to make carry calculation go faster
– compute two high-order sums in parallel while waiting for carry-ini i i 0 d th i i i 1– one assuming carry-in is 0 and another assuming carry-in is 1
– select correct result once carry-in is finally computed
4-bit adder[7:4]
1C8 adderhigh
0C8adder
low
4-bit adder[7:4]
4-Bit Adder[3:0]
C0C4five2:1 mux
0101010101
28C8 S7 S6 S5 S4 S3 S2 S1 S0
What we’ve covered thus far
• Xilinx Virtex II Pro board and tools• Transistor design• Delay estimates• Pass transistors• Muxes• Demuxes• Demuxes• Adders
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