H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012

CSA avec reset pour s-CMS, bruit en temporel

(Up-Grade TRACKER) (Asic R&D Version 1)

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 2

CSA Requirements

Qin = 1.2 fC to 10 fC (7.5 ke- , 62 ke-) Charge Collection Time = 10ns Cd = 5pF Power supply < 200 µW/amplifier F_slhc = 20 Mhz (version 1) or 40 Mhz Output pulse < 50ns

S/N = 20 (before irradiation) ENC = 700 e- if Q = 15000 e- = 2.4 fC (before irradiation)

Q is the most probable value for a Landau distribution of input charge

S/N = 10 (after irradiation) ENC = 700 e- if Q = 7500 e- = 1.2 fC (after irradiation)

Front-End in AC coupling mode

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 3

Schematic - Power Supply

115µA

10µA

Idet

X10

10µA

IBM 130nm Process

Power supply measurements @ 1.6V NMOS input transistor : 143 µA (including

bias current) Bias current cascode : 28 µA SF output : 200 µA

CSA Power Supply 171 µA (274 µW) compared to 253 µW in schematic simulation

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 4

Noise in a Non Switched CSA

Cd

-+

Cf

Votage Noise

Current Noise

HzVf

Aen /

2

2

HzAin /2

20022,_ ,

4Vin

C

CGev

fd

nennoiseout

22

2,_ ,

*4

*Vin

C

Riv

f

fninnoiseout

Rf

• Rf is a noiseless resistor• G0w0 : GBW of amplifier

Equation 1Equation 2

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 5

Noise in Switched CSA

Cd

-+

Cf

Votage Noise

Current Noise

HzVf

Aen /

2

2

HzAin /2

200220022,_ ,

41

*400 Vin

C

CGee

k

Gev

fd

nkTinG

nennoiseout

d

fC

CknsTin ,25

22

2

002

22

,_ ,22

3

2VinT

C

i

C

C

GT

C

iv in

f

nfd

f

ninnoiseout

Using the weighting function(F S Goulding NIMA 1972 493-504)

Noise is measured just before the reset switch on

• Voltage noise is independent of switching time • Current noise is proportional to the switching time• If Strips are AC coupled Voltage noise is dominant whereas in DC coupled both (en and in)

contribute to the output noise • G0w0 : GBW of amplifier loaded by Cd and Cf

Equation 3 Equation 4

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 6

KTC noiseRf

Cd

-+

Cf

Votage Noise

1,

*1

1

G

G

CRCRj

Vin

Vout

Dfff

Switched closed : at the end of Reset noise is stored in Cf or in Cd+Cf

• Ideal amplifier (G=∞, w0=∞): no noise stored in Cd and v2=kT/Cf is transferred to the output during readout

• Poor amplifier : noise is stored on both Cf and Cd and v2=kT/(Cf+cd) will be amplified during readout

fd

ffd

fd C

C

C

kT

C

C

CC

kTV **

22

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 7

KTC noise

d

CRG

CR

kTRV

fondonon

0224

2

00

2

1

1*4*

2

1

Bandwidth amplifier > Bandwidth Ron*Cf (1/RonCf)22 42nV

C

kTV

f

Bandwidth amplifier < Bandwidth RonCf Ron=100Ω, G0=57dB, f0=1GHz

2002 7.1*2* µVC

RwGkTV

don

22

2 1.2** µVC

C

C

kT

C

C

CC

kTV

fd

ffd

fd

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 8

004

11 G

C

CK

fd

fCK

*4

12

HzAinRfRfK

vv

iRfoutnoiseRfoutnoise

n /,212

22

2,2

1,2

HzVinK

iRfKv

enRfoutnoise

n /,1

*2*22

222,2

Noise simulation (AC noise) has been made for 2 different Rf in non switched CSA, in and en can be extractedOuput noise is the sum of equation 1 and equation 2

K1 = 73.8E9 K2 = 2.5E12 (Cf = 0.1pF)in

2 = 5.85E-28 A2/Hzen

2 = 8.3E-18 V2/Hz

in= 24.2 fA/sqrtHz (eq 1.88 nA shot noise)en= 2.88 nV/sqrtHz ( eq 500 W resistor)

Vout, noise2 = 760 nV2 @ RF1 100 MW

Vout, noise2 = 615 nV2 @ RF2 1 MW

(760 nV2, Vout=74 mV, Qin=10fC ~ ENC = 730e-)

Eq 1 and 2Vout, noise

2 (en) = 612 nV2 @ RF1 100 MWVout, noise

2 (in) = 146 nV2 @ RF2 100 MWen is dominant noise source

Noise calculation

Noise simulation in AC mode and calculation for switched mode

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 9

Noise calculation in switched mode using :• en (computed in previous slide)

• in (computed in previous slide)

• equation 3 and 4

Vout, noise2 (en) = 610 nV2

Vout, noise2 (in) = 340 pV2

Total output noise = 610 nV2 = 780 µVVout = 74 mVENC = 658 e-

Tr_noise simulation :200 iterations Fmax = 5GHzVout measured @ 26 ns

Compute the standard deviation for all values picked @ 26ns

Total output noise = 738 µVVout = 74 mV ENC = 623 e-

2 ways to simulate noise in switched CSA:• TR_noise • Standard AC noise + calculation

Noise calculation

Calculation and TR_noise simulation in good agreement

TR_noise:• No noise summary• More CPU time• More reliable

AC Noise:• Increase by 20% of noise• Noise summary available• Less CPU time

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 10

Vout vs cdInput capacitor :Cd : 4.9 pF C(Cd + PCB + test socket) : 9 pFC(QFN package) : 0.5pFCesd input pad : 2pF

Total input capacitor : 12.5pF

63.72 mV

63.72 mV @ 10fCTin = 40ns

Gconv = 6.3 mV/fC(In agreement with test

6.2 mV/fC))

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 11

ENC vs Cd (AC noise simulation)

qCCe

GENC fdn

1****

4200

ENC (5pF, 100 M W ) = 730e-

ENC (15pF, 100 M W ) = 1260e-5pF < Cd < 15 pF

730e-

1260e-

26ns

Vout for ENC calculation

Vout = 74mVOutput Noise = 871µV

Vout = 70mVOutput Noise = 1.41mV

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 12

ENC vs Cd (TR noise simulation)

Cd = 5pFCd = 15 pF Tin = 26 ns, simulation time 50ns, 100 iterations

674e-

1363e-Vout @ 25 ns for ENC calculation

Vout = 55mVOutput Noise = 1.2mV

Vout = 71mVOutput Noise = 766µV

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 13

Cd = 5pFVout = 77 mVStddev = 1.25 mVENC = 1014 e-

Cd = 12.5pFVout = 64 mVStddev = 1.59 mVENC = 1552 e-

ENC vs Cd (TR noise simulation)

Tin = 26 ns, simulation time 10µs, 200 pulsesCd = 5pFCd = 15 pF

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 14

ENC vs Cd (TR noise simulation)

Cd = 12.5pFVout = 67 mVStddev = 1.62 mVENC = 1511 e-

Tin = 40 ns

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 15

Fclk = 15 MHz

Asic 3Reset

CSA Output

• CSA RMS Noise = 1.32 mV1600 e-

Tests Results - Noise

Qin = 0 Qin = 1.2 fC

Output Signal Dispersion

2 histograms lightly separated @ 15 MHzS/N = 7.5 (compared to 10 required)

• MIP : 1.2 fC• CSA RMS Noise = 1.32 mV1600 e-

Cd ~ 12.5pF (5 pf in simulation)ENC for 5pf will be 1600/sqrt(2.5) = 1 011 e-

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 16

ENC

Fclk = 15 Mhz(Tin = 40 ns)

ASIC 1 1302

ASIC 2 1396

ASIC 3 1595

ENC in e- @ 15 Mhz

ENC (simulated AC) @ 12.5pF = 1140 e- ENC (simulated TR noise n pulses, Tin = 26ns, sim time 50ns) @ 12.5pF = 1080e-ENC (simulated TR noise , Tin = 26ns, sim time 10µs) @ 12.5pF = 1552e- ENC (simulated TR noise Tin =40ns) @ 12.5pF = 1511 e-

H.Mathez– VLSI-FPGA-PCB IN2P3@ Lyon– June. 5-6-7, 2012 17

Conclusion

CSA works well @ 15 Mhz

Step in progess : increase performance (Speed, S/N, 40 MHz Clocking) ASIC with few channels (CSA, Comparators) : possible submission fall 2012

Both sensor polarities (holes or electrons) CSA @ 1.2 v & low temperature