cs649 sensor networks - department of computer sciencemchang/cs450/cs450.fa2013.week.02...images:...
TRANSCRIPT
![Page 1: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/1.jpg)
Network Embedded Systems
Sensor Networks – Fall 2013
Embedded Programming
Marcus Chang, [email protected]
1
![Page 2: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/2.jpg)
Embedded Systems
Integrated Components
Microcontroller Unit (MCU)
CPU
Volatile memory (e.g. RAM)
Persistent memory (e.g. Flash)
Peripherals:
Analog-to-Digital Converters (ADC)
Timers (counters, alarms, stop-watches)
SPI, I2C, UART
Radio
…
2
Intel 8742
Image: Ioan Sameli, Wikipedia
![Page 3: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/3.jpg)
MSP430F1611
3
![Page 4: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/4.jpg)
Blocking/Threading (vs. Event Driven) Function call that do not return until complete
External events can make this arbitrary long
… wget(www.google.com)
… getKey();
… read(file);
… write(file);
Non-Embedded Programming
4
![Page 5: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/5.jpg)
Blocking function calls
Each call suspends thread
Blocking/Threading vs. Event driven
5
read(file)
write(file)
<I/O done>
Thread Time
Running
Suspended, ready
Suspended, blocked
<OS reading>
<OS writing>
![Page 6: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/6.jpg)
Threading:
Blocking/Threading vs. Event driven
6
read(file)
getKey()
write(file)
<I/O done>
Thread 1 Thread 2
Context
switch
?
Running
Suspended, ready
Suspended, blocked
Time
![Page 7: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/7.jpg)
Blocking/Threading vs. Event driven
7
read(file)
getKey()
write(file)
OS Maintenance
/ Sleep
<I/O done>
<key pressed>
Thread 1 Thread 2 Idle
![Page 8: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/8.jpg)
Non-blocking calls
Multiple concurrent function calls
Explicit sleep
Blocking/Threading vs. Event driven
8
read(file)
write(file)
<read done>
<key pressed>
Main
getKey()
sleep()
sleep()
<write done>
![Page 9: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/9.jpg)
Polling (vs. Interrupts) Calling/waiting for non-blocking calls to change state
… while(getKey() == null) sleep(100);
… while(bufferIsEmpty() == true) ;
Polling vs. interrupts
9
![Page 10: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/10.jpg)
Polling vs. interrupts
10
End
Get character
Is there a
character?
Start Rx
Wait
Yes
No
Start Rx Interrupt
End Rx Interrupt
Get character
Sleep
Interrupt
![Page 11: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/11.jpg)
SP – Stack Pointer
TOS – Top of the stack
PC – Program Counter
SR – Status Register
Interrupt processing
11
read(file)
write(file)
<read done>
<key pressed>
Main
getKey()
sleep()
sleep()
<write done>
![Page 12: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/12.jpg)
SP – Stack Pointer
TOS – Top of the stack
PC – Program Counter
SR – Status Register
Interrupt Vector
12
read(file)
getKey()
write(file)
<I/O done>
<key pressed>
Main
getKey()
Source: Texas Instruments
Priority Address Module Register
![Page 13: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/13.jpg)
Interrupt Handler
Store function pointer in interrupt vector
void interrupt_signal_timer() {
// find reason for interrupt
if (TIMER_FLAG & TIMER_OVERFLOW_BIT)
// increment overflow counter
OVERFLOW_COUNTER++;
// zero out overflow interrupt flag
TIMER_FLAG &= ~TIMER_OVERFLOW_BIT;
}
13
![Page 14: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/14.jpg)
SP – Stack Pointer
TOS – Top of the stack
PC – Program Counter
SR – Status Register
Return from Interrupt
14
read(file)
write(file)
<read done>
<key pressed>
Main
getKey()
sleep()
sleep()
<write done>
![Page 15: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/15.jpg)
Race conditions
15
Problem:
Accessing the same variables in both main program and asynchronous interrupt context
Images: Frank Duignan
![Page 16: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/16.jpg)
Race conditions
16
Disable interrupts during atomic operations
Might miss interrupts!
Images: Frank Duignan
![Page 17: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/17.jpg)
Memory Map
17
Memory Mapped I/O
Peripheral modules are accessed as regular variables (pointers)
Flash read, extension of RAM
Flash write, ‘peripheral module’
Pros and cons
Global variables, no overhead
Buffer swapping
No memory protection
Images: Doina Bucur
![Page 18: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/18.jpg)
Memory Banking
Intel 8051 – billions units shipped per year (2008)
Original 8051 had 64 KiB address space Memory is accessed by addressing specific banks
18 Source: Texas Instruments
![Page 19: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/19.jpg)
Data types
Common data types:
char, short, int, long, float, etc.
But, the MSP430 is a 16-bit CPU
How big is a short? int? long? float? double?
Determined by the compiler
Specific data types (stdint.h): int8_t, uint8_t, int16_t, uint16_t, int32_t, uint32_t, int64_t, uint64_t
E.g. 12-bit ADC reading uint16_t
19
![Page 20: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/20.jpg)
Recap: GPIO
MCU datasheet
8 pins on each port, one bit each = 1 byte per port
E.g. set Port 1 pin 3 high:
P1OUT |= 0x04; // set value before direction to avoid outputting old value
P1DIR |= 0x04; // high means pin is output
20 Source: Texas Instruments
![Page 21: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/21.jpg)
Grace
Graphical Peripheral Configuration Tool
21 Image: 43oh.com
![Page 22: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/22.jpg)
Grace
Graphical Peripheral Configuration Tool
22 Image: 43oh.com
![Page 23: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/23.jpg)
Grace
Graphical Peripheral Configuration Tool
23 Image: 43oh.com
![Page 24: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/24.jpg)
Errata Sheet
24 Texas Instruments
![Page 25: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/25.jpg)
US15
25 Source: Texas Instruments
![Page 26: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/26.jpg)
CPU41
26 Source: Texas Instruments
![Page 27: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/27.jpg)
Assembly
Only when exact sequence matters
Flash write on CC2430 (8051 based MCU)
; Write 32-bit word from XDATA ; Assumes 32 MHz system clock is used ; CLR EAL ;mask interrupts C1: MOV A,FCTL ;wait until flash controller is ready JB ACC.7,C1 MOV FADDRH,#00h ;setup flash address high MOV FADDRL,#01h ;setup flash address low MOV FWT,#2Ah ;setup flash timing MOV FCTL,#02h ;set flash page write MOV FWDATA,#12h ;first byte MOV FWDATA,#34h ;second byte MOV FWDATA,#56h ;third byte MOV FWDATA,#78h ;fourth byte, initiates write
27
Code: Texas Instruments
![Page 28: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/28.jpg)
Boot Strap Loader
Flash upload program in protected memory
Enable BSL program with ‘secret handshake’
Erase Flash
Upload code
28 Image: Texas Instruments
![Page 29: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/29.jpg)
Universal asynchronous receiver/transmitter
MSP430 Registers
Control and Status
Enable
Communication format (I2C, SPI, UART)
Device status
Baud rate
Communication speed
Buffers
Rx and Tx
29 Images: Wikipedia
![Page 30: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/30.jpg)
#include <msp430x14x.h> static char string1[] = { "Hello World\n\r" }; char i; void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog P3SEL = 0x30; // P3.3,4 = USART0 TXD/RXD // Control registers ME1 |= UTXE0 + URXE0; // Enable USART0 module UCTL0 |= CHAR; // 8-bit character UTCTL0 |= SSEL0; // UCLK = ACLK UCTL0 &= ~SWRST; // Initialize USART state machine // Speed registers UBR00 = 0x03; // 9600 baud UBR10 = 0x00; // UMCTL0 = 0x4A; // IE1 |= URXIE0 + UTXIE0; //Enable RX/TX interrupt IFG1 &= ~UTXIFG0; // Clear initial flag on POR while(1) _BIS_SR(LPM3_bits + GIE); // Enter LPM3 w/ interrupt }
Hello World\n\r // UART0 TX ISR #pragma vector=USART0TX_VECTOR __interrupt void usart0_tx (void) { if (i < sizeof string1-1) TXBUF0 = string1[i++]; } // UART0 RX ISR #pragma vector=USART0RX_VECTOR __interrupt void usart0_rx (void) { if (RXBUF0 == 'u') // 'u' received? { i = 0; TXBUF0 = string1[i++]; } }
30
Code: Texas Instruments
![Page 31: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/31.jpg)
Operating Systems
Event-Driven
TinyOS
Bottom-up
Interrupt handling part of application
Event-Driven, Thread-based (co-operative)
Contiki
Context switch on blocking calls
Thread-based (pre-emptive)
FreeRTOS, eCos
Top-down
31
![Page 32: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/32.jpg)
TinyOS
System Architecture Directions for Networked Sensors By Jason Hill, Robert Szewczyk, Alec Woo, Seth Hollar, David
Culler, and Kristofer Pister
2000
32
![Page 33: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/33.jpg)
SMS messaging was first used in December 1992, when Neil Papworth, a 22-year-old test engineer for Sema Group used a personal computer to send the text message "Merry Christmas"
33
![Page 34: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/34.jpg)
Sensor network motes are
Highly application specific
Broad span in the design space
Problem
Sensor network specific operating system missing
Approach
Modular, micro-threaded OS
Context
34
![Page 35: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/35.jpg)
Small size, low power
Concurrency intensive
Limited hardware support
Diversity in design and usage
Robust operation
Sensor Network Characteristics
35
![Page 36: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/36.jpg)
Yet Another Mote
36
![Page 37: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/37.jpg)
MCU ? (2000) TelosB (2004)
ROM 8 KiB 48 KiB
RAM 512 B 10 KiB
Clock 4 MHz 8MHz
Power (active/idle) 5mA/2mA 2mA/1mA
Peripherals I2C, SPI, UART, ADC, Timers
Vs. TelosB
Radio TelosB
Speed 19.2 kbps 250 kbps
Type Bit 128 byte packets
Power (rx/tx) 4 mA / 12 mA 20 mA / 21 mA
37
![Page 38: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/38.jpg)
Meet sensor network characteristics AND run on mote-class device
TinyOS
Event driven
Two-level scheduling: Tasks and events
Scalable hardware/software boundary
No blocking functions or polling
(No dynamic memory)
Challenge
38
![Page 39: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/39.jpg)
Environmental Monitoring
Sample sensors
Store measurements
Transmit measurements
Forward other’s measurements
Running Example Application
39
![Page 40: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/40.jpg)
Modularized OS
40
Divide application and OS in components
Components
Self-contained
Well-defined interfaces (uses and provides)
Three layer abstraction:
Application
Hardware Independent Layer
Hardware Abstraction Layer
![Page 41: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/41.jpg)
Component Graph
41
![Page 42: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/42.jpg)
Interfaces
Provides (up)
Uses (down)
Mutators
Call command (down)
Signal event (up)
Tasks
Low priority
Functions, command calling, event signaling
Asynchronous events
High priority
Hardware interrupt handler
42
Components
![Page 43: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/43.jpg)
Concurrency
Tasks run atomically with regard to other tasks
Race conditions can be detected at compile time
Split-phase operation
Commands are non-blocking
E.g. call command ‘start’, signal event ‘startDone’
Modular
Code reuse
Flexible hardware/software boundary
43
“Surreal, but nice”
![Page 44: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/44.jpg)
44
void main( void )
{
...
while(1) {
while (taskQueue.notEmpty()) {
task = taskQueue.next();
task.run();
}
sleep();
}
...
void taskAdc() { ... };
void taskRadio() { ... };
void taskTimer() { ... };
...
void interruptTimer() { time = readTimer(); // 16-bit value taskQueue.insert(taskTimer); } void interruptAdc() { value = readAdc(); // 16-bit value taskQueue.insert(taskAdc); } void interruptRadio() { // 128 bytes packet - post task taskQueue.insert(taskRadio); }
Tasks Asynchronous Events
![Page 45: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/45.jpg)
Code Size
45
![Page 46: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/46.jpg)
178 bytes
SMS messaging was first used in December 1992, when Neil Papworth, a 22-year-old test engineer for Sema Group used a personal computer to send the text message "Merry Christmas“
SMS message
160 bytes
Contiki OS Kernel
810 bytes
How Tiny?
46
![Page 47: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/47.jpg)
TinyOS
Event driven OS
2-level scheduling (Tasks, Asynchronous Events)
Modular design
Component graph
Tradeoffs code complexity with high concurrency
47
Summary
![Page 48: CS649 Sensor Networks - Department of Computer Sciencemchang/cs450/CS450.FA2013.Week.02...Images: Doina Bucur Memory Banking Intel 8051 – billions units shipped per year (2008) Original](https://reader036.vdocuments.mx/reader036/viewer/2022081618/60b1962efa618c72983258dc/html5/thumbnails/48.jpg)
Schedule
48
Week 1: Introduction and Hardware
Week 2: Embedded Programming
Week 3: Medium Access Control
Week 4: Link Estimation and Tree Routing
Week 5: IP Networking
Week 6: Near Field Communication
Week 7: (seminar, no lecture)
Week 8: Energy Management
Week 9: Review and Midterm
Week 10: Time Synchronization
Week 11: Localization
Week 12: Energy Harvesting
Week 13: (seminar, no lecture)
Week 14: TBD