cs61c l23 combinational logic blocks (1) garcia, fall 2006 © ucb lecturer soe dan garcia ddgarcia...
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CS61C L23 Combinational Logic Blocks (1) Garcia, Fall 2006 © UCB
Lecturer SOE Dan Garcia
www.cs.berkeley.edu/~ddgarcia
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures
Lecture 23 – Combinational Logic Blocks
Close call! Cal squeakedby Washington
in Overtime 31-24. We win, and then we drop a spot in
the polls. Yikes! UCLA soon. calbears.cstv.com
QuickTime™ and aTIFF (Uncompressed) decompressor
are needed to see this picture.
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CS61C L23 Combinational Logic Blocks (2) Garcia, Fall 2006 © UCB
Review
•Use this table and techniques we learned to transform from 1 to another
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CS61C L23 Combinational Logic Blocks (3) Garcia, Fall 2006 © UCB
Today
•Data Multiplexors
•Arithmetic and Logic Unit
•Adder/Subtractor
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CS61C L23 Combinational Logic Blocks (4) Garcia, Fall 2006 © UCB
Data Multiplexor (here 2-to-1, n-bit-wide)
“mux”
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CS61C L23 Combinational Logic Blocks (5) Garcia, Fall 2006 © UCB
N instances of 1-bit-wide mux
How many rows in TT?
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CS61C L23 Combinational Logic Blocks (6) Garcia, Fall 2006 © UCB
How do we build a 1-bit-wide mux?
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CS61C L23 Combinational Logic Blocks (7) Garcia, Fall 2006 © UCB
4-to-1 Multiplexor?
How many rows in TT?
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CS61C L23 Combinational Logic Blocks (8) Garcia, Fall 2006 © UCB
Is there any other way to do it?
Hint: NCAA tourney!
Ans: Hierarchically!
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CS61C L23 Combinational Logic Blocks (9) Garcia, Fall 2006 © UCB
Administrivia
•HW due wednesday
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CS61C L23 Combinational Logic Blocks (10) Garcia, Fall 2006 © UCB
Arithmetic and Logic Unit
•Most processors contain a special logic block called “Arithmetic and Logic Unit” (ALU)
•We’ll show you an easy one that does ADD, SUB, bitwise AND, bitwise OR
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CS61C L23 Combinational Logic Blocks (11) Garcia, Fall 2006 © UCB
Our simple ALU
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CS61C L23 Combinational Logic Blocks (12) Garcia, Fall 2006 © UCB
Adder/Subtracter Design -- how?• Truth-table, then
determine canonical form, then minimize and implement as we’ve seen before
• Look at breaking the problem down into smaller pieces that we can cascade or hierarchically layer
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CS61C L23 Combinational Logic Blocks (13) Garcia, Fall 2006 © UCB
Adder/Subtracter – One-bit adder LSB…
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CS61C L23 Combinational Logic Blocks (14) Garcia, Fall 2006 © UCB
Adder/Subtracter – One-bit adder (1/2)…
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CS61C L23 Combinational Logic Blocks (15) Garcia, Fall 2006 © UCB
Adder/Subtracter – One-bit adder (2/2)…
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CS61C L23 Combinational Logic Blocks (16) Garcia, Fall 2006 © UCB
N 1-bit adders 1 N-bit adder
What about overflow?Overflow = cn?
+ + +
b0
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CS61C L23 Combinational Logic Blocks (17) Garcia, Fall 2006 © UCB
What about overflow?•Consider a 2-bit signed # & overflow:•10 = -2 + -2 or -1•11 = -1 + -2 only•00 = 0 NOTHING!•01 = 1 + 1 only
•Highest adder•C1 = Carry-in = Cin, C2 = Carry-out = Cout
•No Cout or Cin NO overflow!
•Cin, and Cout NO overflow!
•Cin, but no Cout A,B both > 0, overflow!
•Cout, but no Cin A,B both < 0, overflow!
± #
Whatop?
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CS61C L23 Combinational Logic Blocks (18) Garcia, Fall 2006 © UCB
What about overflow?•Consider a 2-bit signed # & overflow:
10 = -2 + -2 or -111 = -1 + -2 only00 = 0 NOTHING!01 = 1 + 1 only
•Overflows when…•Cin, but no Cout A,B both > 0, overflow!
•Cout, but no Cin A,B both < 0, overflow!
± #
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CS61C L23 Combinational Logic Blocks (19) Garcia, Fall 2006 © UCB
Extremely Clever Subtractor
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CS61C L23 Combinational Logic Blocks (20) Garcia, Fall 2006 © UCB
Peer Instruction
A. Truth table for mux with 4-bits of signals has 24 rows
B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl
C. If 1-bit adder delay is T, the N-bit adder delay would also be T
ABC1: FFF2: FFT 3: FTF4: FTT5: TFF6: TFT7: TTF8: TTT
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CS61C L23 Combinational Logic Blocks (21) Garcia, Fall 2006 © UCB
Peer Instruction Answer
A. Truth table for mux with 4-bits of signals is 24 rows long
B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl
C. If 1-bit adder delay is T, the N-bit adder delay would also be T
ABC1: FFF2: FFT 3: FTF4: FTT5: TFF6: TFT7: TTF8: TTT
A. Truth table for mux with 4-bits of signals controls 16 inputs, for a total of 20 inputs, so truth table is 220 rows…FALSE
B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl … TRUE
C. What about the cascading carry? FALSE
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CS61C L23 Combinational Logic Blocks (22) Garcia, Fall 2006 © UCB
“And In conclusion…”•Use muxes to select among input•S input bits selects 2S inputs
•Each input can be n-bits wide, indep of S
• Implement muxes hierarchically
•ALU can be implemented using a mux•Coupled with basic block elements
•N-bit adder-subtractor done using N 1-bit adders with XOR gates on input•XOR serves as conditional inverter