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CS552Operating Systems

z/390

Basic Assembler Language

Programming

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Architecture

• CISC– Complex Instruction Set Computer– Multiple operands per instruction

• Multiple instruction formats• 64 bit architecture,

– Instr set is variable• 32-bit• 64-bit

– 32 bit instructions work on low-order

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I/O & State

• Subchannels– Allow for variability of path to device– Use a "control block" for access

• Program Status Word– Interruptability (on/off)– Privilege mode (on/off)– Wait state (on/off)– Next instruction

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Format Terms

• Op operation code (8 bits)• R1, R2, R3 register number 0-F (8 bits)• B register used as address

base• X register used as an index• DDD 0-FFF 12-bit disp. from base• M,I 8-bit, mask or immediate

data• LL length of data

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Instruction Architecture

Most-used formats

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RR Format

• Example:AR 5,14

– Adds the contents of Reg 14 to the contents of Reg 5– results in Reg 5– No memory references involved

• Note: examples show Regs as decimal values, but Assembler converts them to Hexadecimal

• In memory, this instruction looks like:1A5E

Op R1 R2

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RX Format

• Memory address is:– content of X– + content of B– + value DDD

• Example:– L Load - Opcode X'58'– L R,DDD(B,X)– L 4,mydata(12)

• Result replaces value in R– If "mydata" is at offset X'23' from Reg 5, which holds X'0E00', then, in

memory, this will look like:

584C5023– Mydata becomes a "starting point, and the content of Reg 12 is added to it

as an "index" - nice for table accesses

Op R X BDDD

+

Arrows reverse for store operations

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RS Format

• Memory address:– content of B– + value DDD

• Example:– LM Load Multiple - Opcode X'98'– LM R1,R2,DDD(B)– LM 4,7,mydata

• Result: Loads all registers from R1 to R2, from data at "mydata"– If "mydata" is at offset X'23' from Reg 5, which holds X'0E00', then, in

memory, this will look like:

98475023– Note: "wrap-around" of register numbers is legal

• Ex: LM 14,12 loads regs 14, 15, 0,1,2,…,12 inclusive

Op R1 R2 BDDD

Arrows reverse for store operations

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SI Format

• Performs "Op" using the instruction content itself (Imm) as data. That is, no additional memory reference is done.)

• Example:– N And Immediate - Opcode X'94'– N DDD(B),I– N mydata,X'0A'If "mydata" is at offset X'23' from Reg 5, which holds X'0E00',

then, in memory, this will look like:940A5023

Note: when writing the instruction, the memory ref comes 1st, FOLLOWED BY the Imm data!

Op Imm BDDD

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SS Format

• Memory address is:– + content of Bn

– + value DDDn

• Example:– MVC Move Characters - Opcode X'D2'

– MVC DDD1(B1,LL),DDD2(B2)

– MVC yourdata(23),mydata 23=X'17'

• Result replaces value in B1DDD1

– "mydata" is at offset X'02' from Reg 5 (X'0E00')– "yourdata" is at offset X'55' from Reg 8 (X'1F00')– then, in memory, this will look like:

– D21750028055

Op LL B1DDD1 B2DDD2

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Writing a Program

Assembler directives

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Module Definitions

• CSECT - externally known module– Named or unnamed– Linkable object

• Could be a compilation result• Contains program code or data

• DSECT - externally known "dummy" module– Used to define offsets– Like a "C" 'struct' with a pointer

• Both ended by another C/DSECT or END

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Storage Specification

• DC Define Constant– Hex, character, decimal formats– Contains the actual "constants"– Constants are NOT protected

• DS Define Storage– Allows for "reserving" an area– No pre-defined value, NOT zeroed out!!!

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Storage Specification 2

• Op [m] {attrib1} [Ln] '{value}'• Op [m] {attrib2} [Ln] ({value})

– m is a repetition factor (0 is valid)– n is a length (per element)

• Attrib values– Attrib1 X, C, H, F, D ,B– Attrib2 A, S

• ExamplesDS 0CL5 uses no memory

DC 3XL3'25' 000025000025000025

DC A(mydata) 4-byte, aligned, address

DC S(mydata) converts to base/disp notation

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Setting a Base Address

• Special instruction: BALR R1,R2

• At EXECUTION time, – R1 will receive the address of the NEXT inst

in memory following the BALR itself– A branch (jump) will be taken to the address

in R2 (call/return semantics)• IF R2 is register 0, no branch is taken!!!

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Base Register Specification• USING Tells assembler which reg to use for names

– Register to use as Base– Generates NO code (takes no space in memory)

• Example:BALR 12,0 12 has addr of "go"

USING *,12 go MVC Data1(5),Data2Data1 DC C'target location'Data2 DC C'Source location'

• Data1 is 6 bytes from "go"– The * means: "starting here" and the MVC is 6 bytes long– Could have said: USING go,12

• If Reg 12 has address of "go", then data1 will be 6 bytes from Reg 12• YOU must put the correct memory address into the Base Reg• DROP terminates use of a register for name addressability

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Naming

• EQU "equates" a name to a location or value• Example:

– Data1 DC X'010203' length attr=1» Because no length was explicitly given

– Data2 DC XL3'010203' length attr=3– Hextwo EQU Data2+1– K5 EQU 5

– Hextwo now refers to the location of 02 inside Data1– BE CAREFUL: since the target of Hextwo is in a

string of length 3, hextwo has a length 'attribute' = 3– K5 has a numeric value of 5 - uses NO memory

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Ending the Program Definition

• END – tells assembler "end of program"– Generates NO code. It is NOT a "return"

Comments• An * placed in column 1 of any line

– tells assembler "ignore this line"

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I/O

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I/O

• Basic I/O instructions– SSCH Start Sub-Channel– TSCH Test " - clears pending

interrupts

• Operand (SSCH/TSCH) points to an ORB – control block– Specifies additional info

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ORB layout

Word# Usage

0 Interruption Parameter

1 Key SCMYFPIAU0HT LPM LD00000X

2 Channel-Program Address (address of 1st CCW in chain)

3 CSS Priority

Res CU priority

Res

4-7 Reserved

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I/O Programming

• Setup the ORB

• Setup the interrupt handler

• Setup address of nsi in PSW to be loaded

• Setup low memory – (I/O new & PGM new PSW's)

• Ssch

• Enable interrupts

• Wait for interrupt

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General Programming Concepts

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IBM Application Conventions

• All APPLICATION programs return to caller via Reg 14

• All programs save their caller's registers in an area pointed-to by Reg 13, STARTING WITH Reg 14

• Example:– STM 14,12,12(13)

• saves callers regs 14, 15, 0,1, 2…12 in an area addressed by Reg 13+12

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Application conventions -2Save Area Chaining: USING *,15 called via R15MYPG STM 14,12,12(13) save caller's regs

ST 13, mysave+4 Set BACK-ptrLR 14,13 pt to caller's areaLA 13,mysaveST 13,8(0,14) set FWD-ptrLA 12,MYPG change to R12USING MYPG,12 tell assembler L 13,MYSAVE+4 restore caller regsLM 14,12,12(13)BR 14 return to callerEND

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Application conventions -2

• Macros• Expand into actual inline code• Save writing and remembering• NOT a function call• Examples:

– Save (14,12)– Return (14,12)– Generate the red-colored code on previous

slide

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O/S Programs

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Structure

• Privileged

• No save-area chaining

• No "runtime" libraries

• Two styles:– Monolithic - one complete linked file– Modular

• multiple files, • dynamically loaded files

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Context Management

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Reserved Memory

• Page 0 is Reserved storage for O/S

• Accessible only in privileged mode

• Uses base register 0– "treated" by hardware as if = zero

• Same layout as real page 0

• 4096 bytes (addresses 0-FFF)– Only needs 12 bits, no base register value

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Hex

AddressPurpose(all PSW's: 8 bytes each)

0 Initial PSW

8 Initial CCW1

10 Initial CCW2

18-3F Old PSW's (Ext, SVC, Pgm, Mck, I/O)

58-7F New PSW's ( '' )

86-89 Interrupt codes (ext, svc, pgm) 2 Bytes each

BC-BF I/O int parameter (4 bytes)

C0-FF Reserved

0100 1st byte of O/S or Program

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Boot Sequence• ROM forces an I/O read:

– 24 bytes from Cyl 0, Hd 0, Rec 0– Into loc 0, with chaining to loc 8 – These 24 bytes contain

• PSW 0 state vector w/Addr of 1st byte of pgm• CCW1 Read more data• CCW2 And more data

• CCW Chaining continues at loc 8• At end of data, PSW is loaded• Execution begins

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Program State Management

• LPSW - Load Program Status Word– Loads address of NSI– Sets privilege mode for NSI– Sets wait state on/off for NSI– Enables/disables interrupts for NSI– Sets memory protection mask for NSI

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VM Simulation

• Boot minidisk formatted as a CMS disk– Not a free-standing drive– Temp disk is usable

• O/S module created in CMS• O/S file copied to boot disk• Stand-Alone Program Loader (SAPL) installed

on boot using SAPIPL• When drive is booted, SAPL loads the O/S• O/S may then use any volumes (but must either

create a file system or use CMS file system

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Using VM

Some CP & CMS commands

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What is VM?

• A virtual environment– Minidisks– Virtual devices (some are true simulations)– Spool management (prt, con)– Real-system resource mgr– Privilege-mode emulator for virtual machines– Allows a user to

• Invoke ALL real hw instructions in a program• Boot an O/S - existing or roll-your-own

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What is VM? - 2

• Two components– CP the Control Program or Hypervisor

• Does all real I/O, paging, scheduling• Manages virtual devices (disks, consoles, etc)

– CMS the "shell" that comes with VM• File system• Program management

– No multi-threading – No multi-programming

• Extensive s/w development & file mgmt commands

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Program creation

• Xedit text mode editor– Command line for issuing commands

• HLASM translates assembler source– Hlasm myos

• LOAD collects compiled files– Load myos (RLDSAVE– RLDSAVE keeps relocation dictionary in file for SAPL

• GENMOD link-edits the LOADed files– Gen myos

• Scripting language: REXX

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Booting your own system

• Define T3390 as vaddr cyl n• Format vaddr modeletter • Format vaddr modeletter n-1 (recomp• Salipl vaddr (origin xxxx mod myos• #CP IPL vaddr

– Need the #CP to avoid terminal type problems• Returning to the CMS shell

– #CP IPL CMS• Modeletter:

– A-Z, same as a PC– Defines path for files AND writeability of drive

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Display

• Displays contents of memory, regs, PSW – in hex and char format

• ExampleDisplay 0 100 200

displays 3 locations

Display 0-200

displays x'0' through x'200'

Display P

displays the current PSW