University of Texas at Austin CS352H - Computer Systems Architecture Fall 2009 Don Fussell

CS352H: Computer Systems Architecture

Topic 8: MIPS Pipelined Implementation

September 29, 2009

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MIPS Pipeline

Five stages, one step per stageIF: Instruction fetch from memoryID: Instruction decode & register readEX: Execute operation or calculate addressMEM: Access memory operandWB: Write result back to register

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Pipeline Performance

Assume time for stages is100ps for register read or write200ps for other stages

Compare pipelined datapath with single-cycle datapath

200ps200psj

500ps200ps100 ps200psbeq

600ps100 ps200ps100 ps200psR-format

700ps200ps200ps100 ps200pssw

800ps100 ps200ps200ps100 ps200pslw

Total timeRegisterwrite

Memoryaccess

ALU opRegisterread

Instr fetchInstr

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Pipeline Performance

Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

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Pipeline Speedup

If all stages are balancedi.e., all take the same timeTime between instructionspipelined

= Time between instructionsnonpipelined

Number of stages

If not balanced, speedup is lessSpeedup due to increased throughput

Latency (time for each instruction) does not decrease

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Pipelining and ISA Design

MIPS ISA designed for pipeliningAll instructions are 32-bits

Easier to fetch and decode in one cyclec.f. x86: 1- to 17-byte instructions

Few and regular instruction formatsCan decode and read registers in one step

Load/store addressingCan calculate address in 3rd stage, access memory in 4th stage

Alignment of memory operandsMemory access takes only one cycle

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Hazards

Situations that prevent starting the next instruction in thenext cycleStructure hazards

A required resource is busyData hazard

Need to wait for previous instruction to complete its dataread/write

Control hazardDeciding on control action depends on previous instruction

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Structure Hazards

Conflict for use of a resourceIn MIPS pipeline with a single memory

Load/store requires data accessInstruction fetch would have to stall for that cycle

Would cause a pipeline “bubble”

Hence, pipelined datapaths require separateinstruction/data memories

Or separate instruction/data caches

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Data Hazards

An instruction depends on completion of data access by aprevious instruction

add $s0, $t0, $t1sub $t2, $s0, $t3

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Forwarding (aka Bypassing)

Use result when it is computedDon’t wait for it to be stored in a registerRequires extra connections in the datapath

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Load-Use Data Hazard

Can’t always avoid stalls by forwardingIf value not computed when neededCan’t forward backward in time!

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Code Scheduling to Avoid Stalls

Reorder code to avoid use of load result in the nextinstructionC code for A = B + E; C = B + F;

lw $t1, 0($t0)lw $t2, 4($t0)add $t3, $t1, $t2sw $t3, 12($t0)lw $t4, 8($t0)add $t5, $t1, $t4sw $t5, 16($t0)

stall

stall

lw $t1, 0($t0)lw $t2, 4($t0)lw $t4, 8($t0)add $t3, $t1, $t2sw $t3, 12($t0)add $t5, $t1, $t4sw $t5, 16($t0)

11 cycles13 cycles

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Control Hazards

Branch determines flow of controlFetching next instruction depends on branch outcomePipeline can’t always fetch correct instruction

Still working on ID stage of branch

In MIPS pipelineNeed to compare registers and compute target early in the pipelineAdd hardware to do it in ID stage

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Stall on Branch

Wait until branch outcome determined before fetching nextinstruction

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Branch Prediction

Longer pipelines can’t readily determine branch outcomeearly

Stall penalty becomes unacceptable

Predict outcome of branchOnly stall if prediction is wrong

In MIPS pipelineCan predict branches not takenFetch instruction after branch, with no delay

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MIPS with Predict Not Taken

Predictioncorrect

Predictionincorrect

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More-Realistic Branch Prediction

Static branch predictionBased on typical branch behaviorExample: loop and if-statement branches

Predict backward branches takenPredict forward branches not taken

Dynamic branch predictionHardware measures actual branch behavior

e.g., record recent history of each branch

Assume future behavior will continue the trendWhen wrong, stall while re-fetching, and update history

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Pipeline Summary

Pipelining improves performance by increasing instructionthroughput

Executes multiple instructions in parallelEach instruction has the same latency

Subject to hazardsStructure, data, control

Instruction set design affects complexity of pipelineimplementation

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MIPS Pipelined Datapath

WB

MEM

Right-to-leftflow leads tohazards

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Pipeline registers

Need registers between stagesTo hold information produced in previous cycle

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Pipeline Operation

Cycle-by-cycle flow of instructions through the pipelineddatapath

“Single-clock-cycle” pipeline diagramShows pipeline usage in a single cycleHighlight resources used

c.f. “multi-clock-cycle” diagramGraph of operation over time

We’ll look at “single-clock-cycle” diagrams for load &store

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IF for Load, Store, …

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ID for Load, Store, …

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EX for Load

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MEM for Load

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WB for Load

Wrongregisternumber

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Corrected Datapath for Load

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EX for Store

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MEM for Store

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WB for Store

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Multi-Cycle Pipeline Diagram

Form showing resource usage

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Multi-Cycle Pipeline Diagram

Traditional form

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Single-Cycle Pipeline Diagram

State of pipeline in a given cycle

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Pipelined Control (Simplified)

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Pipelined Control

Control signals derived from instructionAs in single-cycle implementation

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Pipelined Control

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Concluding Remarks

ISA influences design of datapath and controlDatapath and control influence design of ISAPipelining improves instruction throughputusing parallelism

More instructions completed per secondLatency for each instruction not reduced

Hazards: structural, data, control